Output Prediction Logic: A High Performance CMOS Design ...

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Delays for an 8-Gate (FO of 4) Heterogeneous Critical Path • NOR3, NAND3, AOI22, INV, INV, NOR3, NAND3, and AOI22 • Having the gates so ordered means that each gate type will have to pull down once and stay high once • Each gate drives a load of four identical gates • The device sizes used were exactly those selected for the uniform chains Logic Family Delay Speedup Static CMOS 2.13ns 1.0 OPL-static 910ps 2.34 OPL-pseudo 650ps 3.28 OPL-dynamic 688ps 3.10
Delays for Two Implementations a 32-bit Carry Look-Ahead Adder Logic Family Delay Speedup CLA type Static CMOS 3.0ns 1.0 Three levels OPL-static 1.5ns 2.0 Three levels OPL-pseudo 1.8ns 1.65 Three levels OPL-pseudo 552ps 5.43 Two levels • First three designs used all NAND gates; last one is all NOR gates
Page 1 and 2: Output Prediction Logic: A High Per
Page 3 and 4: Background • Dynamic circuit fami
Page 5 and 6: Why Static CMOS is So Slow • All
Page 7 and 8: Output Prediction Logic • Problem
Page 9 and 10: OPL Pseudo-nMOS Gate • Tri-state,
Page 11 and 12: OPL Clocking 1 1 1 1 gate1 gate2 ga
Page 13 and 14: OPL Clocking • When a clock arriv
Page 15 and 16: VDD GND clk in a. Early Clock out O
Page 17 and 18: 3 2.5 2 1.5 1 0.5 0 Waveforms for O
Page 19 and 20: Measuring Delays for OPL • For ea
Page 21 and 22: 10-Gate Critical Path Delays (FO of
Page 23: Energy Consumption Chain Type Stati
Page 27 and 28: Delays for ISCAS Random Logic Bench
Page 29 and 30: Domino CVSL Gate Logic Inputs CLK C
Page 31 and 32: Delays (ns) for Chains of 10 Gates
Page 33 and 34: Long Wire With Noise Injection
Page 35 and 36: Delays of OPL-dyn. AOI22 Chains inc
Page 37 and 38: Gclk Clock Generation clk1 clk2 •
Page 39 and 40: Ultra High Speed Adder Design • U
Page 41 and 42: 8-Bit Sum using Carry Select Sum 7
Page 43 and 44: 64-bit Adder: Statistical Analysis
Page 45: OPL Summary • OPL appears to be f

Output Prediction Logic: A High Performance CMOS Design ...

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