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Implementing an IEEE 1588 V2 Node on the ColdFire MCF5441x ...

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<str<strong>on</strong>g>IEEE</str<strong>on</strong>g><str<strong>on</strong>g>1588</str<strong>on</strong>g> demo<br />

5.2 Measuring <strong>the</strong> clock synchr<strong>on</strong>icity<br />

To measure <strong>the</strong> synchr<strong>on</strong>icity of <strong>the</strong> clocks, <strong>the</strong> MCF54418 provides <str<strong>on</strong>g>an</str<strong>on</strong>g> opti<strong>on</strong> for generating a<br />

pulse-per-sec<strong>on</strong>d (PPS) signal. This signal is generated directly from <strong>the</strong> <str<strong>on</strong>g>1588</str<strong>on</strong>g> timer <str<strong>on</strong>g>an</str<strong>on</strong>g>d is routed to <strong>the</strong><br />

GPIO PD0 pin (signal name T1IN/PWM_EXTA1/T1OUT/SDHC_DAT1/ GPIOD0/RGPIO). This GPIO<br />

pin is routed to <strong>the</strong> J8-34 (J8-33) pin <strong>on</strong> <strong>the</strong> primary TWR-ELEV board of <strong>the</strong> tower system.<br />

To measure <str<strong>on</strong>g>an</str<strong>on</strong>g>d compare PPS signals from different boards, attach <strong>the</strong> oscilloscope probe to <strong>the</strong> J8-34<br />

(J8-33) pin of <strong>the</strong> primary TWR-ELEV board. Figure 19 illustrates clock synchr<strong>on</strong>icity measurement<br />

using <strong>the</strong> oscilloscope.<br />

To measure <strong>the</strong> clock synchr<strong>on</strong>izati<strong>on</strong> accuracy, a test was performed between two TWR-MCF54418-KITs<br />

c<strong>on</strong>nected back-to-back. Table 6 summarizes <strong>the</strong> c<strong>on</strong>figurati<strong>on</strong> of <strong>the</strong> IXXAT <str<strong>on</strong>g>1588</str<strong>on</strong>g> <str<strong>on</strong>g>V2</str<strong>on</strong>g> stack used for<br />

testing:<br />

26<br />

Table 6. <str<strong>on</strong>g>1588</str<strong>on</strong>g> stack c<strong>on</strong>figurati<strong>on</strong> for clock synchr<strong>on</strong>izati<strong>on</strong> accuracy Testing<br />

<str<strong>on</strong>g>1588</str<strong>on</strong>g> c<strong>on</strong>figurati<strong>on</strong> Assigned value<br />

Clock basic type Boundary Clock<br />

Delay request mech<str<strong>on</strong>g>an</str<strong>on</strong>g>ism End-to-End<br />

One-step mode False<br />

Announce message interval 2 sec<strong>on</strong>ds<br />

Sync message interval 0.25 sec<strong>on</strong>ds<br />

Delay request interval 0.25 sec<strong>on</strong>ds<br />

Used filter Minimum filter<br />

Filter window length 6<br />

Measurement period 0.5 hours<br />

The results of <strong>the</strong> clock synchr<strong>on</strong>izati<strong>on</strong> accuracy test are provided below, see Table 7.<br />

Table 7. Clock synchr<strong>on</strong>izati<strong>on</strong> accuracy test results<br />

Average clock offset –2.18 ns<br />

St<str<strong>on</strong>g>an</str<strong>on</strong>g>dard deviati<strong>on</strong> 13.88 ns<br />

Peak-to-peak r<str<strong>on</strong>g>an</str<strong>on</strong>g>ge –62ns to +62 ns<br />

<str<strong>on</strong>g>Implementing</str<strong>on</strong>g> <str<strong>on</strong>g>an</str<strong>on</strong>g> <str<strong>on</strong>g>IEEE</str<strong>on</strong>g> <str<strong>on</strong>g>1588</str<strong>on</strong>g> <str<strong>on</strong>g>V2</str<strong>on</strong>g> <str<strong>on</strong>g>Node</str<strong>on</strong>g> <strong>on</strong> <strong>the</strong> MCF5441X, Rev. 0<br />

Freescale Semic<strong>on</strong>ductor

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