T - BVU College of Engineering, Pune, India

Sharada Kale and Shinde
full-scan (Figure 3). In a circuit with a lot of
sequential feedback and thereby the: length of the
sequences cannot be bounded it is not advisable
to use scan flip-flops. In particular parts of the
design where timing is critical it can also be
advisable to not using scan flip-flops. In these
cases the design is called partial scan. When this
type of design is run through an ATI'G-tool it
may cause loss of fault coverage. increased
runtime and an increase in the number of tc"S(
vector generated.
3-3. Multiple Scan Chains
If many flip-flops are used in a design a
single scan chain can become too large. It call
take very long time to load each state with a very
long scan chain. Splitting the chain in more scan
chains can solve this. The trade-offs of this
solution is that multiple scan chain." requires
more dedicated (cest pins. If multiple scan chains
are used the scan chains should have the same
number of scan bits as far as possible this IS
called balanced scan chains.
This is the rncst cost efficient method and it
uses the memory more efficient
3.4. Scan Design Rules
The 'e are many rules of for designing a
scan-based design among allthcsc four is useful:
• Use only one kind of flip.flop in the design.
E.g. D-type:master-slave.
• At least one primary input pin must be
available for test.
• .Every flip-flop clock must be controllable
from primary inputs.
• Avoid synchronous latches, transparent
latches.
• Do not feed clock to data inputs of f1ip- flops
4. Built in Self Test
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iconADELCO 2007
Since circuits become more dense and faster
with smaller size and that the logic-to-pin ratio
on chips is increasing makes the testing of logic
morc and more difficult. It takes longer time to
generate test patterns and the patterns consume
lot of memory. Often are the designers not aware
of the gate-level structure of their designs
because it is synthesized in VHDL hardware
description languages. Therefore it has becoming
interesting to implement different kind of logic
in the design so it can test itself so called BIST.
Figure 4. Built in self test (3]
The idea of BIST is to implement test
pattern generation and response analyzing and
even fault analyzing together with the chip. BIST
(Figure 4) can be categorized in different ways:
Online IlIST: Testing is done during normal
operation
• Concurrent testing - detects faults while
system is doing normal functions..
e Nun-Concurrent testing - detects faults
while system is in idle mode.
Offline BIST: System is brought 10 a test
mode
e. functional testing - tests the system at a
high level of function.
e Structural testing - detects structural faults
of the system.
4.1. BIST Pattern Generation