T - BVU College of Engineering, Pune, India

Proceedings of the 

international conference on ADvances in Electronics and COnununicarions (iconAOELCO 2(07) 

National Engineering College, Kovilpatti. Tamilnadu, India. Feb.I-J. 2007. pp. 249 - 256 

Design for Testability 

Sharada D.Kale t and Shinde.A.A 1 

IBharati Vidyapeetb's College of Engineering for Women. Pune. 

}Bharati Vidyapeetli's College of Engineering. Pune. 

'sharada.kale@gmail.com 

AbstrQCt - When designing and manufacturing 

electronics today testing is essential. When the 

designs are getting smaller and aore complex 

more effort is applied to the test engineer to test 

the products with high fault coverage and at a 

fast rate: It is therefore essential to think of test 

already in the design phase of the product. This 

paper will try to explain the concept of Design 

for testability (DF7) and explain the most used 

techniques today. Boundary Scan. Built in Self- 

Test and Scan Design. A discussion is also 17UJde 

in how the cost of implementing these method,' 

looks like. 

Keywords: Design for testability, OFT, Ad-hoc 

OFT, Structured OFT, Scan design, Built in selftest 

(BI51), Boundary scan and Cost model 

I. Introduction 

What is Design for testability? - Test is not 

a task that is without prepararion; (0 pn:parc a 

(k~i~1I fur Icst requires 11~lt lloc Iksigu have " 

good proportion of testability. With rcstabiluy 

we mean how easy it is to generate test vectors 

that have good fault coverage. II is also 

imperative that these methods are financial 

profitable in cost and quality. Two u~ljllr 

keywords in test arc controllability and 

observability. Controllability means that you 

could control every node in the design to all 

possible values that are imperative to test a node. 

Observability means that with different methods 

every node can be measured and tested (Jl. 

Design for testability (OFT) is an operation 

that is carried out in parallel with the design of 

the product; this involves modifying the design 

in such way that maximum controllability and 

observabiliry is attained This is done by using 

good design practices that is called Ad-Hoc OFT 

and by structural OFT, w!tieh is done by adding 

extra hardware to the design. 

This paper will try to give an insight in 

Design for Testability (OFT) and will focus on 

methods mainly used for digital circuits. The 

main methods discussed are Scan Design, Built 

in Self-Test and Boundary Scan. A discussion is 

also made in the benefits and trade-off of OFT 

and how the cost has an impact on the decision. 

2. Non-structured OFT and Ad-hoc 

OFT 

I"Of small and less complex designs the 

methods for testing could include bed-of-nails 

testers, ATfi-testers with conventional 

instruments and so forth, So the DFT methods 

lor this typc or design should not be 10(1 

expensive and time consuming. Arnong these 

methods there arc design rules how to design 

printed circuit boards so they can be tested with

Sharada Kale and Shinde 

bed-of-nail testers as well as general design rules 

how to design a circuit so that it is easier to 

test (I). 

2.1. Design Rules for PCBs 

On a PCB almost all errors is of the type 

shorts or opens. To detect short between 

networtcs, one must access each net at a single 

point, which can be chosen at the must 

convenient point. To detect opens each net-end 

must be accessed. this test is the most difficult 

for a bed-of-nails tester. 

Insulation test - It is essential that each net 

have at least one access on each net where the 

nail or probe can be placed. Continuity test - At 

the end of each net an access point mU~1be place 

to make it possible to test all opens. If possible 

avoid using packages with to small pitch which 

makes it harder to get test points within a 

reasonable distance. Also if possible avoid 

placing two or more dense component close to 

each other and also try to place them on the 

periphery of the board. 

2.2. Ad-hoc DFT 

Ad-hoc design for testability relies on 

"good' design practices learnt through 

experience are used as guidelines: 

• Avoid asynchronous (un-clocked) feedback. 

• Make flip-flops initializable 

• A void redundant gates. A void large 1;111ill 

gates. 

• Provide test control for difficult-to-control 

signals. 

• A void gated clocks. 

• Consider ATE requirements (tristarcs. ctc.) 

• Separate digital circuitry from analogue. 

• Divide large logic blocks into smaller ones, 

which can N: selected. 

• Avoid circuitry with large sequential depth. 

~' \ 

250 

iconADELCO 2007 

These techniques can be used for small 

designs but when designs get bigger the design is 

hard to get an overview of and these methods are 

approximate and do not always point to the 

source of the testability problem. 

As the size and complexity of digital 

systems are getting larger alternative forms of 

design for testability is getting popular. These 

methods are called structured OFT_ In structured 

OFT extra logic is included in the design to 

easily test a circuit. Among these methods scan 

design, Built in Self-Test and Boundary Scan are 

commonly used. 

3, Scan Design 

In a scqucnt.al circuit it is difficult to fonn 

test vectors fur stuck-at-faults because the 

sequential depth of the design easily makes the 

test vectors to large. The main idea with sean 

design is to obtain control and observability for 

flip-flops and' thus making it easier to form test 

vectors. Adding a test mode to the circuits such 

that when the circuit is in test mode, all flip-flops 

functionality forms one or more shift registers 

does this. Controllability is achieved in test mode 

by setting the flip-flops to any desired state by 

shifting in the required state into the shift register 

(also known as scan register). The states of the 

flip-flops are observed by shifting the contents of 

the scan register out. The states of all flip-flops 

in a design can be set or observed in a number of 

clock cycles that equals the number of flip-flops 

in the longest scan register J2 J. 

3.1. Scan Cells 

The theory of SC

I 

l 


500 port may be connected to the Q or Qnegative 

ports. 

Agure 1. Mux-O Flip-Flop 

It is important to ensure that external control 

signals do not interfere with the flip-flop (Figure 

2) when it is in scan mode (I]. 

Figure 2. Set-Scan Flip-Flop 

251 

icon AOELCO 2007 

• Operate: Normal transparent operation of 

the element, 0 to Q and QN. 

..Scan Sample: Observability of1he logic that 

fans into the scan element, 0 to 500. 

•. Scan LoadIShift Serially IoadIshift data into 

the scan chain while unloading the last 

sample. SOl to SOO . 

• .Scan Data Apply: Control the output of the 

scar. element and thereby controlling the 

logic attached to Q. 

.H'l...·t 

..•...: .._-_ .. 1.- i-·. : 

"'~: 

'.cbr••••.••~ 

••••••• ~f •••. 

" 

'.' i F+- 

~ 

i:'--; 

--' 

1 

I 

!:. 

• ~ .0(,'\." 

..,...~.. \ •..•... 

------- ••.••.. (W-. 

Figure 3, Full-Scan chain (1) 

The signal path of the flip-flop can be 

controlled and observed by four transfer 

. functions. 

3.2. Partial Scan 

When all flip-flops in a design can be 

controlled and observed with scan cells is called


full-scan (Figure 3). In a circuit with a lot of 

sequential feedback and thereby the: length of the 

sequences cannot be bounded it is not advisable 

to use scan flip-flops. In particular parts of the 

design where timing is critical it can also be 

advisable to not using scan flip-flops. In these 

cases the design is called partial scan. When this 

type of design is run through an ATI'G-tool it 

may cause loss of fault coverage. increased 

runtime and an increase in the number of tc"S( 

vector generated. 

3-3. Multiple Scan Chains 

If many flip-flops are used in a design a 

single scan chain can become too large. It call 

take very long time to load each state with a very 

long scan chain. Splitting the chain in more scan 

chains can solve this. The trade-offs of this 

solution is that multiple scan chain." requires 

more dedicated (cest pins. If multiple scan chains 

are used the scan chains should have the same 

number of scan bits as far as possible this IS 

called balanced scan chains. 

This is the rncst cost efficient method and it 

uses the memory more efficient 

3.4. Scan Design Rules 

The 'e are many rules of for designing a 

scan-based design among allthcsc four is useful: 

• Use only one kind of flip.flop in the design. 

E.g. D-type:master-slave. 

• At least one primary input pin must be 

available for test. 

• .Every flip-flop clock must be controllable 

from primary inputs. 

• Avoid synchronous latches, transparent 

latches. 

• Do not feed clock to data inputs of f1ip- flops 

4. Built in Self Test 

252 


Since circuits become more dense and faster 

with smaller size and that the logic-to-pin ratio 

on chips is increasing makes the testing of logic 

morc and more difficult. It takes longer time to 

generate test patterns and the patterns consume 

lot of memory. Often are the designers not aware 

of the gate-level structure of their designs 

because it is synthesized in VHDL hardware 

description languages. Therefore it has becoming 

interesting to implement different kind of logic 

in the design so it can test itself so called BIST. 

Figure 4. Built in self test (3] 

The idea of BIST is to implement test 

pattern generation and response analyzing and 

even fault analyzing together with the chip. BIST 

(Figure 4) can be categorized in different ways: 

Online IlIST: Testing is done during normal 

operation 

• Concurrent testing - detects faults while 

system is doing normal functions.. 

e Nun-Concurrent testing - detects faults 

while system is in idle mode. 

Offline BIST: System is brought 10 a test 

mode 

e. functional testing - tests the system at a 

high level of function. 

e Structural testing - detects structural faults 

of the system. 

4.1. BIST Pattern Generation

/ 


The size of the BIST logic should not be too 

large compared to the rest of the logic otherwise 

the BIST logic can have more errors than the 

usable circuit. The design of the BIST should be 

in the order of 20"~ to be efficient. Because of 

this the test patterns cannot take up to much 

memory space so !hey must be compressed 

somehow. The design must have a simple 

hardware implementation and it should not slow 

down the nonnal operation. Different kinds of 

hardware for pattern generation can be used can 

be used, the most preferred is LFSR - linear 

feedback shift register (Figure S). 

.,., ." ..- 

Figure 5. LFSR 

" 

Different kinds of methods for pattern 

generation can be used. 

4.1.1. Exhaustive Testing. Every test pattern 

are applied to the circuit. which requires 2. test 

patterns. It can be implemented using a binary 

counter or a maximum length autonomous 

LFSR. This method is considered ouly when 

0


generator, a testing response compactor and a 

scan chain cell (2J. 

S. Boundary Scan 

Almost all printed circuit boards today is of 

the type multilayer SMT·boards with a lot of 

circuitry in between the layers and components 

soldered on both sides. Many components used 

today are not easily accessible because they have 

their connections under their package e.g. SP and 

BOA circuits. This makes it difficult to use in 

circuit test systems with nails. In circuit testers 

also has the disadvantage that the stress 

components during testing. All these problems 

has led to a standard for testing components on 

PCBs, this standard is called ITAG 1149.1 

Boundary-scan Design Standard. Boundaryscan 

operates under two major modes: 

• Non-invasive mode: In this mode the circuit 

is guaranteed to work independent from the 

rest of the logic in the IC. This makes it 

pos- ible for the circuit to serially shifting in 

and out data from the circuit. These 

activities do not affect the normal behavior 

of the circuit. 

• Pin permission modes: This mode takes 

control of the input and output pins of the 

IC, thus making it possible to test the 

interconnections of the IC separately from 

the system logic. This mode disrupts the 

normal behavior of the circuit. For Ie's to 

work under the 1149.1 standard they must 

start-up in non-invasive mode so the Ie is 

not damaged. When running the Ie in the 

pin permission modes care must be taken 

when returning to non-invasive mode. 

Accidentally driving a bus simultaneously 

with 'I's and '0'5 can easily occur 

5.1. Configuration of Boundary Scan 

Components 

254 


On an integrated circuit compliant with the 

standard each pin has a boundary-scan cell, all 

these cells are connected in series to form a 

boundary register. The first cell in the chain is 

connected to the input pin TDI (fest Data In) 

and the last cell is connected to the output pin 

TOO (Test Data Out). DiffCRtlt kinds of 

registers can be connected between the TOI and 

TOO pins. The device 10 register provides the 

identification of the circuit, the Bypass register 

makes it possible to reduce the length of the 

register when a specific IC is (lot used for a test, 

The Instruction register can' be loaded with 

instructions, which enables different modes of 

the hardware. The TAP-controller is a simple 

finite state machine that recognizes the 

boundary-scan protocol and controls the 

operation of the hardware through internal 

signals, The only signals that are allowed to 

influence the TAP controller is the test clock 

(TCK)-, test mode select (TMS)- and the Test 

reset (TRST)- pins. (Figure 6) When connecting 

many circuits a boundary-scan chain is created, 

this chain can be configured in many different 

ways. 

Figure 6. Boundary Scan 

S.2. Test Instructions


To control the system various rest 

instructions are used among these some can be 

used for other purposes than testing. 

SAMPLEIPRELOAO - (required) with this 

instruction it is possible to take a sample of the 

components input and output signals and it is 

also possible to load the boundary scan register 

with this value. 

EXTEST - (required) this instruction makes it 

possible to test circuits independently off the 

chip since it captures the signals coming into the 

chip and driving the circuits with signals from 

the boundary-scan register. 

BYPASS - (required) With the BYPASS 

instruction it is possible to use shorter boundaryscan 

vectors if the particular '\OlTlp')nentis not 

used by certain tests. . 

lNTEST - (optional) with this instruction It IS 

possible to shifting in and out tests vectors and 

test data from the on chip logic. 

RUNBIST - (optional) The purpose of 

RUNBIST is to control on-chip logic BIST via 

the boundary-scan chain. 

CLAMP - (optional) This instruction is used 

when forcing the output pins to be driven by the 

boundary-scan register. 

IDCOOE - The component has a code, which 

contains the identification of the component; this 

is called a JEOEC code. The instruction puts this 

data between TOI and TOO so that it can be 

shifted out. This instruction is required when 

components have JEDEC codes. 

255 

icon ADELCO 2007 

USERCODE - When using user programmable 

components such as FrGAs this instruction is 

used to load the device identification register 

with the code that the user has prograrmned into 

the component. This instruction is required when 

user programmable component has a device 10 

register. 

HIGHZ - This instruction puts all output pins 

into high impedance state that prevents damage 

to the on-system logic and protects other 

components as well. 

5.3. Boundary Scan Cells 

The boundary scan cells could look different 

depending on the function of the component. 

Control and observe cell - The normal type of 

boundary scan cell (Figure 7). 

Figure 7. Control-and-Observe Scan Cell 

Observe only cell - If the cell should only 

sample the signal it is only necessary to use an 

Observe only cell. Bi-directional pins (Figure 8). 

If the component has bidirectional pins the cell 

must have three cells to take care of these 

signals. Since a component with a lot of 

bidirectional pins requires many cells it is 

possible to control these tri-state cells with one 

enable signal. But special care must be taken so 

that one does not use a scan register both to 

control an output pin and as an input to the 

system logic.

- 

I I 

, 5,5, 

r . 

i: ,1 

f I 

'- 


l EN ' 

~-T-~.!:'· 

-- •.... _-_.j 

Figure 8. Bi-directional pin 

5.4. Boundary 

Language 

Scan Description 

To communicate the infonnation about the 

boundary scan hardware to users of a particular 

chip and to CAD-tools through the VHOL 

hardware description language a Boundary Scan 

Description Language (UDSL) was added to the 

1149.1 standard. BOSL can be used by ATPGtools 

to generate test patterns and by synthesis 

tools to synthesize test logic but are not usable as 

a simulation model, since it can not describe 

voltages, currents and so forth. 

Pros and Cons 

+ Less overhead than Scan design 

+ Less expensive test equipment 

+ IC's tested at their complete, interconnected 

environment 

- Circuits with boundary scan are expensive 

and they can be hard to find 

Requires quite expensive software 

and equipment 

6. Benefits and 1 rade-offs of OFT 

The major benefits of using Design for 

testability are: 

256 


• Shorter time to market 

• Reduced test time 

• Inexpensive test equipment 

• Yield learning, which is often overlooked 

The implementation of OFT involves some 

sacrifices. 

• Increased area of components 

• More pins on the I'eu 

• Increased PCB area 

• Degraded performance of the circuit. 

It is up 10 each cOlllpany to decide if the 

product they producing can benefit on applying 

OFT or not. 

7. Conclusion 

This paper has tried to give an insight in 

design for testability. The main ideas used today 

arc Scan design. built in self-test and Boundary 

scan. The difficulties in choosing methods are 

dependent of a lot of factors to get the most 

benefit-to-cost ratio. There are cost models used 

that try to help in this decision. To apply OFT or 

not apply OFf is dependent on factors like 

quality and volume. 

References 

[I) Alfred L. Crouch, "Design-for-test", Prentice 

Hall PTR 1999. 

(2) RooD. (Shawn) Blanton and Wojciech Maly. 

"Design for testability model", www.ece 

Cost.cmu.edulcssi/resbooklpdf/wei2.pdf. 

(3) Michael L Bushnell and Vishwani D. Agrawal, 

"Essentials of Electronic Testing ", Kluwer 

Academic Publishers 200 I

T - BVU College of Engineering, Pune, India

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