Communicating via HDLC over a TDM Interface with a QUICC ...

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QUICC Engine Baud Rate Generates and Clock Routing “bank of clocks” logic block provides the multiplexing options between the various clock sources and clock users, as shown in Figure 4. Rx UCC1 Tx Rx UCC2 Tx Rx UCC3 Tx Rx UCC4 Tx Rx UCC5 Tx Rx UCC6 Tx Rx UCC7 Tx Rx UCC8 Tx UPC1 UPC2 IR Rx Tx IR Rx Rx USB Tx Tx Time stamps 1,2 ce_timer and RTC clocks BRG1 BRG2 BRG16 Rx Tx TDMA1 Bank of Clock Selection Logic (Partially filled cross-switch logic programmed in the CMX registers.) Figure 4. Bank of Clocks Rx Tx TDMH1 CLK1 CLK2 CLK3 CLK4 CLK23 CLK24 BRGO1 BRGO2 BRGO16 UCC1 GRX CLK UCC2 GRX CLK UCC1 TBI RX CLK1 UCC2 TBI RX CLK1 RTC CLK In a typical TDM application, an external source would provide both the data clock and the frame sync. The bank-of-clocks logic is used to connect the appropriate clock pins to the TDM logic. For this example, Communicating via HDLC over a TDM Interface with a QUICC Engine UCC, Rev. 0 8 Freescale Semiconductor
QUICC Engine Baud Rate Generates and Clock Routing two baud rate generators are used to produce a data clock and a frame sync in order to avoid requiring an external clock source. The bank-of-clocks logic makes this easy by routing the two baud rate generators used to the TDM interface. The baud rate generators work by dividing a source clock to a user programmable frequency. The source clock can be one of the external clock pins or the internal QUICC Engine clock. This choice of clock sources for the 16 BRGs provides significant flexibility in clock generation. In this example, the QUICC Engine clock is used as the input for the two of the BRGs. This clock is referred to as the CE_CLK in MPC8360 Reference manual and the BRGCLK in the QEIWRM. CE_CLK/BRGCLK is generated by the QUICC Engine PLL, which is clocked by the PCI bus clock or CLKIN depending on system configuration. On the MPC8360-RDK, CE_CLK/BRGCLK is 250 MHz. Figure 5 shows a baud-rate generator block diagram. CLK Pin x CLK Pin y BRGCLK RXDn EXTC Clock Source MUX ATB Autobaud Control DIV 16 CD[0–11] Divide by 1 or 16 Prescaler 12-Bit Counter 1–4,096 BRGOn Clock Figure 5. Baud-Rate Generator (BRG) Block Diagram The baud rate generators consist of a pre-divider followed by a 12 bit divider. The predivider can divide the clock by one (i.e. no change) or 16. The divider’s range is from one to 4,096. (Note that programming the divider register to zero results in divide by one in the hardware.) Using both gives a division range of one to 65,536 (16 × 4,096). In this example, the two BRGs are setup as follows: BRG3 — Divide by 16 turned off ( BRGC3[DIV6] bit = 0) — Counter = 161 (BRGC[CD] = 0xA0). — BRG3 output = 250 MHz ÷ (1 × 161) = 1.552 MHz. BRG11 — Divide by 16 turned on ( BRGC3[DIV6] bit = 1) Communicating via HDLC over a TDM Interface with a QUICC Engine UCC, Rev. 0 To Pin and/or Bank of Clocks Freescale Semiconductor 9 BRGn
Page 1 and 2: Freescale Semiconductor Application
Page 3 and 4: Communicating via HDLC over a TDM I
Page 5 and 6: QUICC Engine Sub-blocks Needed for
Page 7: Communicating via HDLC over a TDM I
Page 11 and 12: Timeslot Assigner Description/Confi
Page 13 and 14: 5.2 TSA Mode Register Settings Time
Page 19 and 20: #include // The following defines
Page 21 and 22: BRG11 enabled to produce a 8.0005 k
Page 23 and 24: Set the last bit on timeslot 24 ptr
Page 25 and 26: assumptions: // The IMMR define mat
Page 27 and 28: } // Set RFTHR & RFCNT *(UWORD *)(U
Page 29 and 30: MFF = 1, multiple frames allowed in
Page 31 and 32: void enable_ucc8 (); void enable_uc
Page 33 and 34: Set the RX BD pointer to the area o
Page 35 and 36: THIS PAGE INTENTIONALLY LEFT BLANK

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