Annual report 2005 - Europractice-IC

EUROPRACTICE IC service 

The right cocktail of ASIC Services 

EUROPRACTICE IC Service offers you a proven route to ASICs that features: 

• Low-cost ASIC prototyping 

• Flexible access to silicon capacity for small and medium volume production quantities 

• Partnerships with leading world-class foundries, assembly and testhouses 

• Wide choice of IC technologies 

• Distribution and full support of high-quality cell libraries and design kits for the most popular 

CAD tools 

• RTL-to-Layout service for deep-submicron technologies 

• Front-end ASIC design through Alliance Partners 

Industry is rapidly discovering the benefits of using the EUROPRACTICE IC service to help bring new 

product designs to market quickly and cost-effectively. The EUROPRACTICE ASIC route supports especially 

those companies who don’t need always the full range of services or high production volumes. 

Those companies will gain from the flexible access to silicon prototype and production capacity at 

leading foundries, design services, high quality support and manufacturing expertise that includes IC 

manufacturing, packaging and test. This you can get all from EUROPRACTICE IC service, a service that 

is already established for more than 10 years in the market. 

The EUROPRACTICE IC Services are offered by the following centers : 

• IMEC, Leuven (Belgium) 

• Fraunhofer-Institut fuer Integrierte Schaltungen (Fraunhofer IIS), Erlangen (Germany) 

By courtesy of IMEC 

The European Commission 

is funding the Europractice 

IC Service under the IST 

programme in the 6 th 

framework. This funding is 

exclusively used to support 

European universities and 

research laboratories.

Dear EUROPRACTICE customers, 

Table of contents 

Foreword 

It was with great pleasure that we recently announced the offering of UMC’s 90nm technology as part of our EUROPRACTICE 

IC Service. By offering 90nm technology we are following very closely the ITRS roadmap and as such smaller companies as 

well as universities and research institutes can benefit from the high density and high speed advantages of 90nm. 

From your Foreword reactions we believe that our technology portfolio is now pretty diverse and attractive. Our 0.35µ offering 1 

from AMIS and austriamicrosystems is very suited for medium complexity designs with analog, high voltage and high 

speed (SiGe) options. With the various IHP 0.25µ SiGe:C technologies, you have access to very high speed (up to 

Your Total and Turn-Key ASIC Solution 3 

200GHz) devices. Finally UMC’s 0.25µ, 0.18µ, 0.13µ and 90nm CMOS technologies including the various analog and RF 

options offer you Easy access access to the most advanced technologies. 

3 

Phase I: ASIC Design 4 

We also noticed an increase interest in OPTO technologies for CMOS Imagers. Let me inform you that we have with 

Phase II: Prototyping and test development 5 

AMIS the possibility to do stitching on their CMOS processes allowing to get very large imagers. From austriamicrosys- 

tems we have the Phase OPTO III: option First on test their & Characterization 0.35µ CMOS. From of UMC prototype we are offering now MPW runs in their advanced 5 0.18µ 

CIS (CMOS Image Sensor) technology. So a whole portfolio of CMOS Image Sensor technologies is at your disposal. 

Phase IV: Qualification of the ASIC 6 

We see an increased Phase V: interest Volume in our production easyCOT & prototype test activities and small/medium volume service. Through our easyCOT 6 

service we offer 

EUROPRACTICE 

easy access and 

offers 

technical 

deep 

assistance 

submicron 

in 

design 

various 

support 

aspects 

service 

such as access to standard cell libraries, 

7 

foundry design rules and technology parameters, RTL-to-layout service, prototyping, advanced packaging such BGA, 

test software and Low hardware cost IC-prototyping development, debugging, characterization, qualification, product ramp-up and small 8 to 

medium volume Technologies production. Many / Supply of our partners start-up / mini@sic customers do not have the technical expertise and rely 9on 

our 

easyCOT service to bring their idea to the market. Why shouldn’t you try it ? 

EUROPRACTICE offers full test solutions for production 10 

Last year, 2005, Web was site a good / EUROPRACTICE-online year! We saw again an increased number of designs on our prototype runs : 11 450 de- 

signs (414 in 2004 and 363 in 2003). A large part of this increase came through our concept of mini@sic whereby 

universities Results and research institutes world-wide have the opportunity to prototype smaller designs at lower 12cost 

on 

selected MPW runs. Last year 139 designs have been prototyped under the mini@sic concept. For your reference, the 

MPW prototyping service 12 

cost for prototyping a design of 1525 x 1525 microns in UMC 0.18µ only costs 2600 euro. So what are you waiting 

for ? It is the ideal Small solution volume to projects have students involved in advanced IC design. 

15 

Finally, it Examples is also my of great ASIC pleasure projects to announce to our European universities and research institutes that we 16signed 

a new 3-year contract with the European Commission under the 6th Framework in order to provide them with CAD 

tools, discounted List of customers prototyping and technical support. 

29 

I thank you for your continuous support and look forward to future cooperation, 

Sincerely yours, 

Dr. C. Das 

Chairman EUROPRACTICE IC Service 

IMEC (Belgium) 

europractice | foreword 

1

Table of contents 

Foreword 1 

Your Total and Turn-Key ASIC Solution 3 

Easy access 3 

Phase I: ASIC Design 4 

Phase II: Prototyping and test development 5 

Phase III: First test & Characterization of prototype 5 

Phase IV: Qualification of the ASIC 6 

Phase V: Volume production & test activities 6 

EUROPRACTICE offers deep submicron design support service 7 

Low cost IC-prototyping 8 

Technologies / Supply partners / mini@sic 9 

EUROPRACTICE offers full test solutions for production 10 

Web site / EUROPRACTICE-online 11 

Results 12 

MPW prototyping service 12 

Small volume projects 15 

Examples of ASIC projects 16 

List of customers 29 

2 europractice | table of contents

EUROPRACTICE: 

Your Total and Turn-Key ASIC Solution 

EUROPRACTICE provides semiconductor 

and system companies with a total 

and turn-key ASIC solution including : 

• easy access to foundry design rules, 

cell libraries and design kits 

• deep submicron RTL-to-layout service 

• low cost prototype fabrication service 

• volume fabrication service including 

wafer fabrication, packaging and 

test 

• ASIC qualification 

• logistics 

• technical customer support 

Easy access 

Through its agreement with foundries 

and library partners, EUROPRACTICE is 

allowed to distribute foundry technology 

information and cell libraries upon 

simple signature of a standard Non- 

Disclosure Agreements or a Design Kit 

License Agreement. Those agreements 

can be downloaded from the EURO- 

PRACTICE website. In this way you 

have access in a few days without 

having to go through a painful customer 

qualification procedure at the 

foundry. Foundry information includes 

design rules, spice parameters, design 

& layout manuals and DRC/ERC/LVS 

decks. Cell library information includes 

library manuals and design kits for 

New fables startup companies as well as small companies or companies 

having small ASIC volume products in niche markets experience 

huge problems to get access to foundries since their volume is too 

small. 

EUROPRACTICE has wafer foundry agreements with different leading 

suppliers, allowing to offer the most advanced as well as specific technologies 

to those customers. Our foundry partners acknowledge the 

EUROPRACTICE Service as the optimal solution to provide wafer capacity 

to smaller customers. Suppliers see EUROPRACTICE as one big customer 

representing about 600 universities and 300 companies worldwide. 

Through agreements with foundry partners, EUROPRACTICE is 

able to offer ASIC solutions ranging from a few wafers to thousands of 

wafers per year. 

most of the popular CAD tools (Cadence, 

Synopsys, Mentor Graphics, 

Tanner, etc.). This foundry and library 

information is distributed on the EU- 

ROPRACTICE CD-ROM or via FTP. 

europractice | a total solution 

3

Phase I: ASIC Design 

When customers have received design 

rules, cell libraries, etc., they 

can start the ASIC design. ASIC design 

can be split up into front-end 

design and back-end design. Frontend 

design covers ASIC specification 

feasibility study and design including 

tasks such as schematic 

entry, VHDL description, scan insertion, 

simulation and synthesis. The 

front-end design can be carried out 

by the customer himself or can be 

subcontracted to a design house. 

During this design phase, Europractice 

offers technical support on 

technology, test, type of package, 

etc. Important know-how and feedback 

from the test house will be 

used to improve the DFT (Design 

For Testability). ”State-of-the-art” 

CAD tools are used during the ASIC 

design phase. 

Design House know-how 

Design for testability (DFT) 

Foundry, IP provider 

Design rules, IP & cell libraries 

models 

Foundry, IP provider 

IP cell libraries layout 

Foundry 

Golden rules file 

for DRC, LPE, LVS 

Critical design review 

Tape out 

Correct GDS-II database for manufacturing 

4 europractice | a total solution 

> 

> 

> 

> 

> 

When the netlist is ready the backend 

design activity starts including 

layout generation using state-ofthe 

art layout tools. Deep submicron 

digital place & route tasks 

are in most cases not performed 

by the customers. For those customers 

that have not their own 

layout tools, EUROPRACTICE is offering 

such deep submicron layout 

service (see deep submicron layout 

service on page 7). After initial 

layout, timing verification is carried 

out by the customer using 

parasitic layout information and 

layout is iterated until timing is 

met. Verification of the design 

needs to be done in all technology 

corners. 

When layout is finished, a final 

DRC (Design Rule Check) and LVS 

ASIC specifications 

Initial design review 

Preliminary design review 

Digital, analog 

front-end design 

Physical layout 

generation 

Design verification 


(Layout versus Schematic) is performed 

on the GDS-II database in 

order to deliver a correct GDS-II to 

the foundry for manufacturing. 

customer 

design 

foundry, IP provider 

assembly 

test 

By courtesy of IMEC

Phase II: Prototyping and test development 

After all the checks have been performed 

and the GDS-II database is 

correct for manufacturing, Europractice 

sends the database to the 

foundry for prototyping. Masks will 

be generated by the foundry and 

first silicon will be produced. Prototyping 

can be done on MPW 

(Multi Project Wafer) runs or SPW 

(Single Project Wafer) pilot runs 

(see Low Cost IC prototyping on 

page 8). 

In parallel with prototype fabrication 

and prototype packaging the 

test solution including test hardware 

and software is developed. 

EUROPRACTICE will generate 

bonding diagram and assembly instructions. 

For prototyping ceramic 

packages as well as the produc- 

When packaged prototypes are 

available, they will be shipped to 

the test house for debugging. Debugging 

includes continuity and 

leakage tests, ATPG test and test 

of the different analog blocks 

(when available on the ASIC) at 

room (RT) temperature. When prototypes 

are working correctly according 

to the ASIC specification, 

low (LT) and high (HT) temperature 

are performed. The next stage 

is a full characterization of the 

ASIC at the corners of the voltage 

supply and frequency at LT, RT and 

HT. 

tion plastic packages can be 

used. Prototype packaging is 

done through one of the assembly 

partners in Europe or 

the Far-East. 

Mask generation 

Wafer fabrication 

(MPW or engineering lot) 

Packaging prototypes 

Correct GDS-II database for manufacturing 

Prototypes and test solution available 

Phase III: First test & Characterization of prototype 

During each test a datalog is generated 

of the measured values and 

histograms and cpk reports are 

sent to the customer. In case of 

specific problems, failure analysis 

can be done to determine the reason 

of the failing. 

By courtesy of Microtest 

Test hardware development 

Probe card / test board 

Test software 

development 

Debugging hardware 

Prototypes and test solution available 

Test and debug 

prototypes 

Test at 

RT, LT, HT 

Characterization 

prototypes 

Datalog, histograms, drift 

analysis, CPK, CP 


5

Phase IV: Qualification of the ASIC 

When customers only need prototypes 

of their ASIC, qualification is not needed. 

However when prototypes are working 

correctly and the customer would like to 

have volume production it is the right 

time to think about the “product qualification”. 

Qualification requirements: 

Medical 

Industrial 

Space 

Consumer 

Europractice offers within their test solution 

service a full qualification through 

one of the test house partners. The 

qualification procedure can range from 

Consumer, Industry and Medical till Space qualification according to the Military, 

JEDEC standards... 

The qualification procedure will be discussed 

between Europractice, customer 

and test house and a full qualification 

flow will be prepared. To speed 

up the procedure, most of the tests 

are running in parallel. Special burn-in 

boards will be developed for reliability 

tests. 

By courtesy of MASER Engineering 

Phase V: Volume production & test activities 

Once the ASIC has been qualified, the ASIC is ready for volume production. During 

the ramp-up phase, yield and process will be monitored. Once the ASIC runs into 

higher volume, the test solution can be transferred to test houses in the Far East. In 

that case the test boards are copied, the original test board will remain in our European 

test houses so that yield and process monitoring is still possible. 


By courtesy of Microtest 

> 

Start new batch of wafers 

Packaging 

Development of 

qualification procedure 

Qualification hardware 

development 

Qualification software 

development 

Datalog, histograms, 

CPK, CP 

Wafer production 

Probe test 

Packaging 

Final test 

Yield & process 

monitoring 

Delivery tested 

components


offers deep submicron design support service 

Synthesis and layout of deep submicron chips is not 

straightforward. You need a highly trained team of engineers 

equipped with expensive state-of-the art software 

tools. The chips are growing in size whereas the 

technology dimensions are getting smaller. Because of 

this, designers have to understand how to tackle issues 

like: clock-skew, latencies of interacting clock domains, 

IR-drop on the power distribution, electro-migration 

and signal integrity issues, handling up to 8 

layers of metal in the back-end, incorporating IP blocks 

in the design, on-chip variation, design for packaging, 

etc. 

Supporting high-level designers, EUROPRACTICE IC Service 

provides a design support service starting from 

RTL code or synthesized netlist. The service includes 

the whole back-end design flow: virtual prototyping, 

physical synthesis, deep-submicron layout, timing 

analysis, simulation, ATPG, tape-out preparation, etc. 

The service is equipped with state-of-the art tools from 

the major vendors: the Synopsys Galaxy and Cadence 

Encounter Platforms. 

In the past many circuits were taped out successfully 

both for in-house developed Systems-On-a-Chip as for 

ASICs developed by third party design houses, research 

institutes and universities. Many of these circuits 

included IP blocks like analog full custom blocks, 

memory macro’s (even from different vendors), special 

I/O and RTL level (soft or firm) IP. 

Procedures are in place to offer standard and staggered 

I/O configurations and configurations with bonding 

pads equally spread over the standard-cell core, for 

flip-chip application. 

Some circuit complexities handled are: up to 71 million 

transistors, several hundred interrelated gated clock 

domains and technologies from many different vendors 

down to 90nm. 

Layout of a 40 million transistor circuit featuring RAMS and other 

IP in Chartered Semiconductor 0.13µ CMOS – 46.5 mm 2 

(By courtesy of IMEC) 

Layout of a 3.7 million-transistor circuit featuring several memory 

blocks and PLL in UMC 0.18µ CMOS (6 metal layers) – 20 mm 2 

(By courtesy of IMEC) 


7

Low cost IC prototyping 

The cost of producing a new ASIC 

for a dedicated application within 

a small market can be high, if directly 

produced by a commercial 

foundry. This is largely due to the 

NRE (Non-Recurring Engineering) 

overheads associated with design, 

manufacturing and test. 

EUROPRACTICE has reduced the 

NRE, especially for ASIC prototyping, 

by two techniques: 

(i) Multi Project Wafer Runs or 

(ii) Multi Level Masks. 

Multi Project Wafer Runs 

By combining several designs from 

different customers onto one mask 

set and prototype run, known as 

Multi Project Wafer (MPW) runs, 

the high NRE costs of a mask set 

is shared among the participating 

customers. 


Fabrication of prototypes can thus 

be as low as 5% to 10% of the 

cost of a full prototyping wafer 

run. A limited number of tested or 

untested ASIC prototypes, typically 

20-50, are delivered to the customer 

for evaluation, either as 

naked dies or as encapsulated devices. 

Only prototypes from fully 

qualified wafers are taken to ensure 

that the chips delivered will 

function “right first time”. 

In order to achieve this, extensive 

Design Rule and Electrical Rule 

Checkings are performed on all 

designs submitted to the Service. 

EUROPRACTICE is organising about 

130 MPW runs per year in various 

technologies. 

Multi Level Mask 

Single User Runs 

Another technique to reduce the 

high mask costs is called Multi 

Level Mask (MLM). With 


this technique the available mask 

area (20 mm x 20 mm field) is typically 

divided in four quadrants 

(4L/R: four layer per reticle) whereby 

each quadrant is filled with one 

design layer. As an example : one 

mask can contain four layers such 

as nwell, poly, ndiff and active. 

The total number of masks is thus 

reduced by a factor of four. By 

adapting the lithographical procedure 

it is possible to use one 

mask four times for the different 

layers by using the appropriate 

quadrants. Using this technique 

the mask costs can be reduced by 

about 60%. 

The advantages of using MLM single 

user runs are : (i) lower mask 

costs, (ii) can be started any date 

and not restricted to scheduled 

MPW runs, (iii) single user and (iv) 

customer receives minimal a few 

wafers, so a few hundreds of prototypes. 

This technique is preferred over 

MPW runs when the chip area becomes 

large and when the customer 

wants to get a higher number 

of prototypes or preserie. 

When the prototypes are successful, 

this mask set can be used 

under certain conditions for low 

volume production. 

This technique is only 

available for technologies 

from AMI Semiconductor 

and IHP.

Technologies 

For 2006, EUROPRACTICE has extended its technology 

portfolio. Currently customers can have access to prototype 

and production fabrication in the following 

technologies : 

• AMIS 0.35µ C035M-A 5M/2P/HR 

• AMIS 0.35µ C035M-D 5M/1P 

• AMIS 0.35µ C035M-I3T80U 80 V - 3M & 4M 

• AMIS 0.5µ C05M-A 3M/2P/HR 

• AMIS 0.5µ C05M-D 3M/1P 

• AMIS 0.5µ CMOS EEPROM C5F & C5N 

• AMIS 0.7µ C07M-A 2M/1P/PdiffC/HR 

• AMIS 0.7µ C07M-D 2M/1P 

• AMIS 0.7µ C07M-I2T100 100V 2M & 3M option 

• AMIS 0.7µ C07M-I2T30 30 V - 2M 

• AMIS 0.7µ C07M-I2T30E 30 V - 2M 

• UMC L90N Logic/Mixed-Mode/RFCMOS 1P9M lowK 

• UMC L130E FSG 1P8M Cu Logic/Mixed-Mode (HS/SP/LL) 

• UMC L130E FSG 1P8M Cu Mixed-Mode/RFCMOS (HS/SP/LL) 

• UMC L180 CIS 2P5M + MMC (Color filter + µlens sup.) - 

OPTO process 

• UMC L180 Logic GII 1P6M 1.8V/3.3V + MMC 

• UMC L180 Mixed-Mode/RFCMOS 1.8V/3.3V 

• UMC L250 Mixed-Mode/RFCMOS 1P5M 2.5V/3.3V 

• austriamicrosystems 0.35µ SiGe-BiCMOS S35 4M/4P 

• austriamicrosystems 0.35µ CMOS C35B3C1 3M/2P/5V IO 

• austriamicrosystems 0.35µ CMOS C35B4C3 

4M/2P/HR/5V IO 

• austriamicrosystems 0.35µ CMOS CSI 3M/2P/5V IO 

• austriamicrosystems 0.35µ CMOS C35OPTO 4M/2P/5V IO 

• austriamicrosystems 0.35µ CMOS w/EEPROM C35 4M/2P 

• austriamicrosystems 0.35µ HV CMOS H35 50V 3M & 4M 

• austriamicrosystems 0.8µ CMOS CXQ 2M/2P/HR 

• austriamicrosystems 0.8µ CXZ 2M/2P/HR 50V 

• IHP SG25H1 0.25µ SiGe:C Ft/Fmax=180GHz/220GHz 

4M/MIM 

• IHP SG25H1/H2/H3/VD with 5th thick metal option 

• IHP SG25H2 0.25µ comp. SiGe:C 4M/MIM 

• IHP SG25H3 0.25µ SiGe:C Ft/Fmax= 120/140GHz 4M/MIM 

• IHP SGB25VD 0.25µ SiGe:C Ft=30GHz@BVCEO>7V+RF 

HV-LDMOS 

• IHP SGC25B 0.25µ SiGe:C Ft=120GHz/4M/MIM 

Supply Partners 

IMEC is working together with several partners to 

get access to wafer fabrication, assembly and test. 

Foundry partners 

AMI Semiconductor (AMIS) 

austriamicrosystems 

IHP 

UMC 

Assembly partners 

ASAT 

ASE 

Edgetek 

HCM 

Selmic 

Library partner 

Virtual Silicon 

Test partners 

ASE 

DELTA 

MASER Engineering 

Microtec 

Microtest 

Rood Technology 

mini@sic prototyping conditions 

for universities and research 

laboratories 

In order to stimulate universities and research laboratories 

to prototype their ASIC designs, Europractice 

has introduced in 2003 the concept of mini@sic. 

That means that Europractice has selected several 

MPW runs in different technologies on which universities 

and research labs can prototype very small ASIC 

designs with reduced minimum prototype fee as follows 

: 

• All MPW runs in AMIS technologies are open to the 

mini@sic conditions with minimum prototyping fee 

of equivalent of 1 mm2 • Selected MPW runs in selected austriamicrosystems 

technologies are open to the mini@sic conditions 

with minimum prototyping fee of equivalent of 4 or 

5 mm2 • All MPW runs in IHP technologies are open to the 

mini@sic conditions with zero minimum prototyping 

fee 

• Selected MPW runs in UMC 0.18µ and 0.13µ CMOS 

mixed/RF technology are open to the mini@sic conditions 

with minimum prototyping fee of equivalent 

of ~ 2.3 mm2 europractice | a total solution 

9

Europractice offers full test solution 

Electrical Test 

• Electrical test of Analog, Digital, Mixed ASIC’s 

• Single and Multi-site test 

• Wafer test under cleanroom class 1000 up to 8” wafers 

• Yield and process monitoring 

• Final test on each type of package 

Reliability and qualification test 

The product can be qualified according to the military standards for: 

• Space qualification 

• Medical qualification 

• Industrial qualification 

• Consumer qualification 

1. Qualification 

• Visual Inspection 

• High Temperature Operating Life test (HTOL) 

• Low Temperature Operating Life test (LTOL) 

• High Temperature Bias (HTB) 

• Latch-up test 

• ESD HBM, CDM 

Burn-in and life test 

• Static and dynamic burn-in 

• Max clockfreq up to 40 MHz 

• HTOL 

Additional services 

• Laser marking 

• Dry pack and Vacuum seal 

• Barcode labelling 

Failure analysis 

• Decapsulation of plastic packages 

• SEM, SAM, X-ray, EMI imaging 

• Optical Microscopy 

• Plasma Etching 

• Probe Bench & Curve Tracer 


• Multilayer boards (up to 12 layers) 

• Stud probing, V-probes 

• Characterisation: Cp and Cpk datalog 

2. Package Reliability 

• Temperature Cycle Test (TCT) 

• Temperature Humidity Bias (THB) 

• High Accelerated Stress Testing (HAST) 

• Pressure Cooker Test (PCT) 

• Gross/Fine Leakage Test 

• PIND 

• Vibration, centrifuge, solderability 

• Moisture level qualification 

• Bondpull and die shear 

Design kits 

Designers need the necessary information 

(design rules, electrical parameters, 

cell library, etc.) of the chosen technology 

before they can start the design phase. 

All this information is put together by the foundry in the 

so-called ‘design kit’. EUROPRACTICE distributes more 

than 55 different design kits and cell libraries of the supported 

technologies for most popular CAD tools (Cadence, 

Mentor Graphics, Synopsys, Tanner, etc.) on CD-ROM. 

Customers can have a copy of the CD-ROM with the cell libraries 

& design kits by signing a Non-Disclosure or Design 

Kit License Agreement with EUROPRACTICE.

WEB site 

http://www.europractice.imec.be 

The Europractice IC Service web site provides full information 

such as: 

• Technologies 

• Specification sheets 

• Available and supported cell libraries and design kits 

• MPW runs 

• MPW prices 

• Small volume possibilities 

• Deep submicron netlist-to-layout service 

• Procedures for registration of designs for prototyping 

• Etc. 

Europractice-online 

http://www.europractice-online.be 

In 2003 Europractice introduced “Europractice-online”, 

a platform for information exchange. This platform is 

hosted by IMEC’s Microelectronics Training Center. 

Users can register to access information available on 

Europractice-online. The information that is available is 

grouped per technology and contains: 

• Public information 

• Confidential information in ‘closed’ domains, accessible 

after signature of Non-Disclosure Agreement or 

Design Kit License Agreement 

• News flashes 

• Frequently Asked Questions 

• Mailing lists 

The user can personalize the mailing lists in such a way that he is automatically informed by e-mail whenever a 

new document is posted, news is posted, FAQ is posted, etc. The user can choose for which technologies he will 

be notified. As such managers can select to be informed on latest news, whereas designers can ask to be notified 

on all new items for a specific technology. 


11

Results 

MPW prototyping 

service 

ASICs prototyped on MPW runs 

In 2005, a total of 450 ASICs have 

been prototyped. Whereas the number 

of designs on MPW runs have 

been decreased over the last years, 

we are very much pleased to see an 

increase again in 2004 and 2005, 

as well as for designs from European 

universities, research institutes 

as from industry. 

69% of the designs are sent in by 

European universities and research 

laboratories while the remaining 

31% of the designs is being sent in 

by non-European universities and 

companies world-wide. 

Geometry mix 

Year over year we see a shift towards 

newest technologies. Also in 

600 

500 

400 

300 

200 

100 

0 

Europractice Research 

15% 

Industry + non- European univ/research 

2000 2001 2002 2003 2004 2005 

Industry + non-European univ/research 140 159 155 115 128 138 

Europractice Research 27 46 13 48 52 69 

Europractice Academic 313 281 237 200 234 243 

12 europractice | results 

31% 

2005 the same trend is shown. The 

majority of the designs is now 

being done in 0.35µ and below 

(77%) while a few years ago the 

majority of the designs was still 

done in 0.7/0.8µ. 

mini@sic 

Very encouraging is the fact that the 

mini@sic concept was accepted 

very well by universities in 2005 

with 139 designs prototyped (90 in 

MWP designs in 2005 

Europractice Academic 

54% 

2004, 54 in 2003). This is a big increase 

and confirms that reducing 

the prototyping cost for education 

helps to stimulate universities to be 

more active in ASIC design. 

Interesting to see is that under the 

mini@sic conditions, the more advanced 

technologies are even more 

used (due to the drastic price reduction).

160 

140 

120 

100 

80 

60 

40 

20 

0.25 6% 

0 

0.25 6% 

0.13 

0.18 

0.25 

0.35 

0.5 & 0.6 

0.7 & 0.8 

0.18 21% 

MWP designs: technology used: 2004 

0.18 20% 

MWP designs: technology used: 2005 

2004 2005 

0.13 2% 

0.13 3% 

0.35 45% 

0.35 48% 

0.18 33% 

0.25 3% 

0.7/0.8 21% 

0.7/0.8 20% 

0.13 7% 

mini@sic designs per gatelength 

0.5/0.6 5% 

0.5/0.6 3% 

0.7/0.8 9% 


0.5/0.6 2% 

0.35 46% 

europractice | results 

13

14 europractice | results 

0 

EUROPRACTICE is offering its services world-wide 

EUROPRACTICE has offered since 1996 its low cost ASIC MPW 

prototyping services to customers from 48 countries worldwide. 

As the service is based in Europe, the majority of the 

designs come from European customers. But the interest 

from non-European countries is growing fast. 

100 200 300 400 500 600 700

Small volume projects 

More and more customers are using 

the COT (Customer Own Tooling) 

model when they need volume production. 

Through this COT model 

they have full control about every 

aspect of the total design and production 

flow. Large customers with 

sufficient ASIC starts and volume 

production can invest in the COT 

model as it requires a considerable 

knowledge and experience about all 

aspects such as libraries, design 

kits, transistor models, testing, 

packaging, yield, etc. For smaller 

customers the COT model is very attractive 

but very difficult due to the 

lack of experience. For those customers 

EUROPRACTICE offers the solution 

by guiding the customers 

through the full production flow applying 

the COT model. EUROPRAC- 

TICE helps you with technical assistance 

in the selection of the right 

package, setting up the test solution, 

yield analysis, qualification, etc. 

Netherlands 

16 

United Kingdom 3 

Spain 1 

Norway 1 

Korea 

2 

Number of small volume projects per country 

Through EUROPRACTICE you can 

also experience the benefits of the 

COT model. 

68 small volume projects in 2005 

EUROPRACTICE offers a great benefit 

to the foundries by taking care 

about the smaller customers, not 

being able to commit high volumes. 

Although the number of small volume 

projects has decreased, the 

total wafer volume sold has increased. 

This mainly due to the 

fact that die size of ASICS is larger 

than in previous years. 

EUROPRACTICE takes care about 

the volume projects requiring annual 

volumes up to 1000 wafers and 

more. For foundries this is small 

business but for many customers 

this can be millions of pieces. 

In 2005 EUROPRACTICE sold 68 

small volume projects in 13 countries 

and delivered about 7.5 mil- 

USA 1 

Australia 3 

Germany 21 

lion components. The average projects 

represents about 35,000 

pieces, but we deliver projects with 

less than 500 pieces and other projects 

with up to millions of pieces. 

These projects range from pure 

wafer delivery up to fully tested 

and qualified components. 

Request for quotation 

Customers can fill in a simple 2-page 

form with the main specifications. 

With this information EUROPRAC- 

TICE can answer in a few days and 

give a first rough price estimation 

so that customers can make a first 

evaluation. When the full details of 

the ASIC are known (area, testing, 

etc.) a final more accurate price 

quotation can be given. 

The request form can be accessed 

through our WEB site 

(www.europractice.imec.be). 

Austria 2 Belgium 9 

Denmark 4 

France 5 

europractice | results 

15

Examples of ASIC projects 

AMCHIP3 processor 

INFN Ferrara & INFN Pisa, Italy 

Contacts: 

R. Tripiccione, INFN, Ferrara 

(tripiccione@fe.infn.it) 

P. Giannetti, INFN Pisa 

(paola.giannetti@pi.infn.it) 

Technology : 

UMC 0.18µ CMOS 1P6M logic 

Die size : 99 mm 2 

Description 

Particle physics experiment are usu- 

ally built around high-energy parti- 

cle accelerators where primary par- 

ticles (such as protons) are made to 

collide heads-on, producing large 

numbers (hundreds) of secondary 

particles. Physicists study the be- 

haviour and eventual decay of these 

particles, in order to understand in 

details their behaviour and confirm 

or disprove theoretical models. 

In a typical large experiment, such 

as the CDF experiment at Fermilab, 

near Chicago in the US, shown in 

Figure 1, several layers of detectors 

produce signals associated to the 

passage of each particle, for each 

16 europractice | examples 

primary interaction. One of the first 

task to perform is to associate inde- 

pendent signals to tracks, that is to 

the paths followed by each particle 

within the detector, and then to se- 

lect only those events or particles 

that the physicists want to study. 

Figure 2 shows an event as seen af- 

ter the detectors response has been 

digitized and plotted. The task is 

to identify all the tracks that follow 

some specified criteria. This has to 

be down for all events, each arriv- 

ing at a rate of the order of the mi- 

crosecond. There is an obvious way 

to perform the job, suggested by the 

artist impression of Figure 3. All po- 

tentially interesting tracks are enumer- 

ated and then compared with the data 

arriving from the detector: every time 

a match is found, the track is detected, 

and recorded for further analysis. 

Figure 1. Figure 2. 

After digitization, data coming from 

the detector is associated to appro- 

priately formatted strings of bits, 

so, in the micro-electronics world, 

we need to match a given bit se- 

quence to a string contained in a 

large data-base of “legal” strings. 

The data-base contains of the order 

of one million strings. 

This formidable task is performed 

by a collection of AMCHIP3 proc- 

essor chips, whose basic structure 

is that of a content addressable 

memory. Memory locations are ini- 

tially loaded with a set of “legal” 

strings. As the experiment starts 

acquiring data, each event is fed 

to the AMCHIP. The processor com- 

pares in parallel incoming data with 

all its stored patterns and - in just 

one clock cycle - outputs pointers 

to all matching strings contained in 

its bank. Many AMCHIP3 processors 

are used in parallel: each of them 

receives the same input data and 

performs its comparison with a par- 

tial set of the complete data-base. 

A further important function of the 

processor is to sort out and format 

the output and to provide all func- 

tionalities needed to allow a parallel 

effort of hundreds of such proces- 

sors. Each AMCHIP3 processor han-

dles approximately 5000 database 

elements (each of about 100 bits). 

The SVT processing system of the 

CDF experiment uses about 2000 

AMCHIP3 processors. 

The processor has been designed 

at Instituto Nazionale di Fisica Nu- 

cleare, Ferrara using the UMC 0.18 

micron technology available through 

Europractice. The design uses a de- 

sign style based on standard cells. 

This approach has been shown as 

the best compromise between an 

FPGA based approach, much faster 

in design but poor in performance, 

and a full custom design that would 

allow packing many more elements 

in the content-addressable memory 

but would make it hard to migrate 

to more advanced technologies, as 

they become eventually available 

Figure 3. 

and economically viable. The design 

is very regular in structure: a regular 

placement of the standard cells has 

been performed and a very highly 

packed structure has been realized. 

Figure 5. 

The AMCHIP3 has been prototyped as 

a multi-chip project and, after succes- 

ful tests, a dedicated mask set has 

been prepared and production has 

been started. A photograph of the 

AMCHIP3 die is shown in figure 4, 

while a processing board containing 

several AMCHIP3 processors is shown 

in Figure 5. 

Why EUROPRACTICE ? 

The development and production of the AMCHIP has been performed in 

close collaboration with IMEC, that provided several Europractice related 

services. Very important to us are the possibility to develop a complex proc- 

essor at reasonable costs with a multi-project approach, complemented by 

the availability to perform small dedicated production runs with the same 

technology. 

Extremely helpful has also been the support given by IMEC during some 

critical phases of the design and the access to a test facility, where proto- 

types and production parts have been screened. 

europractice | examples 

17 

Figure 4.

18 

ASIC of charge sensitive amplifier (CSA) for micro-strip detectors 

Moscow Engineering Physics Institute, Moscow, Russia 

Contact : 

MEPhI, Electronics Department 

Kashirskoe shosse 31 

Moscow 115409, Russia 

Telephone: +7 495 323 9235 

Fax: +7 495 324 2111 

Eduard Atkin atkin@eldep.mephi.ru 

Technology : 

AMIS 0.35µ CMOS 2P5M analog 

The chip consists of 16 CSAs plus 

2 additional rail-to-rail op-amps. Its 

design area is 4 x 2 mm 2 . 

The basic unit of the chip is being a 

folded cascode CSA, optimized for 

80Gb/s CML-topology 2:1 multiplexer 

Fraunhofer IIS, Erlangen, Germany 

Contact : 

Jan Sundermeyer 

E-mail : 

jan.sundermeyer@iis.fraunhofer.de 

Technology : 

IHP 0.25µ SGC25C 

Die size : 0.74 mm 2 

A standard 2:1 multiplexer chip in 

CML-topology was developed in 

the commercially available 200 GHz 

SiGe HBT technology by IHP for data 

rates of over 80 Gb/s. The data in- 

puts are retimed on chip by two flip- 

flops. The supply voltage was set to 

4~V to give the transistors enough 

head room for proper functionality. 

For this reason measures to avoid 

voltage breakdown on transistors 

had to be taken. The multiplexer 

was provided with a cascode output 

stage to reduce the voltage stress 

on the transistors. The architecture 


detector capacitances up to 100 pF. Its input PMOS 

transistor has a high equivalent channel width (50 

mm !) to fit tight specification demands on noise 

(2000e ENC), dynamic range (1V), power consump- 

tion (1 mW), etc. Two additional op amps can be 

used for signal shaping and fast buffering. 

Main research goals for CSA chip design were: 

• Design and manufacture (via MPW) of a test pur- 

pose chip for micro-strip detectors prototyping; 

• The study of possibilities and merits of AMIS 0.35 

µm C035M-A process; 

• Optimization of the structure and biasing of CSA. 

For that purpose some CSAs are made different 

from each other in the grounding and supply- 

ing circuits. 

delivers wide bandwidth and gener- 

ates little jitter. 

A 40~Gb/s sequence is generated 

by multiplexing four 10~Gb/s-se- 

quences. The positive and negative 

output of the 4:1-multiplexer are 

delayed with different delay con- 

stants to generate two sequences 

with little correlation to each other. 

The delays are adjusted by phase 

adjusters to have synchronous data 

at the mux which is tested. 

supply voltage: -4.3 V 

current consumption: 237 mA 

clock power (single ended, begin of 

cable): 2 dBm 

data level: approx 200 mV 

eye opening (vertical): 70 mV 

eye amplitude: 231 mV 

eye opening (horizontal): 8.97 ps 

jitter RMS : 688 fs 

jitter p-p : 3.78 ps 

Measurements confirmed the chip’s 

functionality at 80~Gb/s though the 

stimuli signals were not optimal.

HACDAC : very high-resolution (>20 bits) data converter 

for space application 

SRON, Netherlands Institute for Space Research, Utrecht, The Netherlands 

Contact : 

Johan Haanstra 

E-mail: j.h.haanstra@sron.nl 

Technology : AMIS 0.35µ CMOS 2P3M analog 


Description 

SRON Netherlands Institute for Space Research is the center of expertise for 

the development and exploitation of satellite instruments for astrophysical 

and earth-oriented sciences. The sensitivity of scientific space instruments 

made by SRON is continuously increasing and is on the way to reach fun- 

damental physical limits. To retrieve the data from the sensors in these 

instruments, very sophisticated front-end electronics (FEE) is needed. The 

technical requirements of the FEE and the demand for low-power and low- 

mass electronics asks the use of full custom radiation hardened ASICs. For 

several future space missions, very high resolution (>20 bits), low frequency 

analog to digital and digital to analog conversion is needed and the qual- 

ity of this conversion is critical to the total instrument system. These data 

converters are needed in missions like LISA, which will use a laser inter- 

ferometric measurement between three formation-flying satellites to detect 

gravitational waves. The satellites are at 5 million km distance from each 

other and distance variations as small as 3nm need to be detected. 

The ExoMars mission, of which the rover with a seismometer will land on the 

planet Mars, is another example of a future ESA mission that needs high- 

resolution data conversion. 

To prepare for these future ESA missions, a feasibility study addressing the 

typical problems of high-resolution data conversion in space applications 

was started. Most systems use AC biased sensors, which enable bandpass 

sigma delta conversion. However, most bandpass converters are designed 

for telecom applications and the resonators used in these converters do 

not fit the requirements for instrumentation applications. SRON did design 

a new discrete time resonator suitable for high-resolution bandpass sigma 

delta conversion and put it on a test chip together with a sample & hold 

circuit and a digital block to generate the clock signals and the test op- 

tions. The chip was developed in cooperation with Xensor Integration, a 

small enterprise focussing on integrated sensors located in Delfgauw, the 

Netherlands. The chip was processed in the AMIS 0.35u CMOS process via 

the Europractice MPW service. 


19

20 

20/24 GHz VCO for Ka-band satellite or 

ISM-band application 

IMST GmbH, Kamp-Lintfort, Germany 

Contact : 

Olaf Kersten 

E-mail : kersten@imst.de 

Technology : IHP 0.25µ SG25H1 


Description 

IMST GmbH, Kamp-Lintfort, has de- 

signed a 20/24 GHz VCO (Voltage 

Controlled Oscillator) for Ka-band 

satellite or ISM-band applications. 

This development is funded and 

supported by the German Space 

Agency DLR/BMBF in the framework 

of the project KERAMIS “Ceramic 

Microwave Circuits for Satellite 

Communications” (Project ID = 50- 

YB-0317). Development and investi- 

gation of multilayer LTCC technology 


and other components like solid 

state power amplifier, synthesizer 

and re-configurable switch matrix 

are further tasks of the KERAMIS 

project. 

The presented VCO on SiGe is the 

first oscillator design aiming to 

achieve the following specifications 

in the given frequency bands: 

Tuning range: ftune = 500 MHz 

Tuning voltage: Vtune = 2 … 2.8 V 

Output power: Pout = 5 … 10 dBm 

Phase noise: Lf < –80 dBc/Hz @ 

100KHz offset 

While not all specifications have been 

met in the first cycle a re-design has 

already been initiated to fulfil the 

requirements. Re- 

sults are expected to 

be available in early 

2006. The SiGe-chip 

is intended to be uti- 

lized in future satel- 

lite multimedia appli- 

cations in Ka-band, 

while the 20 GHz 

range is reserved for 

satellites’ down-link 

(up-link: 30 GHz). Fi- 

nally the VCO will be 

encapsulated into a 

hermetically sealed 

LTCC package to fulfil 

space requirements. 

This technology will 

also be made evalu- 

ated for applications 

in the 24 GHz ISM- 

band. 

MARC : Muon Arm 

Readout Chip 

INFN and Cagliari University 

Strada prov.le per Sestu km 1.0 

09042 Monserrato (CA), Italy 

Contact : 

Gianluca Usai, Davide Marras 

E-mail : gianluca.usai@ca.infn.it, 

davide.marras@ca.infn.it 

web address: www.ca.infn.it and 

gruppo3.ca.infn.it 

Technology : austriamicrosystems 

0.6µ CUP 


Application 

The ALICE experiment at CERN is an 

experiment devoted to the study of 

new states of matter which can be 

possibly created in ultra relativistic 

heavy ion collisions. The experiment 

is one of the main 4 projects installed 

at the LHC accelerator at CERN which 

will start running in 2007. 

The Muon Arm is one of the ALICE 

sub-projects devoted to the de- 

tection of muon pair produced by 

heavy quark resonances as the J/psi 

and Y family. The detailed study of 

particle production will give evi- 

dence to transition to a new state of 

matter where the quarks and gluons 

(the constituents of protons and 

neutrons) will be deconfined (the so 

called quark-gluon plasma). 

The main part of the Muon Arm is 

a set of tracking stations made by 

multi-wire proportinal chambers 

which measure particle track points 

and momentum (with the help of a 

magnetic field).

Each chamber has segmented cath- 

ode planes (strips or pads) which 

produce a charge signal on the pas- 

sage of a particle. The charge is col- 

lected and converted to a digital 

number by the front-end electronics. 

ASIC description 

The front-end electronics of the 

Muon Arm tracking chambers is 

based on readout modules (called 

MANU) located onto the chamber 

surface (the first stations) or on its 

borders (in the slat topology) and 

performs local digitization and nu- 

merical compression. 

Each MANU module contains four 

MANAS chips which are directly con- 

nected to the pads and integrate 

the charge signal. 

The readout chip MARC (Muon Arm 

Readout Chip) controls the four 

MANAS chip and two serial ADC 

AD7476, and performs zero sup- 

pression on the data and communi- 

cates with a DSP ADSP2106 through 

a 4 bit bus developed by Analog 

Devices (Link Port). The Threshold 

value are stored in a 64 words x 12 

bit RAM. The 12 bit ADC words are 

latched in a temporary input shift 

register and compared with the 

RAM words. Data above threshold 

are then stored in a 64 words x 18 

bit FIFO together with 6 bit channel 

address. The data extracted from 

the FIFO are merged with the 11 bit 

module address word, a parity bit, 

and two control bit. The resulting 

32 bit word is sent through the Link 

Port as 8 nibbles of 4 bit each. 

The clock for MARC is generated 

using a 16 MHz quartz. The quartz 

is connected to an AMS oscilla- 

tor standard cell that works in the 

range 1-20 MHz. The chip internal 

logic must go at 40 MHz and the 

logic controlling the Link Port runs 

at 80 MHz. A PLL was designed to 

multiply the frequency to the de- 

sired value. The PLL is based on a 

pulse frequency detector and VCO 

(voltage controlled oscillator). 

The local bus connecting the MANU 

modules uses LVTTL logic. The MARC 

Link Port output drivers can source/ 

sink 32 mA. They are realized inter- 

nally with 4 - 8 mA tristate drivers. 

Externally each output driver has 

two pins in the package which must 

be tied together in the PCB. 

Several modules are connected in 

daisy chain and share the same Link 

Port bus. In fig. 1 a diagram of the 

chip is shown along with the inputs/ 

outputs. The chip is designed in the 

austriamocrosystems 0.6µ CMOS 

3.3V technology. 

Why Europractice ? 

Prototypes were made for design 

verification through Europractice. A 

pre-series using MPW production 

and plastic packaging was used for 

verifying functionality with radia- 

tion to be expected in the applica- 

tion. The final production of 28,000 

parts was done using a single tool- 

ing maskset in austriamicrosystems 

0.6µ CMOS technology with a cus- 

tom asynchronous test solution us- 

ing an Agilent 93000 tester. 


21

22 

Polymeric chemoresistive 

gas sensors 

School of Engineering, 

University of Warwick, 

Coventry CV4 7AL, 

United Kingdom 

Contacts : 

Marina Cole, Jesús García-Guzmán 

and Julian W. Gardner 

E-mail : Marina.Cole@warwick.ac.uk 

Technology : 

AMIS 0.7µ CMOS 1P2M analog 

Die size : 3300 x 3750 µm 2 

Description 

The chip is a second generation chip 

fabricated through Europractice AMIS 

0.7µm C07M-A process as a part of 

a PhD research project (García-Guz- 

mán) conducted at Warwick Univer- 

sity for the monitoring of volatile or- 

ganic compounds (VOCs) or gases. 

The design integrates two polymeric 

chemoresistive gas sensors in a nov- 

el ratiometric configuration, togeth- 

er with smart circuitry, into a single 

chip. The circuit provides automatic 

compensation of signal from vari- 

ations in both supply voltage and 

ambient temperature. On-chip con- 

trol of the operating temperature of 

the sensors is also an option. As 

part of the research programme, 

the response of the ratiometric set 

of polymeric chemoresistors to dif- 

ferent concentrations of gases at 

different temperatures and humidi- 

ties was simulated with the aid of 

a novel parametric Cadence model 

(also developed at Warwick) prior to 

fabrication. Simulations confirmed 

that the ratiometric configuration is 

less sensitive to temperature vari- 


ations and that it also has a better 

performance in terms of humidity 

dependence when compared to in- 

dividual chemoresistors. 

Figure1 shows the overall structure 

of the new smart gas sensor sys- 

tem. The main component is the 

ASIC chip, which performs two ba- 

sic functions: (a) sensing the gas 

presence and concentration, and 

(b) controlling the operating tem- 

perature of the gas sensor. Within 

the ASIC chip, the top section cor- 

responds to the gas sensor circuit, 

whereas the bottom sections corre- 

spond to temperature control and 

monitoring. A micro-controller unit 

is used for processing the inputs 

and outputs of the ASIC chip. Ad- 

ditionally, three digitally controlled 

potentiometers (available in the Xi- 

cor’s X9258 integrated circuit) are 

used in order to accomplish some 

specific trimming functions. The 

performance of the first generation 

chip agreed with simulations and 

the detailed design description and 

test results have been published in 

the following references: 

1. Garcia-Guzman J., Ulivieri N., Cole 

M., and Gardner J.W., Design and 

simulation of a smart ratiometric 

ASIC chip for VOC monitoring, Sen- 

sors and Actuators B, 95 (2003), 

pp. 232-243. 

2. Gardner, J.W., Garcia-Guzman, J. and 

Cole, M., Smart ASIC chip for va- 

pour detection based upon carbon 

black/polymer composite nanoma- 

terials, Proc. of SPIE Conference 

on Smart Electronics, MEMS, Bi- 

oMEMS, and Nanotechnology, Vol. 

5389, 14-18 March 2004, San Di- 

ego, California, USA, pp. 344-354. 

Figure 1 : Block diagram 

representation of the ra- 

tiometric sensor system

PhD designs at KULeuven 

Katholieke Universiteit Leuven – KULeuven 

ESAT-MICAS department, Leuven, Belgium 

Contact : 

Michiel Steyaert 

E-mail : michiel.steyaert@esat.kuleuven.be 

Technology : UMC 0.18µ CMOS 1P6M mixed-mode RF 

Die size : 5 x 5 mm 2 

The Europractice facilities enabled designers of ESAT-MICAS to design circuits dealing with important issues in CMOS 

design. The first circuit is related to high-speed sigma delta converters. A new implementation of discrete-time sec- 

ond-order Sigma-Delta Converters has been investigated. The novel architecture developped enables the converter 

to operate at a higher sampling frequency. This allows the use of a simple filter topology while maintaining a good 

accuracy. The second circuit is a CMOS power amplifier for the GHz range. The chosen functionality is class E and 

the design makes use of power combining. The third circuit is a 8KByte low-power embedded SRAM with improved 

robustness against variability and a built-in delay measurement circuit. Finally, the fourth design consists of an 

opto-electrical interface circuit for gigabit optical communication. The circuits contains an integrated photodiode 

which captures the light, followed by a transimpedance amplifier to convert the small diode current into a voltage. 

A post-amplifier boosts the signal to an on-chip voltage swing of 1.2V and an output buffer drives the 50 Ohm load 

of the measurement equipment. All these circuits have been designed in UMC 0.18u within the Cadence environment 

and are being tested within our facilities at MICAS Leuven. The obtained results will be published in international 

and european microelectronics conferences. 

MIMO-OFDM Transceiver Chip 

Integrated Systems Laboratory, ETH Zurich, Gloriastrasse 35, CH-8092 Zurich, Switzerland 

Contact : 

Andreas Burg 

E-Mail : apburg@iis.ee.ethz.ch 

Technology : 

UMC 0.25µ CMOS 


Description 

Multiple-input multiple-output (MIMO) systems employ multiple antennas at both transmitter and receiver to significantly 

improve link reliability and throughput of wireless communication systems. These gains come at no additional trans- 

mit power or bandwidth expenditure. MIMO is considered the key enabling technology for future wireless local area 

networks (WLANs) and wireless local loop systems targeting peak data rates of up to 1 Gbps. While ASICs for the IEEE 

802.11a standard have been presented, little is known about suitable VLSI architectures for MIMO-OFDM systems and 

the corresponding silicon complexity. Goal of this project was to realize an ASIC implementation of a MIMO-OFDM WLAN 

transceiver with up to four transmit and receive antennas. The design supports datarates of up to 192 Mbps and consti- 

tutes one of the fastest WLAN ASIC realizations to date. Its architecture is based on the MIMO-OFDM testbed developed 

at ETH and comprises the complete baseband processing part including de/modulation, frequency offset estimation and 

compensation, frame start detection, and the MIMO detector. The ASIC with a die area of 25 mm 2 was manufactured in a 

250nm 1P/5M CMOS technology. The ASIC running at a system clock frequency of 80 MHz was sucessfully tested. 


23

24 

A zero-IF receiver for WCDMA and WLAN 802.11b 

Royal Institute of Technology – KTH, Kista, Sweden 

Contact : 

Wim Michielsen 

E-mail : wmich@imit.kth.se 

Technology : 

UMC 0.18µ CMOS 1P6M mixed- 

mode RF 

Die size : 1525 x 1525 µm 2 

The following description pertains 

to a chip that we, at the Radio and 

Mixed Signal Circuit and System De- 

sign (RaMSiS) Group from KTH in 

Sweden, have designed and fabri- 

cated through the EUROPRACTICE 

service in February 2005. 

Application 

The chipset is a reconfigurable 

zero/low-IF analog down-converter 

for WCDMA and WLAN 802.11b sig- 

nals. It is our first integrated chip 

for study of future fourth generation 

(4G) wireless multiband reconfig- 

urable radio receivers. The aim is to 

demonstrate the performance and 


the suitability of a reconfigurable 

zero/low-IF architecture. 

ASIC description 

The RF front-end blocks are opti- 

mized to cover the 1.7 – 2.5 GHz fre- 

quency working range. A multiband 

VCO with digital switch for switch- 

ing the working frequency band is 

placed off-chip. The on-chip compo- 

nents comprise a single-ended LNA, 

a single-to-differential converter, 

mixers, a polyphase filter for the 

quadrature signal generation and 

output drivers after the mixers. 

Implementation 

The chip is manufactured in the 0.18 

µm MM/RF technology of UMC. We 

wanted to see the effect of package 

parasitics. So the dies are packaged 

into refurbished MLF-24 packages 

and mounted on a test PCB board. 

Why EUROPRACTICE ? 

The UMC MM/RF 0.18µm designkit 

conveys the basic needs for our 

RF CMOS designs. For university 

research purposes it is crucial that 

we have access to the cheaper MPW 

runs from EUROPRACTICE. We could 

also benefit from the packaging serv- 

ices from EURPRACTICE. In our case 

we obtained the most cost effective 

solution by packaging our chips in 

refurbished MLF-24 packages with- 

out compromising the quality. 

Project information 

www.imit.kth.se/info/FOFU/ramsis/

Designs at Aalborg 

University 

Aalborg University 

Risc Division, Aalborg, Denmark 

Contact : 

Jan Mikkelsen 

E-mail : jhm@kom.aau.dk 

Technology : 

UMC 0.25µ CMOS 1P5M mixed-mode RF 


Description 

The design contains a number of 

different test circuits for different 

applications. A few circuits are de- 

signed for UWB operation in the 

3-5GHz band. Specifically, a very 

linear and very low-power multiplier 

has been designed for this applica- 

tion. Further, the design contains a 

number of different power amplifier 

implementations. Some of the de- 

signs aim for UMTS applications and 

both single-stage and two-stage 

implementations are implemented. 

In addition a number of structures 

have been included to evaluate the 

cross-coupling between planar in- 

ductor structures and specifically 

how to measure this correctly. 

Samira : 8-way SIMD-Vector floating point 

processor 

University of Dresden, Germany 

Institut Nachrichtentechnik 

Contact : 

Hendrik Seidel 

E-mail : seidel@ifn.tu-dresden.de 

Technology : 

UMC 0.13µ CMOS 1P8M 


Description 

The Samira DSP is an 8-way SIMD-Vector 

floating point processor based on a novel 

microarchitecture concept. It can be re- 

garded as a programmable accelerator for 

a number crunching tasks in signal process- 

ing applications. The processor consumes 

1.8mW/MHz running a single precision float- 

ing-point FFT in 1890 cycles. The pure core 

power is less than 0.57mW/MHz for clock 

rates up to 212MHz. So far a moving jpeg 

decoder (15fps, 640x480) has been imple- 

mented on the DSP and was attached to a 

FPGA to enable connectivity through differ- 

ent interfaces like an ethernet interface and 

a VGA controller. With 100% responsibility 

for the overall design process the Vodafone Chair, TU-Dresden was able to 

land a first time right design with Europractice IC Services. 

The SAMIRA design features: 

• 17 single-precision floating 

point units 

• ~ 480k NAND gates (UMC 

0.13µm) 

• 2.9 Mbit on-chip SRAM 

• Multiple memory banks for 

synchronous access 

• Compressed VLIW decoder 

• 120-PQFP package 


25

26 

The CASTLE emulated digital array processor 

Hungarian Academy of Science 

Computer and Automotion Institute 

Analogic and Neural Computing Systems Laboratory 

Budapest, Hungary 

Contacts : 

T. Hidvégi, P. Keresztes and P. 

Szolgay 

E-mail : szolgay@sztaki.hu 

Technology : 

austriamicrosystems 0.35µ CMOS 

Die size : 68 mm 2 

Description 

Emulated digital CNN approaches fo- 

cus on the solution of some problems 

occurred in the analog VLSI imple- 

mentation of a Cellular Neural Network 

Universal Machine (CNN-UM). The ac- 

High Performance ADC 

VTT, Finland 

Contact : 

Markku Aberg 

E-mail : markku.aberg@vtt.fi 

Technology : 

austriamicrosystems 0.35µ 

(SiGe/HBT BiCMOS - S35) 



curacy, the usage of nonlinear tem- 

plate operations and the implemen- 

tation of multilayer structures are 

some of the problems to be solved by 

an emulated digital CNN-UM proces- 

sor array. The speed of the emulated 

digital CNN-UM solution should not 

be smaller by 2 order of magnitude 

than that of an analog CNN-UM. 

A 2 x 3 emulated digital CNN proces- 

sor array (CASTLE ARRAY processor 

array) was designed and implement- 

ed by using a 0.35µ CMOS technolo- 

gy with variable accuracy and with a 

A high performance analog-to-digital 

converter (ADC) has been designed 

and implemented. The 10-bit ADC op- 

erates at the sampling rate of 2GS/s. 

A time-interleaved pipeline topology 

is utilized to achieve the required 

specifications. The ADC samples over 

500 MHz (>1GHz ERBW) input band 

and uses digital background calibra- 

tion to overcome errors arised from 

parallelism. The ADC is optimized in 

terms of power consumption which 

quanrantees maximum efficiency 

in operation. Thus, “low” power 

(< 5W@3.0VDD) operation should 

be achieved. Low-jitter clock delay- 

locked loop (DLL) based generator 

was implemented to provide re- 

quired high accuracy phases for ADC 

fingers. A total timing accuracy of 

around 1 ps is required to maintain 

1 ns/ virtual CNN cell/iteration speed 

supposing 12-bit-accuracy. 

The processor array was interfaced to 

Aladdin Pro where this hardware-soft- 

ware environment provides the same 

high-level support to develop ana- 

logic CNN algorithms that we have by 

using the analog VLSI CNN-UMs. 

ENOB value. The DLL was designed in 

such manner that jitter is minimised 

and a 8 bit skew calibrator was inte- 

grated into each clock phase output. 

The maximum range and resolution 

of the skew calibrator are 128 ps and 

0.5 ps, respectively. 

The ADC chip was laid out using an 

0.35 µm SiGe technology by Austria 

Microsystems. The chip measures 6.9 

x 5.8 mm and consists totally around 

200 000 components. The ADC has al- 

ready processed and the measurement 

results will be available Q2/2006. 

Project participants: Helsinki University 

of Technology, VTT and Nokia 

Acknowledgements: This work has been 

supported by European Space Agency, 

contract nr. AO/1-3939/01/NL/JSC.

Thrane&Thrane’s Explorer500 : 

broadband satellite terminal 

Thrane&Thrane, Denmark 

Contact : 

Allan Sørensen 

E-mail : ATS@thrane.com 

Technology : 

UMC 0.18µ CMOS 

Introduction 

Inmarsat, specialist in Satellite communication, has 

launched its first satellite for Broadband Global Area 

Network (BGAN) services. This service is accessible via 

a small lightweight, satellite terminal, which is easy to 

carry, quick to set up, simple to use, and the same device 

can be used worldwide. One of such terminals is the 

Explorer 500 from Thrane&Thrane (Denmark), the world’s 

leading manufacturer of terminals and land earth stations 

for global mobile satellite and radio communications. 

Applications 

Explorer500 

The Explorer500 combines exceptional per- 

formance with portability. It meets the 

needs of the most demanding business 

traveler for remote, high-speed access 

to corporate networks. With the same 

device you get access worldwide. The 

Explorer500 is very small, less than 22 

x 22 x 5.5 cm and weighs only 1.5 kg. 

The Explorer500 is able to offer remote access, high speed 

internet access (up to 464 kbps), email, telephony, streaming 

and file transfer. The key benefits are simultaneous voice 

and broadband data, global coverage, easy to use, highly 

flexible (supports circuit-switched and IP packet data via 

standard LAN, USB, Bluetooth and phone/fax interfaces). 

The baseband ASIC 

Thrane&Thrane performed the front-end VHDL design and 

test vector generation while IMEC provided RTL-to-layout 

service, prototyping and volume production logistics, includ- 

ing wafer forecast, production and packaging. The selected 

technology is the well-proven UMC 0.18µ logic CMOS tech- 

nology. The package is a BGA452 Ball-Grid Array. The devel- 

opment was quite successful and resulted in first-time-right 

prototypes (although the die was larger than 200 mm 2 ). 

Production ramp-up 

After successful prototyping, IMEC and Thrane&Thrane care- 

fully planned the forecast for ramp-up with UMC in order 

to get delivery of first Explorer500 terminals to the market 

on time when Inmarsat’s BGAN service became operational 

by the end of 2005. Currently IMEC is delivering several 

thousands of ASICs per month to Thrane&Thrane. 

Why Europractice ? 

The satellite communication service is still a very niche 

market where the terminal providers sell less than 100k 

units per year. On the other hand the required ASICs are 

quite complex and need the most advanced technolo- 

gies such as the UMC 0.18µ CMOS technology. Getting 

access to the larger foundries such as UMC for small vol- 

umes is very difficult. Europractice provided the service 

needed and the access to the foundry. 


27

UMCIC2 : new design structures for chip-to-chip communication, 

power optimization and fault-tolerant design 

Ecole Polytechnique Fédérale de Lausanne (EPFL) 

Microelectronic Systems Laboratory (LSM) 

CH - 1015 Lausanne 

Switzerland 

http://lsm.epfl.ch 

Contact : 

Prof. Yusuf Leblebici 

E-mail : yusuf.leblebici@epfl.ch 

Technology : 

UMC 0.18µ CMOS 1P6M mixed-mode 

Die size : 5x5 mm 2 

The Microelectronic Systems Labo- 

ratory of the Ecole Polytechnique 

Fédérale de Lausanne (EPFL) has 

a research focus on next-genera- 

tion digital and mixed-signal VLSI 

circuits, covering topics from high- 

performance digital logic styles over 

chip-to-chip communications and 

power optimization to fault-tolerant 

design styles for nanometer-scale 

technologies. 

Why Europractice? 

Such a vast coverage of research 

topics requires access to flexible 

and affordable technologies. The 

moderate cost of integration, com- 

bined with first-class customer sup- 

port and a large number of runs per 

year in state-of-the-art technologies 

minimizes the manufacturing risks 

and guarantees short design cycles. 

ASIC Description 

The main parts of the presented cir- 

cuit are a novel multi-channel clock 

recovery system, limiting amplifiers 

for multi-channel fiber-optic commu- 

nication links and a power manage- 

28 europractice | examples 

ment controller for advanced power 

management of digital cores. Fur- 

ther more, it includes several test 

blocks for high-performance A/D 

conversion, ultra low-power stand- 

ard cell design and opto-electronic 

conversion. The extremely low area 

and low-power multi-channel clock 

and data recovery (CDR) circuit fully 

benefits of the small feature size 

and the speed offered by this digital 

technology to achieve 

2.5-Gbps/channel data retiming 

with a power consumption of only 

3.5mW/Gbps. The power manage- 

ment controller implements a novel 

on-line energy optimization algo- 

rithm, which is capable of dynami- 

cally adjusting power supply volt- 

ages and operating frequencies of 

multiple processing elements as 

a function of their instantaneous 

workload conditions.

List of Customers per country and number of 

designs they have sent in for MPW fabrication 

CUSTOMER TOWN Number 

of ASICs 

Australia 

Edith Cowan University Joondalup 11 

Motorola Australian Ressearch Centre Botany 1 

University of South Wales Sydney 1 

Austria 

ARC Seibersdorf Research Vienna 1 

austriamicrosystems Unterpremstaetten 53 

Austrian Aerospace Wien 1 

Carinthia Tech Institute Villach-St.Magdalen 1 

IEG Stockerau 1 

Johannes Keppler University Linz 3 

MED-el 2 

Securiton Wien 1 

TU Wien Vienna 4 

Belgium 

Alcatel Space Hoboken 4 

AnSem Heverlee 2 

Browning International SA Herstal 1 

Cochlear Technology Centre Europe Mechelen 9 

ED&A Kapellen 3 

Faculte Polytechnique de Mons Mons 7 

FillFactory Mechelen 2 

ICI - Security Systems Everberg 6 

IMEC Leuven 114 

K.U. Leuven Heverlee 80 

Katholieke Hogeschool Brugge-Oostende Oostende 23 

KHLim Diepenbeek 6 

KHK Geel 4 

KIHA Hoboken 2 

Macq Electronique Brussel 1 

Neurotech Louvain-la-Neuve 1 

Q-Star Test nv Brugge 2 

SDT International Bruxelles 1 

SEBA Service N.V. Grimbergen 1 

SIEMENS ATEA Herentals 2 

SIPEX Zaventem 4 

Societe de Microelectronique Charleroi 1 

Universite catholique de Louvain Louvain-la-Neuve 14 

Universiteit Gent Gent 52 

University of Antwerp Wilrijk 3 

Vrije Universiteit Brussel Brussels 62 



Brazil 

CenPRA Campinas 2 

CPqD - Telebras Campinas 7 

UFPE Recife-PE 1 

UNESP/FE-G Guaratingueta - SP 3 

UNICAMP- University of Campinas Campinas, SP 17 

Universidade de Sao Paulo Sao Paulo-SP 31 

Bulgaria 

Technical University of Sofia Sofia 2 

Canada 

Canadian Microelectronics Corporation Kingston, Ontario 9 

Epic Biosonics Victoria 4 

University of Alberta Edmonton 1 

University of Toronto Toronto 1 

University of Waterloo Waterloo 1 

China 

Dept.Computer Science and Technology BeiJing 1 

Fudan University Shanghai 2 

Microelectronics Center Harbin 1 

The University of Hong Kong Hong Kong 4 

Hong Kong Univ. of Science & Technology Hong Kong 1 

Zhejiang University Yuquan 1 

Croatia 

University of Zagreb Zagreb 1 

Czech Republic 

ASICentrum s.r.o. Praha 4 5 

Brno University of Technology Brno 2 

Czech Technical University-FEE Prague 5 

Denmark 

Aalborg University Aalborg 22 

Algo Nordic A/S Cph 1 

Bang & Olufsen Struer 4 

DELTA Hoersholm 11 

GN-Danavox A/S Taastrup 4 

Microtronic A/S Roskilde 10 

Oticon A/S Hellerup 9 

PGS Electronic Systems Frb. 1 

europractice | list of costumers 

29



Techtronic A/S Roskilde 1 

Tecnical University of Denmark Lyngby 38 

Thrane&Thrane Lyngby 1 

Egypt 

Bahgat Group - IEP Cairo 4 

Estonia 

Tallinn Technical University Tallinn 1 

Finland 

Detection Technology Inc. Li 1 

Fincitec Oy Oulu 4 

Helsinki University of Technology Espoo 39 

Nokia Networks Espoo 2 

Tampere University of Technology Tampere 8 

University of Oulu Oulu 12 

VTI Technologies Vantaa 2 

VTT Electronics Espoo 81 

France 

Atmel Nantes, Cedex 3 3 

C4i Archamps 13 

CCESMAA -IXL Talence 2 

CEA Grenoble 20 

CMP-TIMA Grenoble 7 

CNES Toulouse Cedex 01 4 

CPPM Marseille 2 

Dibcom Palaiseau 1 

Dolphin Integration Meylan 4 

EADS Defense&security 1 

ELA Recherche Meylan 4 

ENSEA Cergy Pontoise 2 

ENST Paris Paris 2 

ESIEE Noisy Le Grand 3 

IN2P3 - LPNHE Paris Cedex 5 6 

Institut des Sciences Nucleaires Grenoble 5 

Institut de Physique Nucleaire Villeurbanne 7 

Institut Sup. d Electronique de Bretagne Brest 2 

ISEN Recherche Lille cedex 3 

LAAS/CNRS Toulouse 4 

Labo PCC CNRS/IN2P3 Paris cedex05 2 

Laboratoire de l Accelerateur Lineaire Orsay 6 

LAPP Annecy-le-Vieux 7 

LEA Cesson Sevigne 1 

LEPSI Strasbourg 15 

LETI-CEA Grenoble 4 

LIRMM Montpellier 2 

Midi Ingenierie Labege 1 

MXM Laboratories Vallauris 3 

30 europractice | list of costumers 



NeoVision France Bagneux 3 

PMIPS - IEF Orsay 2 

SODERN Limeil-Brevannes 2 

SUPAERO Toulouse Cedex 28 

Supelec Gif-sur-Yvette 3 

TTPCOM Sophia Antipolis 1 

Universite Pierre et Marie Curie Paris 4 

Vision Integree Nogent sur Marne 3 

Germany 

AEG infrarot-module 1 

ALV-Laser Vertriebsgesellschaft mbH Langen 1 

austriamicrosystems Dresden 2 

Balluff 1 

Bergische Universitaet Wuppertal Wuppertal 1 

Biotronik GmbH & Co Erlangen 9 

Bruker AXS 1 

Bruker Biospin 2 

Cairos Technologies Karlsbad 8 

Comtech GmbH St. Georgen 3 

Daimler-Benz AG Ulm 3 

Darmstadt University of Technology Darmstadt 3 

Dr. Johannes Haidenhain 1 

ESM Eberline Erlangen 1 

ETA Erlangen 1 

Fachhochschule Aalen Aalen 3 

Fachhochschule Augsburg Augsburg 1 

Fachhochschule Bremen Bremen 2 

Fachhochschule Darmstadt Darmstadt 8 

Fachhochschule Dortmund Dortmund 2 

Fachhochschule Esslingen Goeppingen 2 

Fachhochschule Furtwangen Furtwangen 6 

Fachhochschule Giessen-Friedberg Giessen 11 

Fachhochschule Koeln Gummersbach 3 

Fachhochschule Mannheim Mannheim 1 

Fachhochschule Nuernberg Nuernberg 1 

Fachhochschule Offenburg Offenburg 16 

Fachhochschule Osnabrueck Osnabrueck 4 

Fachhochschule Pforzheim Pforzheim 1 

Fachhochschule Ulm Ulm 10 

Fachhochschule Wilhelmshaven Wilhelmshaven 1 

Fachhochschule Wuerzburg Wuerzburg 1 

FAG-Kugelfischer Schweinfurt 3 

FH Hannover Hannover 3 

FH Karlsruhe Karlsruhe 1 

FH Niederrhein Krefeld 5 

FhG-IIS Erlangen 124 

FH-Münster Steinfurt 1 

FORMIKROSYS Erlangen 2 

Fraunhofer ISC 1



Fraunhofer institute silicontechnology Itzehoe 17 

Friedrich-Schiller-University Jena 1 

GEMAC Chemnitz 7 

Geyer Nuernberg 6 

GMD St. Augustin 1 

GSI Darmstadt 9 

iAd GmbH Grosshabersdorf 1 

IHP Frankfurt(Oder) 1 

IIP-Technologies GmbH Bonn 4 

IMKO Micromodultechnik GmbH Ettlingen 3 

IMST GmbH Kamp-Lintfort 3 

INOVA Semiconductor Munich 1 

Institute for Integrated Systemes Aachen 1 

Institute of Microsystem Techology Freiburg 2 

Jakob Maul GmbH Bad Koenig 1 

Johannes Gutenberg-Universitaet Mainz 9 

KVG Quatrz Crystal Neckarbisch 1 

Hella 1 

Lenze GmbH Aerzen 2 

LHR Comtech St. Georgen 1 

MAN Nüremberg 1 

Max Planck Institute Munchen 1 

MAZ Brandenburg Brandenburg 2 

MEODAT Ilmenau 2 

Metzeler Automotive 3 

MPI-Halbleiterlabor Munich 2 

NeuroConnex Meckenheim 1 

Optek Systems Innovations 1 

OPTRONICS 1 

Phisikalisches Institut Bonn 20 

Preh Werke NA 2 

Rechner Industrieelektronik GmbH 1 

Ruhr-University Bochum Bochum 4 

RWTH Aachen Aachen 8 

Scanditronix Wellhöfer NA 3 

Schleicher GmbH & Co Relais-Werke KG 1 

Schleifring und Apparatebau GmbH 1 

Sican Braunschweig GmbH Braunschweig 1 

Siemens 4 

Seuffer Calw-Hirsau 5 

Technical University Ilmenau Ilmenau 14 

Technical University of Berlin Berlin 11 

Trias Krefeld 1 

Trinamic Hamburg 1 

TU Berlin Berlin 5 

TU Chemnitz Chemnitz 11 

TU Darmstadt Darmstadt 11 

TU Dresden Dresden 17 

TU Hamburg-Harburg Hamburg 22 

Universitaet Dortmund Dortmund 2 



Universitaet Hannover Hannover 11 

Universitaet Kaiserslautern Kaiserslautern 9 

Universitaet Paderborn Paderborn 11 

Universität Rostock Rostock 7 

University of Bonn Bonn 29 

University of Bremen Bremen 26 

University of Freiburg Freiburg 3 

University of Heidelberg Heidelberg 31 

University of Kassel Kassel 5 

University of Magdeburg Magdeburg 11 

University of Mannheim Mannheim 8 

University of Munich Munich 1 

University of Oldenburg Oldenburg 1 

University of Saarland Saarbruecken 4 

University of Siegen Siegen 13 

University of Stuttgart Stuttgart 1 

University of Ulm Ulm 3 

Vishay semiconductor Heilbronn 2 

Wellhoeffer Schwarzenbruck 2 

Work Microwave GmbH Holzkirchen 1 

Greece 

ACE Power Electronics LTD AG Dimitrios 1 

Aristotle Univ. of Thessaloniki Thessaloniki 4 

Athena Semiconductors SA Alimos - Athens 2 

Crypto SA Marousi 1 

Datalabs Athens 1 

Democritus University of Thrace Xanthi 3 

Found. for Research and Techn.-Hellas Heraklion 1 

InAccess Athens 1 

HELIC SA Athens 1 

Hellenic Semiconductor Applications Athens 2 

Intracom Paiania 1 

National Tech. Univ. of Athens Athens 14 

NCSR Athens 22 

NTNU n/a 2 

RETECO LTD. Athens 1 

Unibrain SA Athens 1 

University of IONNINA Ioannina 2 

University of Patras - VLSI Laboratory Rio - Patras 18 

Hungary 

Hungarian Academy and Science Budapest 1 

Peter Pazmany Catholic University Budapest 1 

Computer and Automation Inst. Budapest 6 

JATE University Szeged 1 

India 

College of Eng. Guindy Anna Univesity Chennai 1 

Indian Institute of Science Bangalore 3 


31



IIT Madras Chennai 5 

Indian Institute of Science New Dehli 1 

VECC Kolkata 3 

Ireland 

Cork Institute of Technology Cork 3 

National University of Ireland Kildare 1 

Farran Technology Ballincollig 1 

National Microelectronics Research Cent. Cork 15 

Parthus Technologies (SSL) Cork 7 

TELTEC Cork 1 

University College Cork Cork 2 

University of Limerick Limerick 9 

Waterford Institute of Technology Waterford 7 

Israel 

CoreQuest Petach Tikva 2 

DSP Semiconductors Givat Shmuel 1 

Technion - Israel Institute of Techn. Haifa 4 

Italy 

Alcatel Alenia L’Aquila 1 

Alimare SRL Favria Canavese 

(Torino) 1 

Aurelia Microelettronica S.p.A. Navacchio PISA 18 

BIOTRONIC SRL San Benedetto 1 

Cesvit Microelettronica s.r.l. Prato 2 

DEEI - University of Trieste Trieste 2 

INFN Bologna 1 

INFN Cagliari 1 

INFN Catania 4 

INFN Ferrara 1 

INFN Milano 1 

INFN Genova 2 

INFN Padova 2 

INFN Roma 10 

INFN S.Piero a Grado 

(PISA) 2 

INFN Torino 4 

INFN Trieste 7 

Instituto di Sanita Roma 1 

Instituto Trentino di Cultura Trento 21 

ISE Vecchiano 1 

LABEN S.p.A. Vimodrone (MI) 3 

Optoelettronica Italia Terlago 1 

Politecnico di Bari Bari 4 

Politecnico di Milano Milano 53 

Politecnico di Torino Torino 5 

Sincrotrone Trieste SCpA Trieste 3 

SITE Technology s.r.l. Oricola 1 




SYEL S.r.l. Pontadera 1 

Universita degli Studi Dell Aquila L Aquila 3 

Universita di Torino Torino 7 

Università degli Studi di Ancona Ancona 4 

Universita degli Studi di Firenze Firenze 2 

Universita di Cagliari Cagliari 6 

Universita di Catania Catania 38 

University of Bologna Bologna 20 

University of Brescia Brescia 6 

University of Cagliari Monserrato-Cagliari 8 

University of Genova Genova 13 

University of Modena Modena 1 

University of Naples Napoli 1 

University of Padova Padova 23 

University of Parma Parma 6 

University of Pavia Pavia 7 

University of Perugia Perugia 6 

University of Pisa Pisa 15 

University of Rome Tor Vergata Roma 5 

University of Siena Siena 2 

Japan 

Marubeni Solutions Osaka 8 

Hokkaido University Sapporo 6 

Yamatake Kanagawa 1 

Korea 

JOSUYA TECHNOLOGY Taejon 1 

KAIST Daejeon 1 

Korean Elektrotechnology Research Inst. Changwon 1 

Macam Co., Ltd Seoul 2 

Nurobiosys Seoul 7 

Samsung Electro-Mechanics Suwon 1 

Seoul National University Seoul 1 

Seloco Seoul 10 

Malaysia 

SunSem Sdn. Bhd. Kuala Lumpur 1 

University of Technology Skudai 1 

Malta 

University Of Malta Msida 14 

Mexico 

INAOE Puebla 23 

Netherlands 

Aemics Hengolo 8 

Catena Microelectronics BV Delft 1 

Cavendish Kinetics s Hertogenbosch 1



Delft University of Technology Delft 17 

ESA AG Noordwijk ZH 3 

Hogeschool Heerlen Heerlen 1 

Lucent Technologies Nederland BV Huizen 1 

Mesa Research Institute Twente 1 

NFRA Dwingeloo 1 

Sonion Amsterdam 3 

Smart Telecom Solutions 1 

SRON Utrecht 4 

Technische Universiteit Eindhoven Eindhoven 44 

TNO Industrie Eindhoven 1 

TNO -FEL The Hague 2 

TU Delft Delft 40 

University of Amsterdam Amsterdam 1 

University of Twente Enschede 5 

Xanadu Wireless Utrecht 1 

Xensor Integration Delfgauw 3 

New Zealand 

Industrial Research Ltd Lower Hutt 4 

Norway 

AME As Horten 1 

Nygon Asker 1 

IDE AS Oslo 2 

Interon Asker 1 

Nordic VLSI Trondheim 38 

Norwegian Institute of Technology Trondheim 18 

SINTEF Trondheim 6 

University of Bergen Bergen 6 

University of Oslo Oslo 62 

Poland 

AGH Univ. of Science and Technology Krakow 3 

Institute of Electron Technology Warsaw 34 

Technical University of Gdansk Gdansk 3 

Technical University of Lodz Lodz 4 

University of Mining and Metallurgy Krakow 24 

University of Technology & Agriculture Bydgoszcz 1 

University of Technology - Poznan Poznan 1 

Warsaw University of Technology Warsaw 14 

Portugal 

Acacia Semiconductor Lisboa 6 

Chipidea Oeiras 22 

INESC Lisboa 16 

INETI Lisboa 1 

Instituto de Telecomunicacoes Lisboa 28 

Instituto Superior Tecnico Lisboa 6 

Universidade de Aveiro Aveiro 18 



University of Minho Guimaraes 4 

University of Porto Porto 2 

ISEL-IPL LIsboa 1 

University of Tras-os-Montes e Alto Vila Real 2 

Uninova Caparica 5 

Romania 

Polytechnic inst. Bucharest Bucharest 1 

Russia 

MIET-TU Moscow 2 

Moscow Engineering Physics Institute Moscow 1 

University St Petersburg St Petersburg 3 

Serbia and Montenegro 

University of Nis Nis 1 

Singapore 

Agilent Singapore 2 

DSO National Laboratories Singapore 6 

Slovakia 

Inst. of Computer Systems Bratislava 1 

Slovak University of Technology Bratislava 3 

Slovenia 

Iskraemeco d.d. Kranj 19 

NOVOPAS Maribor 1 

University of Ljubljana Ljubljana 8 

South Africa 

Solid State Technology Pretoria 4 

University of Pretoria Pretoria 16 

South America 

CNM/Iberchip 74 

Spain 

Anafocus Sevilla 1 

CNM Bellaterra 27 

Design of Systems on Silicon Paterna 7 

EUSS Barcelona 1 

Facultad de Informática UPV/EHU San Sebastián 2 

Technical University of Madrid Madrid 3 

Univ. Las Palmas Gran Canaria Las Palmas/Gran Canaria 7 

Universidad Cartagena 2 

Universidad de Cantabria Santander 9 

Universidad de Extremadura Badajoz 17 

Universidad de Navarra San Sebastian 31 

Universidad del Pais Vasco Bilbao 3 


33



Universidad Politecnica de Madrid Madrid 1 

Universidad Publica de Navarra Pamplona 12 

Universitat autonoma de Barcelona Barcelona 10 

Universitat de Barcelona Barcelona 24 

Universitat Illes Balears Palma Mallorca 3 

Universitat Politecnica de Catalunya Barcelona 20 

Universitat Rovira i Virgili Tarragona 2 

University of Malaga Malaga 2 

University of Sevilla - CNM - Sevilla 60 

University of Seville Sevilla 17 

University of Vigo Vigo 3 

University of Zaragoza Zaragoza 16 

Sweden 

Bofors Defence AB 2 

Chalmers University Goteborg 6 

Chalmers University of Technology Gothenburg 66 

Defence Researh Establishment Linkoping 5 

Ericsson Molndal 2 

Ericsson Microelectronics Kista 2 

Institutet for Rymdfysik Kiruna 1 

Imego AB Goteborg 1 

Lulea University of Technology Lulea 8 

Lund University Lund 164 

Malardalens University Vasteras 2 

Mid Sweden University Sundsvall 12 

Royal Institute of Technology Kista 21 

Saab Ericsson Space AB Goteborg 1 

SiCon AB Linkoping 4 

Svenska Grindmatriser AB Linkoping 3 

University of Trollhattan Trollhattan 3 

University of Linköping Linköping 151 

Uppsala University Uppsala 11 

Switzerland 

Asulab SA Marin 22 

austriamicrosystems 2 

Bernafon Bern 1 

Biel School of Engineering Biel 8 

CERN Geneva 40 

CSEM Zurich 2 

CT-Concept 7 

EPFL Lausanne 147 

ETH Zurich Zurich 77 

Hochschule Rapperswill Rapperswill 1 

HTA Luzern Horw 2 

HTL Brugg-Windisch Windisch 2 

id Quantique Carouge 6 

Landis + Gyr AG 1 

Leica Geosystems Heerbrugg 1 




LEM Plan-les-Ouates 3 

MEAD Microelectronics S.A. St-Sulpice 2 

MICROSWISS Rapperswil 2 

Paul-Scherrer-Institute Villigen 14 

Photonfocus Lachen 3 

Sentron AG Lausanne 7 

siemens Zug 2 

Smart Silicon Systems SA Lausanne 2 

Suter IC-Design AG Waldenburg 2 

University of Neuchatel Neuchatel 8 

University of Zurich Zurich 32 

Xemics SA - CSEM Neuchatel 33 

Taiwan 

Feng Chia University Taichung 1 

National Cheng Kung University 1 

National Tsing Hua University Hsinchu 4 

Thailand 

Microelectronic Technologies Bangkok 2 

NECTEC Bangkok 28 

Turkey 

ASELSAN Ankara 1 

Bilkent University Ankara 5 

Bogazici University Istanbul 5 

Istanbul Technical University Istanbul 12 

Kardiosis Ankara 1 

Middle East Technical Univ. Ankara 8 

Sabanci University Istanbul 6 

Tubitak Bilten Ankara 4 

United Kingdom 

Aberdeen University Aberdeen 1 

Barnard Microsystems Limited London 2 

Bournemouth University Poole 3 

Bradford University Bradford 7 

Brunel university Uxbridge 1 

Cadence Design Systems Ltd Bracknell 1 

Cambridge Consultants Ltd. Cambridge 3 

Cardiff University Cardiff 5 

CML Microcircuits Ltd. Maldon 12 

Control Technique Newtown 4 

Data Design & Developmentsq Stone 1 

Dukosi Edinburgh 1 

Edinburgh University Edinburgh 38 

Epson Cambridge research lab Cambridge 2 

ELBIT Systems Ltd. 1 

Heriot-Watt University Edinburgh 2 

Imperial College London 9



Jennic Ltd Sheffield 1 

K.J. Analogue Consulting Malmesbury 1 

King’s College London London 1 

Lancaster University Lancaster 7 

Leicester University Leicester 1 

Middlesex University London 6 

Napier University Edinburgh 4 

Nortel Harlow 1 

Plextek Ltd Essex 4 

Positek Limited Glos 1 

CCLRC - RAL Oxon 33 

Saul Research Towcester 22 

Sheffield Hallam University Sheffield 1 

Swindon Silicon Systems Ltd Swindon 3 

Tality Livingston 1 

The Queens University of Belfast Belfast 3 

The University of Hull Hull 1 

The University of Liverpool Liverpool 9 

UMIST Manchester 43 

University College London-UCL London 2 

University of Bath 3 

University of Birmingham Birmingham 6 

University of Brighton Brighton 1 

University of Cambridge Cambridge 20 

University of Dundee Dundee 1 

University of East London London 1 

University of Glasgow Glasgow 21 

University of Hertfordshire Hatfield 1 

University of Kent Canterbury 13 

University of London London 38 

University of Newcastle upon Tyne Newcastle u/o Tyne 3 

University of Nottingham Nottingham 15 

University Of Oxford Oxford 17 

University of Plymouth Plymouth 2 

University of Reading Reading 1 

University of Sheffield Sheffield 4 

University of Southampton Southampton 18 

University of Stirling Stirling 1 

University of Surrey Guildford 1 

University of the West of England Bristol 2 

University of Wales, Aberystwyth Aberystwyth 4 

University of Warwick Coventry 4 

University of Westminster London 5 

Walmsley (microelectronics) Ltd. Edinburgh 1 



USA 

Analog Phoenix 1 

austriamicrosystems USA 1 

Boston university Boston 1 

Brookhaven National Laboratory Upton, NY 1 

Columbia University Irvington, NY 15 

Discera 1 

Duke Universtity Durham 1 

Exelys Ilc Los Angeles 2 

Flextronics Sunnyvale 1 

Fox Electronics Fort Myers 4 

General Electric 2 

Goddard Space Flight Center, NASA Greenbelt 1 

Iwatsu Irving 2 

Linear Dimensions, Inc. Chicago 1 

Micrel Semiconductor San Jose 3 

Microchip Technology 1 

MIT - Lincoln Lab Cambridge 4 

MOSIS Marina del Rey, CA 18 

Nova R&D 1 

Parallax Inc. Rocklin 2 

Philips Medical Systems Andover 1 

Princeton University Princeton, NJ 4 

Rockwell Scientific Thousand Oaks, CA 13 

Stanford Linear Accelerator Meno Park 11 

Symphonix San Jose 5 

Tachyon Semiconductor Naperville, IL 2 

Tekwiss USA Inc. Costa Mesa 2 

Triad Semiconductor 1 

University of Chicago Illinois 2 

University of Colorado Boulder 1 

University of Delaware Newark 3 

University of Florida Gainesville 3 

University of Pennsylvania Philadelphia, Pa. 2 

USRA Washington 1 

Vectron International Inc. Hudson, NH 5 

Xerox El Segundo 1 

Yanntek San Jose, CA 5 


35

All information for MPW runs schedule, prices, etc. is available on-line on our WEB site 

www.europractice.imec.be 

For more information, please contact one of the EUROPRACTICE service centers. 

IMEC 

General EUROPRACTICE IC office & 

IC Manufacturing Center 

C. Das 

Kapeldreef 75 

B-3001 Leuven, Belgium 

Tel : + 32 16 281 248 

Fax : + 32 16 281 584 

mpc@imec.be 

http://www.europractice.imec.be/ 

Fraunhofer Institute for Integrated Circuits (Fraunhofer IIS) 

Integrierte Schaltungen 

IC Manufacturing Center 

W. McKinley, J. Sauerer 

Am Wolfsmantel 33 

D-91058 Erlangen, Germany 

Tel : + 49 9131 776 401 

Fax : + 49 9131 776 499 

europrac@iis.fraunhofer.de 

http://www.iis.fraunhofer.de/asic/svasic 

DESIGN: SHAKKEI.COM

Annual report 2005 - Europractice-IC

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