The Programmer's Guide to TRSDOS Version 6 - Tim Mann's Home ...
The Programmer's Guide to TRSDOS Version 6 - Tim Mann's Home ...
The Programmer's Guide to TRSDOS Version 6 - Tim Mann's Home ...
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7.6 SUPERVISOR CALL DETAILS<br />
7.6.1 @ABORT SVC-21<br />
This SVC will cause an abnormal program exit and return <strong>to</strong> DOS. Any JCL execution in<br />
progress will cease. @ABORT functions by loading the HL register pair with a value of<br />
X'FFFF' and passing control <strong>to</strong> @EXIT.<br />
Registers Affected: Not applicable.<br />
7.6.2 @ADTSK SVC-29<br />
This SVC will add an interrupt level task pointed <strong>to</strong> by your Task Control Block (TCB) <strong>to</strong><br />
the real time clock task processor Task Control Block Vec<strong>to</strong>r Table. <strong>The</strong> task slot can be<br />
0-11; however, some slots are already assigned <strong>to</strong> certain functions in the DOS. <strong>The</strong> SVC,<br />
@CKTSK, can be used <strong>to</strong> test for slot availability. Slot assignments 0-7 are low priority<br />
tasks, slots 8-10 are medium priority tasks, and slot 11 is a high priority task. Note:<br />
<strong>The</strong> TCB is a pointer <strong>to</strong> a word of RAM containing the address of the task driver entry<br />
point and not <strong>to</strong> the location of your task driver. Detailed interfacing on background<br />
tasks is in Chapter 8, the Appendix, on TASK PROCESSOR.<br />
Registers Affected: AF, HL.<br />
Entry<br />
DE Pointer <strong>to</strong> your Task Control Block (TCB).<br />
C Contains the task slot assignment number.<br />
7.6.3 @BANK SVC-102<br />
This SVC deals with memory bank use. <strong>The</strong> <strong>to</strong>p half of the first 64K block is bank 0, and<br />
the second 64K is banks 1 and 2. DOS supports a <strong>to</strong>tal of 8 memory banks of 32K each<br />
(numbered 0-7). See Chapter 8, the Appendix, on BANK SWITCHING for programming details<br />
and illustrations. Internally, the DOS makes use of three s<strong>to</strong>rage bytes: the BAR contains<br />
the bit-image of Bank Available RAM; the BUR contains the bit-image of Bank Used RAM; and<br />
LBANK$ contains the number (0-7) of the currently resident bank. <strong>The</strong>se s<strong>to</strong>rage areas are<br />
not directly accessible <strong>to</strong> the programmer but are referenced through the SVC functions.<br />
In the interfacing register pro<strong>to</strong>col identified below, register-B passes a function code.<br />
Registers Affected: AF, BC, [HL if a transfer is requested].<br />
Bank Request [optional transfer]<br />
Entry:<br />
B 0<br />
C Bank number (0-7). Optionally set bit-7 <strong>to</strong> transfer <strong>to</strong> the address specified<br />
in register pair HL.<br />
HL Optional address <strong>to</strong> transfer <strong>to</strong> in the new bank. This option is selected by<br />
setting bit-7 of register-C.<br />
Exit:<br />
B Returns a 0.<br />
C Returns the previously resident bank number (0-7). If a transfer has been<br />
specified (via bit-7 set), bit-7 will remain set.<br />
A Returns any error code if NZ condition.<br />
NZ Bank not there.<br />
Bank Release<br />
Entry:<br />
B 1; Reset bank in C.<br />
C Bank number.<br />
7-10