MPC866 Application Development System Users Manual

Freescale Semiconductor, Inc... 

User’s Manual 

MPC86XADS 

Version-A 

January 14, 2003 

Freescale Semiconductor, Inc. 

For More Information On This Product, 

Go to: www.freescale.com 

MPC86XADS 

User’s Manual 

© Motorola, Inc., 2003



Important Notice to Users 

While every effort has been made to ensure the accuracy of all information in 

this document, Motorola assumes no liability to any party for any loss or 

damage caused by errors or omissions or by statements of any kind in this 

document, its updates, supplements, or special editions, whether such errors are 

omissions or statements resulting from negligence, accident, or any other cause. 

Motorola further assumes no liability arising out of the application or use of any 

information, product, or system described herein: nor any liability for incidental 

or consequential damages arising from the use of this document. Motorola 

disclaims all warranties regarding the information contained herein, whether 

expressed, implied, or statutory, including implied warranties of 

merchantability or fitness for a particular purpose. Motorola makes no 

representation that the interconnection of products in the manner described 

herein will not infringe on existing or future patent rights, nor do the 

descriptions contained herein imply the granting or license to make, use or sell 

equipment constructed in accordance with this description. 

Trademarks 

This document includes these trademarks: 

Motorola and the Motorola logo are registered trademarks 

of Motorola, Inc. 

Windows is a registered trademark of Microsoft Corporation in the U.S. 

and other countries. 

Intel is a registered trademark of Intel Corporation. 

Motorola, Inc., is an Equal Opportunity / Affirmative Action Employer. 

For an electronic copy of this book, visit Motorola’s web site at http://e-www.motorola.com/ 

© Motorola, Inc., 2002; All Rights Reserved 


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Freescale 

MPC866ADS 

Semiconductor, 

- User’s Manual 

Inc. 

CHAPTER 1 - . . . . . . General Information .............................................................................1 

. . . . . . . . . . .1•1 . . . . Introduction .......................................................................................... 1 

. . . . . . . . . . .1•2 . . . . MPC86x Family Support ..................................................................... 1 

. . . . . . . . . . .1•3 . . . . Abbreviations’ List .............................................................................. 2 

. . . . . . . . . . .1•4 . . . . Related Documentation ........................................................................ 2 

. . . . . . . . . . .1•5 . . . . SPECIFICATIONS .............................................................................. 2 

. . . . . . . . . . .1•6 . . . . MPC86xADS Features ........................................................................ 4 

. . . . . . . . . . .1•7 . . . . MPC86xADS Goals ............................................................................. 6 

CHAPTER 2 - . . . . . . Hardware Preparation and Installation .................................................7 

. . . . . . . . . . .2•1 . . . . INTRODUCTION ............................................................................... 7 

. . . . . . . . . . .2•2 . . . . UNPACKING INSTRUCTIONS ........................................................ 7 

. . . . . . . . . . 2•3 . . . .HARDWARE PREPARATION ................................................... 7 

. . . . . . . . . . .2•3•1 . . . MPCs’ Replacing - U20 .......................................................................9 

. . . . . . . . . . 2•3•2 . . .ADI Port Address Selection........................................................9 

. . . . . . . . . . .2•3•3 . . . Clock Source Selection ........................................................................10 

. . . . . . . . . . .2•3•4 . . . VDDL Source Selection (J3) ...............................................................10 

. . . . . . . . . . .2•3•5 . . . Debug Mode Indication Source Selection ............................................11 

. . . . . . . . . . .2•3•6 . . . ATM Mode - Split, mux, single phy or multy phy & Fast-Ethernet source Control, 

Expansion connector. 11 

. . . . . . . . . . .2•3•7 . . . RS232 - 1 on SMC2 enable by operating the ATM on single phy. (J4) 12 

. . . . . . . . . . .2•4 . . . . INSTALLATION INSTRUCTIONS ................................................ 12 

. . . . . . . . . . .2•4•1 . . . Host Controlled Operation ...................................................................12 

. . . . . . . . . . .2•4•2 . . . Stand Alone Operation .........................................................................13 

. . . . . . . . . . .2•4•3 . . . Debug Port . .........................................................................................13 

. . . . . . . . . . .2•4•4 . . . +5V Power Supply Connection ............................................................14 

. . . . . . . . . . .2•4•5 . . . P21: +12V Power Supply Connection .................................................15 

. . . . . . . . . . .2•4•6 . . . ADI Installation ....................................................................................15 

. . . . . . . . . . .2•4•7 . . . Host computer to MPC86xADS Connection .......................................15 

. . . . . . . . . . .2•4•8 . . . Debug Port Connector. .........................................................................16 

. . . . . . . . . . .2•4•9 . . . Terminal to MPC86xADS RS-232 Connection ...................................16 

. . . . . . . . . . .2•4•10 . . Memory Installation .............................................................................17 

CHAPTER 3 - . . . . . . OPERATING INSTRUCTIONS .......................................................18 

. . . . . . . . . . .3•1 . . . . INTRODUCTION .............................................................................18 

. . . . . . . . . . .3•2 . . . . CONTROLS AND INDICATORS ................................................... 18 

. . . . . . . . . . .3•2•1 . . . ABORT Switch SW5 ...........................................................................18 

. . . . . . . . . . .3•2•2 . . . SOFT RESET Switch SW6 ..................................................................18 

. . . . . . . . . . .3•2•3 . . . HARD RESET - Switches SW5 & SW6 .............................................18 

. . . . . . . . . . .3•2•4 . . . SW7 - Software Options Switch ..........................................................18 

. . . . . . . . . . .3•2•5 . . . SW3 - ATM Fast-Ethernet configuration. ...........................................18 

. . . . . . . . . . .3•2•6 . . . GND Bridges ........................................................................................19 

. . . . . . . . . . .3•2•7 . . . Ethernet 10Base-T. ETH ON - LD21 .................................................19 

. . . . . . . . . . .3•2•8 . . . IRD ON - LD20 ...................................................................................19 

. . . . . . . . . . .3•2•9 . . . RS232 Port 1 ON - LD19 .....................................................................19 

. . . . . . . . . . .3•2•10 . . RS232 Port 2 ON - LD22 .....................................................................20 

. . . . . . . . . . .3•2•11 . . Ethernet RX Indicator - LD4 ................................................................20 

. . . . . . . . . . .3•2•12 . . Ethernet TX Indicator - LD5 ................................................................20 



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. . . . . . . . . . .3•2•13 . . Ethernet JABB Indicator - LD6 ...........................................................20 

. . . . . . . . . . .3•2•14 . . Ethernet CLSN Indicator LD3 .............................................................20 

. . . . . . . . . . .3•2•15 . . Ethernet PLR Indicator - LD1 ..............................................................20 

. . . . . . . . . . .3•2•16 . . Ethernet LIL Indicator - LD2 ...............................................................20 

. . . . . . . . . . .3•2•17 . . 5V Indicator - LD13 .............................................................................20 

. . . . . . . . . . .3•2•18 . . RUN Indicator - LD23 .........................................................................20 

. . . . . . . . . . .3•2•19 . . FLASH ON - LD17 ..............................................................................20 

. . . . . . . . . . .3•2•20 . . DRAM ON - LD15 ..............................................................................20 

. . . . . . . . . . .3•2•21 . . SDRAM ON - LD14 ............................................................................20 

. . . . . . . . . . .3•2•22 . . PCMCIA ON - LD17 ...........................................................................21 

. . . . . . . . . . .3•2•23 . . Fast-Ethernet Full Duplex LD9 ............................................................21 

. . . . . . . . . . .3•2•24 . . Fast-Ethernet Link + Activity LD10 ..................................................21 

. . . . . . . . . . .3•2•25 . . Fast-Ethernet Collision LED LD11 .....................................................21 

. . . . . . . . . . .3•2•26 . . Fast-Ethernet Link LED - speed LD12 ................................................21 

. . . . . . . . . . .3•2•27 . . ATM25Mhz RX-LED LD8 ..................................................................21 

. . . . . . . . . . .3•2•28 . . ATM25Mhz TX-LED LD7 ..................................................................21 

. . . . . . . . . . .3•3 . . . . MEMORY MAP ................................................................................ 21 

. . . . . . . . . . .3•4 . . . . MPC Registers’ Programming ........................................................... 24 

. . . . . . . . . . .3•4•1 . . . Memory Controller Registers Programming ........................................25 

CHAPTER 4 - . . . . . . Functional Description .......................................................................38 

. . . . . . . . . . .4•1 . . . . Reset & Reset - Configuration ........................................................... 38 

. . . . . . . . . . .4•1•1 . . . Regular Power - On Reset ....................................................................38 

. . . . . . . . . . .4•1•2 . . . Manual Soft Reset ................................................................................38 

. . . . . . . . . . .4•1•3 . . . Manual Hard Reset ...............................................................................38 

. . . . . . . . . . .4•1•4 . . . MPC Internal Sources ..........................................................................38 

. . . . . . . . . . .4•1•5 . . . Reset Configuration .............................................................................38 

. . . . . . . . . . .4•2 . . . . Local Interrupter ................................................................................ 39 

. . . . . . . . . . .4•3 . . . . Clock Generator ................................................................................. 40 

. . . . . . . . . . .4•4 . . . . Buffering ............................................................................................ 40 

. . . . . . . . . . .4•5 . . . . Chip - Select Generator ...................................................................... 41 

. . . . . . . . . . .4•6 . . . . DRAM ............................................................................................... 41 

. . . . . . . . . . .4•6•1 . . . DRAM 16 Bit Operation ......................................................................42 

. . . . . . . . . . .4•6•2 . . . DRAM Performance Figures ...............................................................42 

. . . . . . . . . . .4•6•3 . . . Refresh Control ....................................................................................43 

. . . . . . . . . . .4•6•4 . . . Variable Bus-Width Control ................................................................44 

. . . . . . . . . . .4•7 . . . . Flash Memory SIMM ........................................................................46 

. . . . . . . . . . .4•8 . . . . Synchronous Dram ............................................................................ 48 

. . . . . . . . . . .4•8•1 . . . SDRAM Programming .........................................................................51 

. . . . . . . . . . .4•8•1•1 . . SDRAM Initializing Procedure ............................................................52 

. . . . . . . . . . .4•8•2 . . . SDRAM Refresh ..................................................................................52 

. . . . . . . . . . 4•9 . . . . .Communication Ports .................................................................53 

. . . . . . . . . . .4•9•1 . . . Ethernet Port .........................................................................................53 

. . . . . . . . . . .4•9•2 . . . Infra-Red Port .......................................................................................53 

. . . . . . . . . . .4•9•2•1 . . Infra-Red Port Rate Range Selection ...................................................53 

. . . . . . . . . . .4•9•3 . . . RS232 Ports ..........................................................................................53 

. . . . . . . . . . .4•9•3•1 . . RS-232 Ports’ Signal Description ........................................................54 



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. . . . . . . . . . .4•9•4 . . . Utopia Bus and MII Operation & Interface ........................................54 

. . . . . . . . . . .4•9•5 . . . ATM25 .................................................................................................55 

. . . . . . . . . . .4•9•6 . . . ATM155 ...............................................................................................55 

. . . . . . . . . . .4•9•7 . . . Serial ATM (Over E1/T1) ....................................................................56 

. . . . . . . . . . .4•9•8 . . . Fast Ethernet. ........................................................................................56 

. . . . . . . . . . .4•10 . . . PCMCIA Port .................................................................................... 56 

. . . . . . . . . . .4•10•1 . . PCMCIA Power Control ......................................................................58 

. . . . . . . . . . .4•11 . . . Board Control & Status Register - BCSR .......................................... 58 

. . . . . . . . . . .4•11•1 . . BCSR Disable Protection Logic ...........................................................59 

. . . . . . . . . . .4•11•2 . . BCSR0 - Hard Reset Configuration Register .......................................59 

. . . . . . . . . . .4•11•3 . . BCSR1 - Board Control Register 1 ......................................................60 

. . . . . . . . . . .4•11•4 . . BCSR2 - Board Control / Status Register - 2 .......................................63 

. . . . . . . . . . .4•11•5 . . BCSR3 - Board Control / Status Register 3 .........................................65 



. . . . . . . . . . .4•12 . . . Debug Port Controller ........................................................................ 68 

. . . . . . . . . . .4•12•1 . . MPC86xADS As Debug Port Controller For Target System ..............69 

. . . . . . . . . . .4•12•1•1 . Debug Port Connection - Target System Requirements ......................70 

. . . . . . . . . . .4•12•2 . . Debug Port Control / Status Register ...................................................70 

. . . . . . . . . . .4•12•3 . . Standard MPCXXX Debug Port Connector Pin Description ..............72 

. . . . . . . . . . .4•12•3•1 . VFLS(0:1) ............................................................................................72 

. . . . . . . . . . .4•12•3•2 . HRESET* .............................................................................................72 

. . . . . . . . . . .4•12•3•3 . SRESET* .............................................................................................72 

. . . . . . . . . . .4•12•3•4 . DSDI - Debug-port Serial Data In .......................................................72 

. . . . . . . . . . .4•12•3•5 . DSCK - Debug-port Serial Clock ........................................................73 

. . . . . . . . . . .4•12•3•6 . DSDO - Debug-port Serial Data Out ...................................................73 

. . . . . . . . . . .4•13 . . . Power ................................................................................................. 73 

. . . . . . . . . . .4•13•1 . . 5V Bus ..................................................................................................75 

. . . . . . . . . . .4•13•2 . . 3.3V Bus ...............................................................................................75 

. . . . . . . . . . .4•13•3 . . 12V Bus ................................................................................................75 

CHAPTER 5 - . . . . . . Support Information ...........................................................................76 

. . . . . . . . . . .5•1 . . . . Interconnect Signals ........................................................................... 76 

. . . . . . . . . . .5•1•1 . . . P1 - 10BaseT Ethernet Port Connector ................................................76 

. . . . . . . . . . .5•1•2 . . . PA2, PB2 - RS232 Ports’ Connectors ..................................................77 

. . . . . . . . . . .5•1•3 . . . P3 - T1/E1 RJ45 Connector. ................................................................77 

. . . . . . . . . . .5•1•4 . . . P4 - ATM25 RJ45 Connector. .............................................................78 

. . . . . . . . . . .5•1•5 . . . P5 - ATM155 multymode optical connector. ......................................78 

. . . . . . . . . . .5•1•6 . . . P6 ADI - Port Connector ......................................................................78 

. . . . . . . . . . .5•1•7 . . . MPC86XADS’s P7 - Serial Ports’ Expansion Connector ....................79 

. . . . . . . . . . .5•1•8 . . . P8, P11, P14, P16, P17 and P19 Mictor, Logic Analyser connectors. .84 

. . . . . . . . . . .5•1•9 . . . P9 - External Debug Port Controller Input Interconnect. ....................89 

. . . . . . . . . . .5•1•10 . . P10 - 100BaseT Ethernet Port Connector ............................................89 

. . . . . . . . . . .5•1•11 . . P12 - 12V Power Connector ................................................................90 

. . . . . . . . . . .5•1•12 . . P13 - 5V Power Connector ..................................................................90 

. . . . . . . . . . .5•1•13 . . P13A - Power Jack connector 2.1mm. .................................................91 

. . . . . . . . . . .5•1•14 . . P15 - Mach’s In System Programming (ISP) ......................................91 



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. . . . . . . . . . .5•1•15 . . P18 - BNC connector - not populated. .................................................91 

. . . . . . . . . . .5•1•16 . . P20 - JTAG connector for Altera programing. ....................................91 

. . . . . . . . . . .5•1•17 . . Expansion Connector ADD, Data control & PCMCIA Port. ...............92 

. . . . . . . . . . .5•1•18 . . PCMCIA Port Connector .....................................................................97 

. . . . . . . . . . .5•2 . . . . MPC86xADS Part List .................................................................... 100 

APPENDIX A Schematics. 1-20. ...................................................................................... 106 

APPENDIX B Programmable Logic Equations ................................................................. 128 

. . . . . . . . . . .1•0•1 . . . U2 - Debug Port Controller ..................................................................129 

. . . . . . . . . . .1•0•2 . . . U36 - Board Control & Status Register ...............................................149 

. . . . . . . . . . .1•0•3 . . . BCSR5 & ATM & Fast-Ethernet Control Logic. ................................187 

. . . . . . . . . . .1•0•4 . . . Block called nux_862/6 ........................................................................188 

APPENDIX C ADI I/F ........................................................................................................ 195 

. . . . . . . . . . .1•1 . . . . ADI Signal description ...................................................................... 95 

APPENDIX D ADI Installation ........................................................................................... 197 



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TABLE 1-1. . . . . MPC86xADS Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 

TABLE 2-1. ADI Address Selection 9 

TABLE 2-2. . . . . ATM & Fast-Ethernet configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 

TABLE 3-1. ATM & Fast-Ethernet configuration. 19 

TABLE 3-2. . . . . Memory Map in MP86xADS New Mode, . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 

TABLE 3-3. . . . . Memory Map in Compatible Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 

TABLE 3-4. . . . . SIU REGISTERS’ PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 

TABLE 3-5. . . . . Memory Controller Initializations For 50Mhz with DRAM-EDO . . . . . . . . . 26 

TABLE 3-6. . . . . Memory Controller Initializations For 50Mhz with No DRAM-EDO . . . . . . 29 

TABLE 3-7. . . . . UPMA Initializations for 60nsec DRAMs @ 50MHz . . . . . . . . . . . . . . . . . . 31 

TABLE 3-8. . . . . UPMA Initializations for 60nsec EDO DRAMs @ 50MHz . . . . . . . . . . . . . . 32 

TABLE 3-9. . . . . Memory Controller Initializations For 20Mhz . . . . . . . . . . . . . . . . . . . . . . . . 32 

TABLE 3-10. . . . UPMA Initializations for 60nsec EDO DRAMs @ 20MHz . . . . . . . . . . . . . . 35 

TABLE 3-11. . . . UPMB Initializations for KS643232C-TC60 upto 32MHz . . . . . . . . . . . . . . 36 

TABLE 3-12. . . . UPMB Initializations for KS643232C-TC60, 32+MHz - 50MHz . . . . . . . . . 37 

TABLE 4-1. MPC86xADS Chip Selects’ Assignment 41 

TABLE 4-2. . . . . Regular DRAM Performance Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 

TABLE 4-3. . . . . EDO DRAM Performance Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 

TABLE 4-4. . . . . DRAM ADDRESS CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 

TABLE 4-5. . . . . Flash Memory Performance Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 

TABLE 4-6. . . . . SDRAM ADD pin refer to MPC8xx Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 

TABLE 4-7. . . . . SDRAM Connected to MPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 

TABLE 4-8. . . . . Estimated SDRAM Performance Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 

TABLE 4-9. . . . . SDRAM’s Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 

TABLE 4-10. . . . BCSR0 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 


TABLE 4-12. . . . PCCVCC(0:1) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 

TABLE 4-13. . . . PCCVPP(0:1) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 


TABLE 4-15. . . . Flash Presence Detect (4:1) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 

TABLE 4-16. . . . DRAM Presence Detect (2:1) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 

TABLE 4-17. . . . DRAM Presence Detect (4:3) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 


TABLE 4-19. . . . FLASH Presence Detect (7:5) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 



TABLE 4-22. . . . Debug Port Control / Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 

TABLE 4-23. . . . DSCK Frequency Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 

TABLE 4-24. . . . Off-board Application Maximum Current Consumption . . . . . . . . . . . . . . . . 74 

TABLE 5-1. P1 - Ethernet Port Interconnect Signals .................................................................... 76 

TABLE 5-2. . . . . PA2, PB2 Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 

TABLE 5-3. . . . . P3 - T1/E1 RJ45 Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 

TABLE 5-4. . . . . P4 - ATM25 RJ45 Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 

TABLE 5-5. . . . . P1 - ADI Port Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 

TABLE 5-6. . . . . MPC86XADS’s P7 - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 

TABLE 5-7. . . . . P17 Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 



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TABLE 5-8. . . . . P19 - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 

TABLE 5-9. . . . . P11 - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 

TABLE 5-10. . . . P14 - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 

TABLE 5-11. . . . P8 - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 

TABLE 5-12. . . . P16 - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 

TABLE 5-13. . . . P9 - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 

TABLE 5-14. . . . P10 - Ethernet Port Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 

TABLE 5-15. . . . P12 - Interconnect Signals 90 

TABLE 5-16. . . . P13 - Interconnect Signals 90 

TABLE 5-17. . . . . P15 - ISP Connector - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . 91 

TABLE 5-18. . . . P20 - JTAG connector for Altera programing. . . . . . . . . . . . . . . . . . . . . . . . . 91 

TABLE 5-19. . . . MPC86XADS’s P21 - Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 93 

TABLE 5-20. . . . P22 - PCMCIA Connector Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . 97 

TABLE 5-21. . . . MPC86xADS Part List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 



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FIGURE 1-1 MPC86xADS Block Diagram 6 

FIGURE 1-2 MPC86xADS Top Side Part Location diagram .....................................8 

FIGURE 1-3 MPC TOP VIEW ..................................................................................9 

FIGURE 1-4 Configuration Dip-Switch - SW1...................................................10 

FIGURE 2-1 . . . . J1 - VFLS / FRZ Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 

FIGURE 2-2 J4 - SMC2 or Multyphy ........................................................................12 

FIGURE 2-3 Host Controlled Operation Scheme .......................................................13 

FIGURE 2-4 Stand Alone Configuration ....................................................................14 

FIGURE 2-5 P13: +5V Power Connector ...................................................................14 

FIGURE 2-6 P12: +12V Power Connector .................................................................15 

FIGURE 2-7 P6 - ADI Port Connector ........................................................................15 

FIGURE 2-8 BDM Connectoe. ....................................................................................16 

FIGURE 2-9 BDM connector connected to the board ................................................16 

FIGURE 2-10 PA7, PB7 - RS-232 Serial Port Connectors ...........................................16 

FIGURE 2-11 Memory SIMM Installation ...................................................................17 

FIGURE 3-1 SW7 - Description ..................................................................................18 

FIGURE 4-1 Refresh Scheme ......................................................................................44 

FIGURE 4-2 DRAM Address Lines’ Switching Scheme ............................................46 

FIGURE 4-3 Flash Memory SIMM Architecture ........................................................47 

FIGURE 4-4 SDRAM Connection Scheme ................................................................51 

FIGURE 4-5 RS232 Serial Ports’ Connector ..........................................................54 

FIGURE 4-6 UTOPIA and MII Buses interfaces & control .......................................55 

FIGURE 4-7 PCMCIA Port Configuration .................................................................57 

FIGURE 4-8 Debug Port Controller Block Diagram ..................................................69 

FIGURE 4-9 Standard Debug Port Connector .............................................................72 

FIGURE 4-10 MPC86xADS Power Scheme ................................................................74 

APPENDIX C ADI Port Connector ...............................................................................195 

APPENDIX D Physical Location of jumper JG1 and JG2 .............................................198 

JG1 Configuration Options ....................................................................198 

ADI board for SBus ...............................................................................199 



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1•1 Introduction 

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General Information 

1 - General Information 

This document is an operation guide for the MPC86xADS board. It can contain the following parts: 

XPC855T / MPC855T, XPC857T / MPC857T, XPC8860X / MPC860X, XPC862X / MPC862X, XPC866X / 

MPC866X. It contains operational, functional and general information about the ADS. The MPC86xADS is 

meant to serve as a platform for s/w and h/w development around the MPC86X family processors. Using 

its on-board resources and its associated debugger, a developer is able to download his code, run it, set 

breakpoints, display memory and registers and connect his own proprietary h/w via the expansion connectors, 

to be incorporated to a desired system with the MPC86x processor. 

This board is compatible with the MPC8xxFADS for SW point of view. 

This board could also be used as a demonstration tool, i.e., application s/w may be burnedA into its flash 

memory and ran in exhibitions etc.‘. 

1•2 MPC86x Family Support 

The MPC86xADS supports the following MPC8xx family members: 

A. Either on or off-board. 

o XPC855T / MPC855T 


o XPC8860DE / MPC860DE 

o XPC860DP / MPC860DP 

o XPC860EN / MPC860EN 

o XPC860P / MPC860P 

o XPC860SR / MPC860SR 


o XPC862DT / MPC862DT 

o XPC862SR / MPC862SR 


o XPC859X / MPC859X 

o XPC866X / MPC866X 

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1•3 Abbreviations’ List 

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• ADS - the MPC86xADS, the subject of this document. 

• UPM - User Programmable Machine 

• GPCM - General Purpose Chip-select Machine 

• GPL - General Purpose Line (associated with the UPM) 

• I/R - Infra-Red 

• BCSR - Board Control & Status Register. 

• ZIF - Zero Input Force 

• BGA - Ball Grid Array 

• SIMM - Single In-line Memory Module 

1•4 Related Documentation 

• MPC86x User’s Manuals. 

• ADI Board Specification. 

• Motorola 10BaseT MC68160 phy. 

• LSI 10/100BaseT 80225 phy. 

• Infineon E1/T1 PEB2256 Framer. 

• NEC ATM 155Mhz uPD98404 phy 

• idt ATM 25Mhz IDT77V107 phy 

1•5 SPECIFICATIONS 

The MPC86xADS specifications are given in TABLE 1-1. 

TABLE 1-1. MPC86xADS Specifications 

CHARACTERISTICS SPECIFICATIONS 

Power requirements (no other boards attached) +5Vdc @ 1.4 A (typical), 3 A (maximum) 

+12Vdc - @1A. 

Microprocessor MPC86x running upto @ 75 MHz Bus Speed 

Addressing 

Total address range: 

Flash Memory 

Dynamic RAM optional not populated. 

Synchronous DRAM 

4 GigaBytes 

Operating temperature 0 O C - 30 O C 

Storage temperature -25 O C to 85 O C 

2 MByte, 32 bits wide expandable to 8 MBytes 

4 MByte, 32 bits wide EDO SIMM, Optional 

Support for up to 32 MByte, EDO or FPM SIMM 

8 MBytes, SDRAM. 

Relative humidity 5% to 90% (non-condensing) 

Dimensions: 

Length 

Width 

Thickness 

9.173" (233 mm) 

6.3" (160 mm) 

0.063" (1.6 mm) 

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1•6 MPC86xADS Features 

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o Compatible with the old MPC86xADS Board. 

o MPC862/866, running upto 75 MHz bus frequency, mounted on ZIF BGA socket. 

o 8 MByte, Unbuffered, Synchronous Dram On-Board. 

o 4 MByte EDO 60nsec delay DRAM SIMM. Support for 4 - 32 MByte FPM or EDO Dram 

SIMM, with Automatic Dram SIMM identification. 16 Bit Data-Bus Width Support. 

EDO DRAM will not be populated on board. it is optional. 

o 2 MByte Flash SIMM. Support for upto 8 MByte, 5V or 12V Programmable, with Automatic 

Flash SIMM identification. Can be change up to 8MByte. 

o Dual RS232 port with Low-Power Option per each port. 

o T1/E1 connected to TDMB using infineon PEB2256 framer for serial ATM or just T1/E1. 

o Fast Ethernet connected to PCMCIA port or Port-D using LSI-Logic 80225. 

o ATM Mode operate in Utopia Split or mux and also can work multy phy 

or singe phy. 

o ATM25 connected to PCMCIA Port & Port-D in split mode, or only Port-D in mux mode using 

IDT77V106. 

o ATM155 connected to PCMCIA Port & Port-D in split mode, or only Port-D in mux mode 

using NEC uPD98404 device. 

o Memory Disable Option for each local memory map slaves. 

o Board Control & Status Register - 5 BCSR, Controlling Board’s Operation. 

o Programmable Hard-Reset Configuration via BCSR. 

o 5V only PCMCIA Socket With Full Buffering, Power Control and Port Disable Option. Complies 

with PCMCIA 2.1+ Standard. 

o Module Enable Indications. 

o 10-Base-T Port On-Board, with Stand-By Mode. 

o IrDA (4MBps) Port with Stand-By Mode. 

o Dual RS232 port with Low-Power Option per each port. 

o On - Board Debug Port Controller & also ADI I/F. 

o MPC86xADS Serving as Debug Station for Target System option. 

o Optional Hard-Reset Configuration Burned in Flash A . 

o External Tools’ Identification Capability, via BCSR. 

A. Available only if supported also on the MPC86x. 

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o Expansion connectors includes all the CPM ports & bus signals in order to control external 

peripherals. 

o Soft / Hard A Reset Push - Button 

o ABORT Push - Button 

o Single B 5V Supply. 

o Reverse / Over Voltage Protection for Power Inputs. 

o 3.3V VDDL/VDDH for older version then MPC866. 1.8V VDDL & 3.3V HDDH for MPC866, 

done by jumper. 

o Power Indications for Each Power Bus. 

o External dip switches for selections the ATM & Fast Ethernet options in the MPC86x. 

A. Hard reset is applied by depressing BOTH Soft Reset & ABORT buttons. 

B. Unless a 12V supply is required for a PCMCIA card or for a 12V programmable Flash SIMM. 

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Logic Analyser 

Connectors 

Not Populated 

Fast Ethernet PORT 

RJ45 

SDRAM 

8 MBytes 

FLASH 

Upto 8MByte 

DRAM EDO 

Upto 64 Mbyte 

Control 

BCSR 

Expansion 

Connectors 

Expansion 

Connectors 

1•7 MPC86xADS Goals 

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FIGURE 1-1 MPC86xADS Block Diagram 

ADD/DATA 

Buffered 

ADD/DATA 

Fast 

Ethernet 

BCSR Control 

MII 

MPC862/866 

VDDL Power 

3.3V 1.8V 

Switch & Logic 

Data/ADD 

Reset, 

Clocks & 

Interrupts 

Debug Port 

10 Pin Connector 

Debug Port 

Controller 

(ADI I/F) 

PCMCIA 

Control & 

Buffering 

E1/T1 

Framer 

ATM25 

PHY 

ATM155 

PHY 

The MPC86xADS is meant to become a general platform for s/w and h/w development around the MPC86x 

family. Using its on-board resources and its associated debugger, the developer is able to load his code, 

run it, set breakpoints, display memory and registers and connect his own proprietary h/w via the expansion 

connectors, to be incorporated to a system with the MPC. 

This board could also be used as a demonstration tool, i.e., application s/w may be programmedA into its 

flash memory and ran in exhibitions etc. 

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Utopia 

I/O PORTS 

IO Ports 

Utopia 



Data/ADD 

IrDA 

10BaseT 

Ethernet 

ETHERNET 

10BaseT PORT 1 

RS232 

PORT1 

RS232 

PORT2 

PCMCIA 

PORT 

E1/T1 PORP 

RJ45 

ATM25M PORT 

RJ45 

ATM155M 

PORT-Optic


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Hardware Preparation and Installation 

2 - Hardware Preparation and Installation 

2•1 INTRODUCTION 

This chapter provides unpacking instructions, hardware preparation, and installation instructions for the 

MPC86xADS. 

2•2 UNPACKING INSTRUCTIONS 

NOTE 

If the shipping carton is damaged upon receipt, 

request carrier’s agent to be present during 

unpacking and inspection of equipment. 

Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save 

packing material for storing and reshipping of equipment. 

CAUTION 

AVOID TOUCHING AREAS OF INTEGRATED 

CIRCUITRY; STATIC DISCHARGE CAN 

DAMAGE CIRCUITS. 

2•3 HARDWARE PREPARATION 

To select the desired configuration and ensure proper operation of the MPC86xADS board, changes of the 

Dip-Switch settings or jumpers may be required before installation. The location of the switches, LEDs, Dip- 

Switches, jumpers and connectors is illustrated in FIGURE 1-2. The board has been factory tested and is 

shipped with Dip Switch settings as described in the following paragraphs. Parameters can be changed for 

the following conditions: 

• ADI port address 

• MPC Clock Source 

• MPC Internal Logic Supply Source 

• Debug Mode Indication Source 

• ATM Mode - Split, mux, single phy or multy phy. 

• Fast Ethenet source Port, PortD/PCMCIA-Port. 

• PCMCIA Enable. 

• MPC I/O port connected to Expansion Connector. 

• RS232 Port-(1) on SMC2 enable with conjunction with ATM single phy. 

A. Either on or off-board. 

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FIGURE 1-2 MPC86xADS Top Side Part Location diagram 

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2•3•1 MPCs’ Replacing - U20 

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Before replacing the MPC the user should turn off the power. When replacing U20 with another MPC it 

should be noticed where is the MPCs’ A1 pin. Put the new MPC in the same direction as the old one. 

MPC866 thickness is 2.5mm while the other MPC86x thickness is 1.7mm. The board has a socket with 

clamshell inorder that the socket will fit to both devices the board has been supplied with a spacer to put 

between the socket cover (shell) and the device. For MPC86x that is not MPC866 add the spacer between 

the device and the socket cover. 

2•3•2 ADI Port Address Selection 

FIGURE 1-3 MPC TOP VIEW 

The MPC86xADS can have eight possible slave addresses set for its ADI port, enabling up to eight 

MPC86xADS boards to be connected to the same ADI board in the host computer. The selection of the 

slave address is done by setting switches 1, 2 & 3 in the Dip-Switch - SW1. Switch 1 stands for the mostsignificant 

bit of the address and switch 3 stands for the least-significant bit. If the switch is in the ’ON’ state, 

it stands for logical’1’. In FIGURE 1-4 DS1 is shown to be configured to address’0’. 

FIGURE 1-4 Configuration Dip-Switch - SW1 

ADR2 

ADR1 

ADR0 

3 - 5 MHz Generator via EXTCLK 

TABLE 2-1. describes the switch settings for each slave address: 

A1 

1 

2 

3 

4 

MPC 

SW1 

TABLE 2-1. ADI Address Selection 

ADDRESS Switch 1 Switch 2 Switch 3 

0 OFF OFF OFF 

1 OFF OFF ON 

2 OFF ON OFF 

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ON 

ADR2 

ADR1 

ADR0 



32.678 KHz Crystal Resonator


2•3•3 Clock Source Selection 

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TABLE 2-1. ADI Address Selection 

ADDRESS Switch 1 Switch 2 Switch 3 

3 OFF ON ON 

4 ON OFF OFF 

5 ON OFF ON 

6 ON ON OFF 

7 ON ON ON 

Switch #4 on SW1 selects the clock source for the MPC. When it is in the’ON’ position while the ADS is 

powered-up, the on-board 32.768 KHz crystal resonator becomes the clock source and the PLL 

multiplication factor becomes 1:513. When switch #4 is in the’OFF’ position while the ADS is powered-up, 

the on-board 4MHz clock generator becomes the clock source while the PLL multiplication factor becomes 

1:5. Note: For device other then MPC866, SW3 -1 should be ’ON’ 

2•3•4 VDDL Source Selection (J3) 

This board can be use for MPC866 and its derivative and MPC862 and its derivative. For MPC866 VDDL 

should be 1.8V - J3 connect pins 1-2. For MPC862 and its derivative VDDL should be 3.3V. J3 connect 

pins 2-3. 

2•3•5 Debug Mode Indication Source Selection 

Jumper J1 selects between VFLS(0:1) signals and FRZ signal of the MPC as an indication for debug mode 

state. Since with the MPC86xs, each of these signals has alternate function, it may be necessary to switch 

between the two sources, in favor of alternate function being used. 

When a jumper is positioned between pins 1 and 2 of J1 - VFLS(0:1) are selected towards the debug-port 

controller. When a jumper is placed between positions 2 - 3 of J1(2) - FRZ signal is selected. 

FIGURE 2-1 J1 - VFLS / FRZ Selection 

J1 J1 

1 1 

VFLS(0:1) Selected FRZ Selected 

2•3•6 ATM Mode - Split, mux, single phy or multy phy & Fast-Ethernet source 

Control, Expansion connector. 

According to SW3(2,3,4) the user can select the Fast-Ethernet & ATM source and function. The table 

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bellow show the configuration options. 

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TABLE 2-2. ATM & Fast-Ethernet configuration. 

Note: Inorder to work in single phy the user should config the unused phy to any address and the wanted 

phy to different address, The ATM25 config phy address is in address 0x2000008, the ATM155 phy 

address register is in 0x2000129. Then drive the RxAdd(1)-PB17 & RxAdd(0)-PB16 and TxAdd(1)-PB21 

& TxAdd(0)-PB20 to the wanted phy address, by driving them constantly. 

2•3•7 RS232 - 1 on SMC2 enable by operating the ATM on single phy. (J4) 

Jumper J4 selects between ATM multy phy and enable RS232 port 1. Pins PB21 and PB20 have a multiple 

functions TXD and RXD for RS232-1 and ATM TXADD1 and TXADD0 on the board. the MPC allow to work 

with ATM single phy and SMC2 so the board has this ability too. By J4, if J4 connect between 1,2 it drive 

the address pins to the ATM phy’s to be 0b00011 so the user can work with single phy, he can select which 

phy by writing to the address phy register this address. If J4 connect 2,3 it allow the operation with multy 

phy, and the RS232 on SMC2 should not be enable by the appropriate BCSR register. 

Note: The ATM ADD that are used on the board are only RXADD0, RXADD1, TXADD0 and TXADD1. 


SW3 

Switch 2 Switch 3 Switch 4 PORT-D 

ON ON ON Expansion 

Connector 

ON ON OFF Expansion 

Connector 

PORT- 

PCMCIA 

Expansion 

Connector 

Not Define 

ON OFF ON ATM MUX PCMCIA 

ON OFF OFF ATM MUX MII 

OFF ON ON ATM SPLIT 

OFF ON OFF Not Define Expansion 

Connector 

OFF OFF ON Fast-Ethernet PCMCIA 

OFF OFF OFF Fast-Ethernet Expansion 

Connector 




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FIGURE 2-2 J4 - SMC2 or Multyphy. 

2•4 INSTALLATION INSTRUCTIONS 

Because the board shipped with no DRAM EDO and all the SW around are base on that there is an 

DRAM the user should change BR2, BR3, BR4 and OR4 to: BR2 & BR3 valid bit should be 0 (bit 31) 

BR4 = 0x000000C1 and OR4 should be 0xFC800a00, this configuration will map the SDRAM to ADD 

0 & 0x3000000 for 8MByte. When the MPC86xADS has been configured as desired by the user, it can 

be installed according to the required working environment as follows: 

• Host Controlled Operation 

• Debug Port. 

• Stand-Alone 

2•4•1 Host Controlled Operation 

J4 J4 

1 1 

SMC2 Selected Multyphy Selected 

In this configuration the MPC86xADS is controlled by a host computer via the ADI through the debug port. 

This configuration allows for extensive debugging using on-host debugger. 

5V Power Supply 

FIGURE 2-3 Host Controlled Operation Scheme 

37 Wire 

Host 

Computer 


P1 

P1 

ADI 

or paralel port 

Flat Cable 




2•4•2 Stand Alone Operation 

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In this mode, the ADS is not controlled by the host via the ADI/Debug port. It may connect to host via one 

of its other ports, e.g., RS232 port, I/R port, Ethernet port, etc.‘. Operating in this mode requires an application 

program to be programmed into the board‘s Flash memory (while with the host controlled operation, 

no memory is required at all). 

2•4•3 Debug Port. 

In this mode of operation the user control the board via P9 through an external tool connected to its 

computer to the parallel port. The board can work as it work in a host mode but it controlled via the MPC 

debug pins and not through the ADI connector. 

5V Power Supply 

2•4•4 +5V Power Supply Connection 

FIGURE 2-4 Stand Alone Configuration 

Host 

Computer 

The MPC86xADS requires +5 Vdc @ 3A max, power supply for operation. Connect the +5V power supply 

to connector P13 or P13A as shown below: 

FIGURE 2-5 P13: +5V Power Connector 

+5V 

GND 

GND 

P13 is a 3 terminal block power connector with power plug. The plug is designed to accept 14 to 22 AWG 

wires. It is recommended to use 14 to 18 AWG wires. To provide solid ground, two Gnd terminals are 

supplied. It is recommended to connect both Gnd wires to the common of the power supply, while VCC is 

connected with a single wire. 


1 

2 

3 

RS232 

Ethernet 



I/R


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P13A is a Connector that should be use with the power supply which supplied with the board box. 

Plug the power supply to P13A. 

NOTE 

Since hardware applications may be connected to the 

MPC86xADS via the Expansion connectors’ P7 & P21, power 

consumption should be taken into consideration when a 

power supply is connected to the MPC86xADS. In other words 

when adding a HW into the expansion connectors remember 

that the additional will not have more power consumption then 

1A 

2•4•5 P21: +12V Power Supply Connection 

The MPC86xADS requires +12 Vdc @ 1 A max, power supply for the PCMCIA channel Flash programming 

capability or for 12V programmable Flash SIMM. The MPC86xADS can work properly without the +12V 

power supply, if there is no need to program either a 12V programmable PCMCIA flash card or a 12V 

programmable Flash SIMM. 

Connect the +12V power supply to connector P12 as shown below: 

FIGURE 2-6 P12: +12V Power Connector 

+12V 

GND 

P12 is a 2 terminal block power connector with power plug. The plug is designed to accept 14 to 22 AWG 

wires. It is recommended to use 14 to 18 AWG wires. 

2•4•6 ADI Installation 

For ADI installation on various host computers, refer to APPENDIX D -. 

2•4•7 Host computer to MPC86xADS Connection 

1 

2 

The MPC86xADS ADI interface connector, P6, is a 37 pin, male, D type connector. The connection 

between the MPC86xADS and the host computer is by a 37 line flat cable, supplied with the ADI board. Or 

by BDM Connector. FIGURE 2-7 below shows the pin configuration of the ADI connector. 





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FIGURE 2-7 P6 - ADI Port Connector 

NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the MPC86xADS. 

2•4•8 Debug Port Connector. 

Gnd 20 

1 N.C 

Gnd 21 

2 D_C~ 

Gnd 22 

3 HST_ACK 

Gnd 23 

4 ADS_SRESET 

Gnd 24 

5 ADS_HRESET 

Gnd 25 

6 ADS_SEL2 

(+ 12 v) N.C. 26 

7 ADS_SEL1 

HOST_VCC 27 

8 ADS_SEL0 

HOST_VCC 28 

9 HOST_REQ 

HOST_VCC 29 

10 ADS_REQ 

ADS_ACK 

HOST_ENABLE~ 30 

11 

Gnd 31 

12 N.C. 

Gnd 32 

13 N.C. 

Gnd 33 

14 N.C. 

PD0 34 

15 N.C. 

PD2 35 

16 PD1 

PD4 36 

17 PD3 

18 PD5 

PD6 37 19 PD7 

Through this connector the user can control the board like it done from the ADI connector. Today most of 

the control SW use this connector through a command converter box that connected from the other side 

to the PC parallel port. 





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FIGURE 2-8 BDM Connectoe. 

Vfls0 

Gnd 

Gnd 

Hreset 

V3.3 

FIGURE 2-9 BDM connector connected to the board 

Computer 

2•4•9 Terminal to MPC86xADS RS-232 Connection 

A serial (RS232) terminal or any other RS232 equipment, may be connected to the RS-232 connectors 

P2A and P2B. The RS-232 connectors is a 9 pin, female, Stacked D-type connector as shown in FIGURE 

2-10. 

The connectors are arranged in a manner that allows for 1:1 connection with the serial port of an Personal 

Computer. via a flat cable. 

FIGURE 2-10 PA7, PB7 - RS-232 Serial Port Connectors 

NOTE: The RTS line (pin 7) is not connected on the MPC86xADS. 

2•4•10 Memory Installation 

1 

3 

5 

7 

9 

CD 1 

TX 2 

RX 3 

DTR 4 

GND 5 

2 Sreset 

4 Dsck 

6 Vfls1 

8 Dsdi 

10Dsdo 

paralel port 

6 DSR 

7 RTS 

8 CTS 

9 N.C. 

The MPC86xADS has two types of memory SIMM: 

• Dynamic Memory SIMM, will not populated only the socket will be soldered. 

• Flash Memory SIMM. 

To install a memory SIMM, it should be taken out of its package, put diagonally in its socket (no error can 

be made here, since the Flash socket has 80 contacts, while the DRAM socket has 72) and then twisted 

to a vertical position until the metal lock clips are locked. See FIGURE 2-11 "Memory SIMM Installation" 

below. 




Vfls0 

Gnd 

Gnd 

1 

3 

5 

Hreset 7 

V3.3 9 

MPC86xADS 

2 Sreset 

4 Dsck 

6 Vfls1 

8 Dsdi 

10Dsdo


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CAUTION 

The memory SIMMs have alignment nibble near their # 1 

pin. It is important to align the memory correctly before 

it is twisted, otherwise damage might be inflicted to both 

the memory SIMM and its socket. 

FIGURE 2-11 Memory SIMM Installation 

(1) 

Memory 

SIMM 

(2) 

Metal Lock Clip 

SIMM Socket 





3•1 INTRODUCTION 

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Inc. 

OPERATING INSTRUCTIONS 

3 - OPERATING INSTRUCTIONS 

This chapter provides necessary information to use the MPC86xADS in host-controlled and stand-alone 

configurations. This includes controls and indicators, memory map details, and software initialization of the 

board. 

3•2 CONTROLS AND INDICATORS 

The MPC86xADS has the following switches and indicators. 

3•2•1 ABORT Switch SW5 

The ABORT switch is normally used to abort program execution, this by issuing a level 0 interrupt to the 

MPC. If the ADS is in stand alone mode, it is the responsibility of the user to provide means of handling 

the interrupt, since there is no resident debugger with the MPC86xADS. The ABORT switch signal is 

debouncing, and can not be disabled by software. 

3•2•2 SOFT RESET Switch SW6 

The SOFT RESET switch SW5 performs Soft reset to the MPC internal modules, maintaining MPC’s 

configuration (clocks & chip-selects) Dram and SDram contents. The switch signal is debouncing, and it is 

not possible to disable it by software. At the end of the Soft Reset Sequence, the Soft Reset Configuration 

is sampled and becomes valid. 

3•2•3 HARD RESET - Switches SW5 & SW6 

When BOTH switches - SW5 and SW6 are depressed simultaneously, HARD reset is generated to the 

MPC. When the MPC is HARD reset, all its configuration is lost, including data stored in the DRAM or 

SDRAM and the MPC has to be re-initialized. At the end of the Hard Reset sequence, the Hard Reset 

Configuration stored in BCSR0 becomes valid. 

3•2•4 SW7 - Software Options Switch 

SW7is a 4-switches Dip-Switch. This switch is connected over EXTOLI(0:3) lines which are available at 

BCSR, S/W options may be manually selected, according to SW7 state. 

EXTOLI0 Pulled to ’1’ 




FIGURE 3-1 SW7 - Description 

3•2•5 SW3 - ATM Fast-Ethernet configuration. 

1 

2 

3 

4 

Table 3-1 desires the way of configuring the board in order to be fit to the MPC866/862 way of operation. 

As the user know the MPC86x can be configure in ATM or/and Fast ethernet (MPC866 & MPC862 has 

both ATM and Fast Ethernet) the board can be configure for many options over portD and PCMCIA Port 

like ATM Mux, ATM Split, Single phy or multy phy & Fast ethernet or connect an external HW through the 


SW7 

ON 



EXTOLI0 Driven to ’0’ 



EXTOLI3 Driven to ’0’


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Expansion Connectors. SW3 (2,3,4) select all these options. 

Note: Before changing the position of the SW3(2,3,4) the user should turn off the power. 

When the switches are in option(0) position the user can use PD & PCMCIA Ports through the Expansion 

Connectors. Option(2,3) select ATM-Mux through Port-D and PCMCIA or MII through PCMCIA Port. Option(4), 

select ATM split. options(6,7) select PortD for MII and PCMCIA for PCMCIA or Expansion Connector. 

NOTE: In case of board with PHYs ATM25 add ATM 155, for selection ATM in Single Phy or Multy Phy the 

user should configure the following Pins to outputs, drive Port-B(16,17 ATM Rx-Add) & Port-B(19,20, ATM 

TX-ADD) to the wanted address like the internal phy default address for one of the wanted phys. The other 

phy can be left for its default address. 

3•2•6 GND Bridges 

There are 3 GND bridges on the MPC86xADS. They are meant to assist general measurements and logicanalyzer 

connection. 

Warning 

When connecting to a GND bridge, use only INSULATED 

GND clips. Failure in doing so, might result in permanent 

damage to the MPC86xADS. 

3•2•7 Ethernet 10Base-T. ETH ON - LD21 

When the yellow ETH ON led is lit, it indicates that the ethernet port transceiver - the MC68160 EEST, 

is active. When it is dark, it indicates that the EEST is in power down mode, enabling the use of its associated 

SCC pins off-board via the expansion connectors. 

3•2•8 IRD ON - LD20 

When the yellow IRD ON led is lit, it indicates that the Infra-Red transceiver - the TFDS6000, is active and 

enables communication via that medium. When it is dark, the I/R transceiver is in shutdown mode, enabling 

the use of its associated SCC pins off-board via the expansion connectors. 

3•2•9 RS232 Port 1 ON - LD19 

TABLE 3-1. ATM & Fast-Ethernet configuration. 

When the yellow RS232 Port 1 ON led is lit, it designates, that the RS232 transceiver connected to PA2, 

is active and communication via that medium is allowed. When darkened, it designates that the transceiver 


SW3 

Option# Switch 2 Switch 3 Switch 4 PORT-D PORT-PCMCIA 

0 ON ON ON Expansion Connector Expansion Connector 

1 ON ON OFF Expansion Connector Not Define 

2 ON OFF ON ATM MUX PCMCIA 

3 ON OFF OFF ATM MUX Fast-Ethernet 

4 OFF ON ON ATM SPLIT 

5 OFF ON OFF Not Define Expansion Connector 

6 OFF OFF ON Fast-Ethernet PCMCIA 

7 OFF OFF OFF Fast-Ethernet Expansion Connector 




Freescale 




Inc. 


is in shutdown mode, so its associated MPC pins may be used off-board via the expansion connectors. 

3•2•10 RS232 Port 2 ON - LD22 

When the yellow RS232 Port 2 ON led is lit, it designates that the RS232 transceiver connected to PB2, 

is active and communication via that medium is allowed. When darkened, it designates, that the transceiver 

is in shutdown mode, so its associated MPC pins may be used off-board via the expansion connectors. 

3•2•11 Ethernet RX Indicator - LD4 

The green Ethernet Receive LED indicator blinks whenever the EEST is receiving data from one of the 

Ethernet port. 

3•2•12 Ethernet TX Indicator - LD5 

The green Ethernet Receive LED indicator blinks whenever the EEST is transmitting data via the Ethernet 

port. 

3•2•13 Ethernet JABB Indicator - LD6 

The red Ethernet TP Jabber LED indicator - JABB, lights whenever a jabber condition is detected on the 

TP ethernet port. 

3•2•14 Ethernet CLSN Indicator LD3 

The red Ethernet Collision LED indicator CLSN, blinks whenever a collision condition is detected on the 

ethernet port, i.e., simultaneous receive and transmit. 

3•2•15 Ethernet PLR Indicator - LD1 

The red Ethernet TP Polarity LED indicator - PLR, lights whenever the wires connected to the receiver input 

of the ethernet port are reversed. The LED is lit by the EEST, and remains on while the EEST has 

automatically corrected for the reversed wires. 

3•2•16 Ethernet LIL Indicator - LD2 

The yellow Ethernet Twisted Pair Link Integrity LED indicator - LIL, lights to indicate good link integrity on 

the TP port. The LED is off when the link integrity fails. 

3•2•17 5V Indicator - LD13 

The yellow 5V led, indicates the presence of the +5V supply at P13. 

3•2•18 RUN Indicator - LD23 

When the green RUN led - LD23 is lit, it indicates that the MPC is not in debug mode, i.e., VFLS0 & VFLS1 

== 0 (or FRZ == 0, which ever selected by J1). 

3•2•19 FLASH ON - LD17 

When the yellow FLASH ON led is lit, it indicates that the FLASH SIMM is enabled in the BCSR1 register. 

I.e., any access done to the CS0~ address space will hit the flash memory. When it is dark, the flash is 

disabled and CS0~ may be used off-board via the expansion connectors. 

3•2•20 DRAM ON - LD15 

When the yellow DRAM ON led is lit, it indicates the DRAM SIMM is enabled in BCSR1. Therefore, any 

access made to CS2~ (or CS3~) will hit on the DRAM. When it is dark, it indicates that either the DRAM is 

disabled in BCSR1, enabling the use of CS2~ and CS3~ off-board via the expansion connectors. 

3•2•21 SDRAM ON - LD14 

When the yellow SDRAM ON led is lit, it indicates the SDRAM is enabled in BCSR1. Therefore, any 

access made to CS4~ (will hit on the SDRAM. When it is dark, it indicates that either the SDRAM is 

disabled in BCSR1, enabling the use of CS4~ off-board via the expansion connectors. 





3•2•22 PCMCIA ON - LD17 

Freescale 




Inc. 


When the yellow PCMCIA ON led is lit, it indicates the following: 

1) Address & strobe buffers are driven towards the PCMCIA card 

2) Data buffers are driven to / from the PCMCIA card whenever CE1A~ or CE2A~ signals are asserted. 

3) Card status lines are driven towards the MPC from the PCMCIA card. 

When it is dark, it indicates that all the above buffers are tri-stated and the pins associated with PCMCIA 

channel A, may be used off-board via the expansion connectors. 

3•2•23 Fast-Ethernet Full Duplex LD9 

The function of this led is to indicate Full Duplex Detect. 

3•2•24 Fast-Ethernet Link + Activity LD10 

The function of this led is to indicate the occurrence of Link or Activity. 

3•2•25 Fast-Ethernet Collision LED LD11 


3•2•26 Fast-Ethernet Link LED - speed LD12 


3•2•27 ATM25Mhz RX-LED LD8 

This led indicates when it is light that there is a receive on the ATM25 twisted pair lines. 

3•2•28 ATM25Mhz TX-LED LD7 

This led indicates when it is light that there is a transmit on the ATM25 twisted pair lines. 

3•3 MEMORY MAP 

All accesses to MPC86xADS’s memory slaves are controlled by the MPC’s memory controller. Therefore, 

the memory map is re programmable to the desire of the user. After Hard Reset is performed by the debug 

station, the debugger checks for existence, size, delay and type of the EDO DRAM and FLASH memory 

SIMMs mounted on board and initializes the chip-selects accordingly. The SDRAM, DRAM and the FLASH 

memory respond to all types of memory access i.e., user / supervisory, program / data and DMA. 

In the following paragraph there is a description of memory map for 2 options: Compatible Mode and 

MPC86xADS New Mode. 

Compatible Mode is using an EDO DRAM and 8MByte SDRAM. In this Mode all the programmable 

registers are remain the same, (all the memory map is the same as the MPC8xxFADS board) except OR4 

Mask register bits, that will be changed according to SDRAM size to 0xFF80. 

MPC86xADS New Mode is where the EDO DRAM is not used. In this case the SDRAM will be mapped 

differently, see the TABLE 3-2. "Memory Map in MP86xADS New Mode," on page 22, TABLE 3-3. "Memory 

Map in Compatible Mode" on page 23. The following programmable changes should be made in order to 

work in the board in the MPC86xADS New Mode: 

• Programming BR2 Base Address bits for EDO DRAM should be not valid (L-bit should be 

cleared). 

• Programming OR4 Mask Register bits for SDRAM should be changed according to SDRAM size, 

where the 2 MS bits are not masked. For 8MByte SDRAM, OR4 Mask bits = 0xFC80 and BIH should be 0 





. 

Freescale 




Inc. 


TABLE 3-2. Memory Map in MP86xADS New Mode, 

ADDESS RANGE Memory Type Device Type 

00000000 - 007FFFFF a 

02000000 - 020FFFFF Communicatio 

n 

ports: CS5, 

ATM25, 

ATM155, T1/ 

E1 Framer, 

BCSR5,6 

02000000 - 020000FF ATM25 

02000100 - 020001FF ATM155 

02000200 - 020002FF T1/E1 Framer, 

02000300 - 020003FF Control 

register 

02100000 - 02107FFF BCSR(0:4) b 

02100000 - 02107FE3 BCSR0 

2100004 - 02107FE7 BCSR1 

2100008 - 02107FEB BCSR2 

210000C - 02107FEF BCSR3 

2100010 - 02107FF3 BCSR4 

02108000 - 021FFFFF Empty Space 

02200000 - 02207FFF MPC Internal 

MAP d 


SDRAM 8MByte 32 

02800000 - 029FFFFF Flash SIMM MCM29F020 MCM29F040 MCM29F080 

32 

02A00000 - 02BFFFFF 

SM732A1000A SM732A2000 

32 

02C00000 - 02FFFFFF 32 

03000000 - 037FFFFF SDRAM a 

03400000 - FFFFFFFF Empty Space 

a. 0 - 0x007F_FFFF, 0x0300_0000 - 0x037F_FFFF are both mapped to SDRAM (8MByte). 

b. The device appears repeatedly in multiples of its size. E.g., BCSR0 appears at memory locations 

2100000, 2100020, 2100040..., while BCSR1 appears at 2100004, 2100024, 2100044... and so on. 


Port 

Size 

(for 8MByte) 32 



32 

32 

32 

32 c 

32


. 

Freescale 




Inc. 


c. Only upper 16 bit (D0-D15) are in fact used. 

d. Refer to the relevant MPC User’s Manual for complete description of the MPC internal memory map. 

TABLE 3-3. Memory Map in Compatible Mode 

ADDESS RANGE Memory Type Device Type 

00000000 - 003FFFFF DRAM SIMM MB321Bx a 08 

a. x ∈ [B,T] 


Port 

Size 

MB322Bx a 08 MC324Cx a 00 MB328Cx a 00 32 

00400000 - 007FFFFF 32 

00800000 - 00FFFFFF 32 

01000000 - 01FFFFFF 32 

02000000 - 020FFFFF Comunication 

ports: CS5, 

ATM25, 

ATM155, T1/ 

E1 Framer, 

BCSR 5 

02000000 - 020000FF ATM25 

02000100 - 020001FF ATM155 

02000200 - 020002FF T1/E1 Framer, 

02000300 - 020003FF Control register 

02100000 - 02107FFF BCSR(0:4) b 

02100000 - 02107FE3 BCSR0 

2100004 - 02107FE7 BCSR1 

2100008 - 02107FEB BCSR2 

210000C - 02107FEF BCSR3 

2100010 - 02107FF3 BCSR4 


02200000 - 02207FFF MPC Internal 

MAP d 


02800000 - 029FFFFF Flash SIMM MCM29F020 MCM29F040 MCM29F080 

32 

02A00000 - 02BFFFFF 

SM732A1000A SM732A2000 

32 

02C00000 - 02FFFFFF 32 

03000000 - 037FFFFF SDRAM (for 

8MByte) 

03400000 - FFFFFFFF Empty Space 



32 c 

32 

32


Freescale 




Inc. 


b. The device appears repeatedly in multiples of its size. E.g., BCSR0 appears at memory locations 

2100000, 2100020, 2100040..., while BCSR1 appears at 2100004, 2100024, 2100044... and so on. 

c. Only upper 16 bit (D0-D15) are in fact used. 

d. Refer to the relevant MPC User’s Manual for complete description of the MPC internal memory map. 

3•4 MPC Registers’ Programming 

The MPC provides the following functions on the MPC86xADS: 

1) DRAM Controller 

2) SDRAM Controller 

3) Chip Select generator. 

4) UART for terminal or host computer connection. 

5) Ethernet controller. 

6) Infra-Red Port Controller 

7) General Purpose I/O signals. 

8) ATM controller. 

9) T1/E1 (TDM) controller. 

10) Fast Ethernet Controller. 

The internal registers of the MPC must be programmed after Hard reset as described in the following 

paragraphs. The addresses and programming values are in hexadecimal base. 





Freescale 




Inc. 


For better understanding the of the following initialization refer to the MPC86x User’s Manual for more 

information. 

TABLE 3-4. SIU REGISTERS’ PROGRAMMING 

Register Init Value[hex] Description 

SIUMCR 01012440 Internal arbitration, External master arbitration priority - 0, External arbitration 

priority - 0, PCMCIA channel II pins - PCMCIA, Debug Port on JTAG port pins, 

FRZ/IRQ6~ - FRZ, debug register - locked, No parity for non-CS regions, DP(0:3)/ 

IRQ(3:6)~ pins - DP(0:3), reservation disabled, SPKROUT - Tri-stated, BS_A(0:3)~ 

and WE(0:3)~ are driven just on their dedicated pins, GPL_B5~ enabled, GPL_A/ 

B(2:3)~ function as GPLs. 

SYPCR FFFFFF88 Software watchdog timer count - FFFF, Bus-monitor timing FF, Bus-monitor - 

Enabled, S/W watch-dog - Freeze, S/W watch-dog - disabled, S/W watch-dog (if 

enabled) causes NMI, S/W (if enabled) not prescaler. 

TBSCR 00C2 No interrupt level, reference match indications cleared, interrupts disabled, no 

freeze, time-base disabled. 

RTCSC 00C2 Interrupt request level - 0, 32768 Hz source, second interrupt disabled, Alarm 

interrupt disabled, Real-time clock - FREEZE, Real-time clock enabled. 

PISCR 0082 No level for interrupt request, Periodic interrupt disabled, clear status, interrupt 

disabled, FREEZE, periodic timer disabled. 

3•4•1 Memory Controller Registers Programming 

The memory controller on the MPC86xADS is initialized to 50 MHz operation. I.e., registers’ programming 

is based on 50 MHZ timing calculation except for refresh timer which is initialized to 16.67Mhz, the lowest 

frequency at which the ADS may wake up. Since the ADS may be made to wake-up at 25MHzA as well, 

the initialization are not efficient, since there are too many wait-states inserted. Therefore, additional set of 

initialization is provided to support efficient 25MHz operation. 

The reason for initializing the ADS for 50Mhz is to allow proper (although not efficient) ADS operation 

through all available ADS clock frequencies. 

A. The only parameter which is initialized to the start-up frequency, is the refresh rate, which would have been inadequate 

if initialized to 50Mhz while board is running at a lower frequency. Therefore, for best bus bandwidth availability, 

refresh rate should be adapted to the current system clock frequency. 





Freescale 




Inc. 


Warning 

Due to availability problems with few of the supported 

memory components, the below initialization were not 

tested with all parts. Therefore, the below initialization 

are liable to CHANGE, throughout the testing period. 

TABLE 3-5. Memory Controller Initialization For 50Mhz with DRAM-EDO 

Register Device Type Init Value [hex] Description 

BR0 All Flash SIMMs 

supported. 

02800001 Base at 2800000, 32 bit port size, no parity, GPCM 

OR0 MCM29F020-90 FFE00D34 2MByte block size, all types access, CS early negate, 

6 w.s., Timing relax 

MCM29F040-90 

SM732A1000A-9 

MCM29F080-90 

SM732A2000-9 

FFC00D34 4MByte block size, all types access, CS early negate, 


FF800D34 8MByte block size, all types access, CS early negate, 


MCM29F020-12 FFE00D44 2MByte block size, all types access, CS early negate, 


MCM29F040-12 

SM732A1000A-12 

MCM29F080-12 

SM732A2000-12 





BR1 BCSR 02100001 Base at 2100000, 32 bit port size, no parity, GPCM 

OR1 FFFF8110 32 KByte block size, all types access, CS early 

negate, 1 w.s. 

BR2 All Dram SIMMs 

Supported 

00000081 Base at 0, 32 bit port size, no parity, UPMA 

OR2 MCM36100/200-60/70 FFC00800 4MByte block size, all types access, initial address 

multiplexing according to AMA. 

MCM36400/800-60/70 

MT8/16D432/832X-6/7 

FF000800 16MByte block size, all types access, initial address 


BR3 MCM36200-60/70 00400081 Base at 400000, 32 bit port size, no parity, UPMA 

MCM36800-60/70 

MT16D832X-6/7 


OR3 MCM36200-60/70 FFC00800 4MByte block size, all types access, initial address 

multiplexing according to AMA 

MCM36800-60/70 

MT16D832X-6/7 







BR4 

Compatibl 

e Mode 

OR4 

Compatibl 

e Mode 

BR4 

MPC86x 

New Mode 

OR4 

MPC86x 

New Mode 

Freescale 




Inc. 


TABLE 3-5. Memory Controller Initialization For 50Mhz with DRAM-EDO 


K4S643232-TC60 030000C1 Base at 3000000, on UPM B 

FFC00A00 4 MByte block size, all types access, initial address 

multiplexing according to AMB. 

K4S643232-TC60 0x000000C1 Base at 0x0, on UPM B 

BR5 Comm peripheral 0x02000401 

OR5 Comm peripheral 0xFFF009A6 

MPTPR All Dram SIMMs 

Supported 

MAMR MB321BT08TASN60 40A21114a 60A21114 b 

C0A21114 c 

MB322BT08TASN60 20A21114 a 

30A21114 b 

60A21114 c 

MB324CT00TBSN60 40B21114a 60B21114 b 

C0B21114 c 

MB328CT00TBSN60 20B21114 a 

30B21114 b 

60B21114 c 

MBMR KS643232C-TC60 D0802114 c 

80802114 d 

a. Assuming 16.67 MHz BRGCLK. 

b. Assuming 25MHz BRGCLK 

0xFC800800 4 MByte block size, all types access, initial address 


0400 Divide by 16 (decimal) 

refresh clock divided by 40 a or 60 b or C0 c , periodic 

timer enabled, type 2 address multiplexing scheme, 1 

cycle disable timer, GPL4 disabled for data sampling 

edge flexibility, 1 loop read, 1 loop write, 4 beats 

refresh burst. 

refresh clock divided by 20 a or 30 b or 60 c , periodic 

timer 

enabled, type 2 address multiplexing scheme, 1 cycle 

disable timer, GPL4 disabled for data sampling edge 

flexibility, 1 loop read, 1 loop write, 4 beats refresh 

burst. 


timer 




burst. 


timer 




burst. 

refresh clock divided by D0 or 80, periodic timer 


disable timer, GPL4enabled, 1 loop read, 1 loop write, 

4 beats refresh burst. 





c. For 50MHz BRGCLK 

d. Assuming 32MHz BRGCLK. 

Freescale 




Inc. 






Freescale 




Inc. 


TABLE 3-6. Memory Controller Initialization For 50Mhz with No DRAM-EDO 



supported. 




MCM29F040-90 

SM732A1000A-9 

MCM29F080-90 

SM732A2000-9 







MCM29F040-12 

SM732A1000A-12 

MCM29F080-12 

SM732A2000-12 









Supported 

00000089 Invalid bank 

OR2 MCM36100/200-60/70 FFC00800 Invalid bank 

MCM36400/800-60/70 

MT8/16D432/832X-6/7 

FF000800 

BR3 MCM36200-60/70 00400089 Invalid bank 

MCM36800-60/70 

MT16D832X-6/7 

01000089 Invalid bank 

OR3 MCM36200-60/70 FFC00800 4MByte block size, all types access, initial address 


BR4 

Compatibl 

e Mode 

OR4 

Compatibl 

e Mode 

MCM36800-60/70 

MT16D832X-6/7 










Freescale 




Inc. 


TABLE 3-6. Memory Controller Initialization For 50Mhz with No DRAM-EDO 


BR4 

MPC86x 

New Mode 

OR4 

MPC86x 

New Mode 





Supported 

MAMR MB321BT08TASN60 40A21114a 60A21114 b 

C0A21114 c 

MB322BT08TASN60 20A21114a 30A21114 b 

60A21114 c 

MB324CT00TBSN60 40B21114 a 

60B21114 b 

C0B21114 c 

MB328CT00TBSN60 20B21114 a 

30B21114 b 

60B21114 c 

MBMR KS643232C-TC60 D0802114c 80802114 d 

a. Assuming 16.67 MHz BRGCLK. 

b. Assuming 25MHz BRGCLK 

c. For 50MHz BRGCLK 

d. Assuming 32MHz BRGCLK. 

0xFC800800 4 MByte block size, all types access, initial address 




timer enabled, type 2 address multiplexing scheme, 1 

cycle disable timer, GPL4 disabled for data sampling 

edge flexibility, 1 loop read, 1 loop write, 4 beats 

refresh burst. 


timer 




burst. 


timer 




burst. 


timer 




burst. 

refresh clock divided by D0 or 80, periodic timer 


disable timer, GPL4enabled, 1 loop read, 1 loop write, 






Freescale 




Inc. 


TABLE 3-7. UPMA Initializations for 60nsec DRAMs @ 50MHz 

Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception 

Offset in UPM 0 8 18 20 30 3C 

Contents 

@ Offset + 

0 8FFFEC24 8FFFEC24 8FAFCC24 8FAFCC24 C0FFCC84 33FFCC07 

1 0FFFEC04 0FFFEC04 0FAFCC04 0FAFCC04 00FFCC04 X 

2 0CFFEC04 08FFEC04 0CAFCC00 0CAFCC00 07FFCC04 X 

3 00FFEC04 00FFEC0C 11BFCC47 03AFCC4C 3FFFCC06 X 

4 00FFEC00 03FFEC00 X 0CAFCC00 FFFFCC85 

5 37FFEC47 00FFEC44 X 03AFCC4C FFFFCC05 

6 X 00FFCC08 X 0CAFCC00 X 

7 X 0CFFCC44 X 03AFCC4C X 

8 00FFEC0C 0CAFCC00 X 

9 03FFEC00 33BFCC4F X 

A 00FFEC44 X X 

B 00FFCC00 X X 

C 3FFFC847 X 

D X X 

E X X 

F X X 





Freescale 




Inc. 


TABLE 3-8. UPMA Initializations for 60nsec EDO DRAMs @ 50MHz 



Contents 

@ Offset + 

0 8FFBEC24 8FFFEC24 8FFFCC24 8FFFCC24 C0FFCC84 33FFCC07 

1 0FF3EC04 0FFBEC04 0FEFCC04 0FEFCC04 00FFCC04 X 

2 0CF3EC04 0CF3EC04 0CAFCC00 0CAFCC00 07FFCC04 X 

3 00F3EC04 00F3EC0C 11BFCC47 03AFCC4C 3FFFCC06 X 

4 00F3EC00 0CF3EC00 X 0CAFCC00 FFFFCC85 

5 37F7EC47 00F3EC4C X 03AFCC4C FFFFCC05 

6 X 0CF3EC00 X 0CAFCC00 X 

7 X 00F3EC4C X 03AFCC4C X 

8 0CF3EC00 0CAFCC00 X 

9 00F3EC44 33BFCC4F X 

A 03F3EC00 X X 

B 3FF7EC47 X X 

C X X 

D X X 

E X X 

F X X 

TABLE 3-9. Memory Controller Initializations For 20Mhz 



supported. 






Freescale 




Inc. 



2 w.s. 

MCM29F040-90 

SM732A1000A-9 

MCM29F080-90 

SM732A2000-9 


2 w.s. 

FF800920 8MByte block size, all types access, CS early negate, 



3 w.s. 

MCM29F040-12 

SM732A1000A-12 

MCM29F080-12 

SM732A2000-12 


3 w.s. 

FF800930 8MByte block size, all types access, CS early negate, 

3 w.s. 





Supported 


OR2 MB321/2BT08TASN60 FFC00800 4MByte block size, all types access, initial address 


BR3 a 

MB324/8CT00TBSN60 FF000800 16MByte block size, all types access, initial address 


MB322BT08TASN60 00400081 Base at 400000, 32 bit port size, no parity, UPMA 

MB328CT00TBSN60 01000081 Base at 1000000, 32 bit port size, no parity, UPMA 

OR3 MB322BT08TASN60 FFC00800 4MByte block size, all types access, initial address 


BR4 

Compatibl 

e Mode 

OR4 

Compatibl 

e Mode 

BR4 

MPC86x 

New Mode 

OR4 

MPC86x 

New Mode 



MB328CT00TBSN60 FF000800 16MByte block size, all types access, initial address 







0xFC800A00 4 MByte block size, all types access, initial address 






Freescale 




Inc. 






Supported 


MAMR MB321BT08TASN60 60A21114 refresh clock divided by 60, periodic timer enabled, 

type 2 address multiplexing scheme, 1 cycle disable 

timer, GPL4 disabled for data sampling edge flexibility, 

1 loop read, 1 loop write, 4 beats refresh burst. 

MB322BT08TASN60 30A21114 refresh clock divided by 30, periodic timer 




burst. 

MB324CT00TBSN60 60B21114 refresh clock divided by 60, periodic timer 




burst. 

MB328CT00TBSN60 30B21114 refresh clock divided by 30, periodic timer 




burst. 

MBMR KS643232C-TC60 42802114 b 

a. BR3 is not initialized for MB321xx or MB324xx EDO DRAM SIMMs. 

b. Assuming 16.67MHz BRGCLK 

refresh clock divided by 42, periodic timer enabled, 

type 0 address multiplexing scheme, 1 cycle 

disable timer, GPL4 enabled, 1 loop read, 1 loop write, 






Freescale 




Inc. 


TABLE 3-10. UPMA Initializations for 60nsec EDO DRAMs @ 20MHz 



Contents 

@ Offset + 

0 8FFFCC04 8FFFCC04 8FEFCC00 8FEFCC00 80FFCC84 33FFCC07 

1 08FFCC00 08FFCC08 39BFCC47 09AFCC48 17FFCC04 X 

2 33FFCC47 08FFCC08 X 09AFCC48 FFFFCC86 X 

3 X 08FFCC08 X 09AFCC48 FFFFCC05 X 

4 X 08FFCC00 X 39BFCC47 X 

5 X 3FFFCC47 X X X 

6 X X X X X 

7 X X X X X 

8 X X X 

9 X X X 

A X X X 

B X X X 

C X X 

D X X 

E X X 

F X X 





Freescale 




Inc. 


TABLE 3-11. UPMB Initialization for KS643232C-TC60 upto 32MHz 


Offset In UPM 0 8 18 20 30 3C 

Contents 

@ Offset + 

0 0126CC04 0026FC04 0E26BC04 0E26BC00 1FF5FC84 7FFFFC07 

1 0FB98C00 10ADFC00 01B93C00 10AD7C00 FFFFFC04 X 

2 1FF74C45 F0AFFC00 1FF77C45 F0AFFC00 FFFFFC84 X 

3 X F1AFFC00 X F0AFFC00 FFFFFC05 X 

4 X EFBBBC00 X E1BBBC04 X 

5 1FE77C34 a 

a. MRS initialization. Uses Free space. 

1FF77C45 X 1FF77C45 X 

6 EFAABC34 X X X X 

7 1FA57C35 X X X X 

8 X X X 

9 X X X 

A X X X 

B X X X 

C X X 

D X X 

E X X 

F X X 





Freescale 




Inc. 


TABLE 3-12. UPMB Initialization for KS643232C-TC60, 32+MHz - 50MHz 


Offset In UPM 0 8 18 20 30 3C 

Contents 

@ Offset + 

0 1F07FC04 1F07FC04 1F27FC04 1F07FC04 1FF5FC84 7FFFFC07 

1 EEAEFC04 EEAEFC04 EEAEBC00 EEAEBC00 FFFFFC04 X 

2 11ADFC04 10ADFC04 01B93C04 10AD7C00 FFFFFC04 X 

3 EFBBBC00 F0AFFC00 1FF77C47 F0AFFC00 FFFFFC04 X 

4 1FF77C47 F0AFFC00 X F0AFFC00 FFFFFC84 

5 1FF77C34 a 

a. MRS initialization, Uses free space. 

F1AFFC00 X E1BBBC04 FFFFFC07 

6 EFEABC34 EFBBBC00 X 1FF77C47 X 

7 1FB57C35 1FF77C47 X X X 

8 X X X 

9 X X X 

A X X X 

B X X X 

C X X 

D X X 

E X X 

F X X 





Freescale 




Inc. 

Functional Description 

4 - Functional Description 

In this chapter the various modules combining the MPC86xADS are described to their design details. 

4•1 Reset & Reset - Configuration 

There are several reset sources on the ADS: 

1) Regular Power On Reset 

2) Manual Soft-Reset 

3) Manual Hard-Reset 

4) MPC Internal Sources. (See the appropriate Spec or U/M) 

4•1•1 Regular Power - On Reset 

The regular power on reset operates, using a device - the DALAS DS1818. The reference voltage of this 

device is the MAIN VDDH bus of the MPC while the reset line asserted, is the HRESET* line. 

When HRESET~ is asserted to the MPC, Hard-Reset configuration is made available to the MPC, via 

BCSR0. See 4•1•5•2 "Hard Reset Configuration" on page 39 and TABLE 4-10. "BCSR0 Description" on 

page 59. 

4•1•2 Manual Soft Reset 

To support application development not around the debug port and resident debuggers, a soft reset pushbutton 

is provided. (SW6) Depressing that button, asserts the SRESET* pin of the MPC, generating a 

SOFT RESET sequence. 

When the SRESET~ line is asserted to the MPC, the Soft-Reset configuration is made available to the 

MPC, by the debug-port controller. See 4•1•5•3 "Soft Reset Configuration" on page 39. 

4•1•3 Manual Hard Reset 

To support application development not around the debug port, a Hard-Reset push-button is provided A . 

When the Soft Reset push-button (SW6) is depressed in conjunction with the ABORT push-button (SW5), 

the HRESET* line is asserted, generating a HARD RESET sequence. The button sharing is for economy 

and board space saving and does not effect in any way, functionality. 

4•1•4 MPC Internal Sources 

Since the HRESET* and SRESET* lines of the MPC are open-drain and the on-board reset logic drives 

these lines with open-drain gates, the correct operation of the internal reset sources of the MPC is facilitated. 

As a rule, an internal reset source asserts HRESET* and / or SRESET* for a minimum time of 512 

system clocks. It is beyond the scope of this document to describe these sources, however Debug-Port 

Soft / Hard Resets which are part of the development system B , are regarded as such. 

4•1•5 Reset Configuration 

During reset the MPC device samples the state of some external pins to determine its operation modes 

and pin configuration. There are 3 kinds of reset levels to the MPC each level having its own configuration 

sampled: 

1) Power - On Reset configuration 

2) Hard Reset configuration 

3) Soft Reset Configuration. 

A. It is not a dedicated button. 

B. And therefore mentioned. 





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Inc. 


4•1•5•1 Power - On Reset Configuration 

Just before PORESET* is negated by the external logic, the power-on reset configuration which include 

the MODCK(1:2) pins is sampled. These pins determine the clock operation mode of the MPC. Two clock 

modes are supported on the MPC86xADS: 

1) 1:5 PLL operation via on-board clock generator. 

In this mode MODCK(1:2) are driven with’11’ during A power on reset. 

2) 1:513 PLL operation via on-board clock generator. 

In this mode MODCK(1:2) are driven with’00’. during power-on reset. 

4•1•5•2 Hard Reset Configuration 

During HARD reset sequence, when RSTCONF* pin is asserted, the MPC data bus state is sampled to 

acquire the MPC’s hard reset configuration. The reset configuration word is driven by BCSR0 register, 

defaults of which are set during power-on reset. The BCSR0 drives half of the configuration word, i.e., data 

bits D(0:15) in which the reserved bits are designated RSRVxx. If the hard-reset configuration is to be 

changed B , BCSR0 may be written with new values, which become valid after HARD reset is applied to the 

MPC. 

On the ADS, the RSTCONF* line is always driven during HARD reset, i.e., no use is possible with the 

MPC’s internal HARD reset configuration defaults. 

The system parameters to which BCSR0 defaults during power-on reset and are driven at hard-reset, are 

listed below: 

1) Arbitration: internal arbitration is selected. 

2) Interrupt Prefix: The internal default is interrupt prefix at 0xFFF00000. It is overridden to provide 

interrupt prefix at address 0, which is located within the DRAM. 

3) Boot Disable: Boot is enabled. 

4) Boot Port Size: 32 bit boot port size is selected. 

5) Initial Internal Space Base: Immediately after HARD reset, the internal space is located at 

$FF000000. 

6) Debug pins configuration: PCMCIA port BC pins become PCMCIA port B pins. 

7) Debug port pins configuration. Debug port pins are on the JTAG port. 

8) External Bus Division Factor: 1:1 internal to external clocks’ frequencies ratio is selected. 

4•1•5•3 Soft Reset Configuration 

The rising edge of SRESET* is used to configure the development port. Before the negation of SRESET*, 

DSCK D is sampled to determine for debug-mode enable / disable. After SRESET* is negated, if debug 

mode was enabled, DSCK is sampled again for debug-mode entry / non-entry. 

DSDI is used to determine the debug port clock mode and is sampled after the negation of SRESET*. 

The Soft Reset configuration is provided by the debug-port controller via the ADI I/F. Option is given to 

enter debug mode directly or only after exception. 

4•2 Local Interrupter 

The only external interrupt which is applied to the MPC via its interrupt controller is the ABORT (NMI), 

A. The MODCK lines are in fact driven longer - by HRESET~ line. 

B. With respect the ADS’s power-on defaults. 

C. Where they exist. 

D. DSCK is configured at hard-reset to reside on the JTAG port. 





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Inc. 


which is generated by a push-button. When this button is depressed, the NMI input to the MPC is asserted. 

The purpose of this type of interrupt, is to support the use of resident debuggers if any is made available 

to the ADS. All other interrupts to the MPC, are generated internally by the MPC’s peripherals and by the 

debug port. 

To support external (off-board) generation of an NMI, the IRQ0* line which is routed as an NMI input, is 

driven by an open-drain gate. This allows for external h/w to also drive this line. If an external h/w indeed 

does so, it is compulsory that IRQ0* is driven by an open-drain (or open-collector) gate. 

4•3 Clock Generator 

There are 2 ways to clock the MPC on the MPC86xADS when using other device then MPC866: 

1) 3 - 5MHz Clock generator U29 connected to CLK4IN input. 1:5 PLL mode. (SW1 / 4 OFF) 

2) 32.768 KHz crystal resonator Y2 via EXTAL-XTAL pair of the MPC, 1:513 initial PLL multiplication 

factor. (SW1 / 4 ON) 

The selection between the above modes is done using Dip-switch (SW1 / 4) with dual functionality: it is 

responsible to the combination driven to the MODCK lines during power-on reset and to the connection of 

the appropriate capacitor between MPC’s XFC and VDDSYN lines to match the PLL’s multiplication factor. 

When 1:5 mode is selected, a capacitor of 5.6nF is connected, while when 1:513 mode is selected a 0.56µF 

capacitor is connected parallel to it via a digital switch (U52). The capacitors’ values are calculated to 

support a wider range of multiplication factors as possible. 

When mode (2) above is selected, the output of the clock generator is gated from EXTCLK input and driven 

to’0’ constantly so that a jitter-free system clock is generated. 

On-board logic is clocked by the 20Mhz Clock Oscylator. This clock generator is used, so that on-board 

logic is always clocked, even when the MPC is removed from its socket. 

For MPC866 device there is SW3 / 1 this switch is selecting the digital switch U52 to connect XFC to GND 

or to let it get one of the above capacitors for the PLL. If SW3 / 1 is ON it select MPC other then MPC866 

if it is OFF it select MPC866. 

4•4 Buffering 

As the ADS meant to serve also as a hardware development platform, it is necessary to buffer the MPC 

from the local bus, so the MPC’s capacitive drive capability is not wasted internally and remains available 

for user’s off-board applications via the expansion connectors. 

Buffers are provided for address and strobe lines while transceivers are provided for data. Since the capacitive 

load over dram’s address lines mightA exceed 200 pF, the dram address lines are separately buffered. 

Use is done with 74LCX buffers which are 3.3V operated and are 5V tolerant. This type of buffers 

reduces noise on board due to reduced transitions’ amplitude. 

To further reduce noise and reflections, series resistors are placed over dram’s address and strobe lines. 

The data transceivers open only if there is an access to a validB C board address or during Hard - Reset 

configurationD . That way data conflicts are avoided in case an off-board memory is read, provided that it 

is not mapped to an address valid on board. It is the users’ responsibility to avoid such errors. 

A. Depended on dram SIMM’s internal structure. 

B. An address which covered in a Chip-Select region. 

C. Except for SDRAM, which is Unbuffered. 

D. To allow a configuration word stored in Flash memory become active. 





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Inc. 

4•5 Chip - Select Generator 


The memory controller of the MPC is used as a chip-select generator to access on-board A memories, 

saving board’s area reducing cost, power consumption and increasing flexibility. To enhance off-board application 

development, memory modules (including the BCSRx) may be disabled via BCSR1 B in favor of 

an external memory connected via the expansion connectors. That way, a CS line may be used off-board 

via the expansion connectors, while its associated local memory is disabled. 

When a CS region is disabled via BCSR1, the local data transceivers do not open during access to that 

region, avoiding possible C contention over data lines. 

The MPC’s chip-selects assignment to the various memories / registers on the ADS are as shown in 

TABLE 4-1. "MPC86xADS Chip Selects’ Assignment" below: 

4•6 DRAM 

The DRAM EDO is not supplied with the board. the user can put its own DRAM EDO on U38 DRAM 

SIMM.The MPC86xADS is able to operate with 4 MBytes of 60nsec delay EDO Dram SIMM. Support is 

given to any 5V powered FPM / EDO Dram SIMM configured as 1M X32 upto 2 X 4M X 32, with 60 nsec 

or 70nsec delay. 

All dram configurations are supported via the Board Control & Status Register (BCSR), i.e., DRAM size 

(4M to 32M) and delay (60 / 70 nsec) are read from BCSR2 and the associated registers (including the 

UPM) are programmed accordingly. 

Dram timing control is performed by UPMA of the MPC via CS2 (and CS3 for a dual-bank SIMM) region(s), 

i.e., RAS and CAS signals’ generation, during normalD access as well as during refresh cycles and the necessary 

address multiplexingE are performed using UPMA. CS2* and CS3* signals are buffered from the 

DRAM and each is split to 2 to overcome the capacitive load over the Dram SIMM RAS lines. 

The DRAM module may enabled / disabled at any time by writing the DRAMEN~ bit in BCSR1. See TABLE 

A. Phriphrials And off-board. See further. 

B. After the BCSR is removed from the local memory map, there is no way to access it but to re-apply power to the 

ADS. 

C. During read cycles. 

TABLE 4-1. MPC86xADS Chip Selects’ Assignment 

Chip Select: Assignment 

CS0* Flash Memory 

CS1* BCSR 

CS2* DRAM Bank 1 

CS3* DRAM Bank 2 a 

CS4* SDRAM 

CS5* Communication Peripherals 

CS(6-7)* Unused, user available 

a. If exists. 

D. Normal i.e.: Single Read, Single Write, Burst Read & Burst Write. 

E. Taking into account support for narrower bus widths. 





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Inc. 


4-11. "BCSR1 Description" on page 60. 

Note: The DRAM is not populated on the board the user can populate is own DRAM in order to expand its 

memory or to run old SW which run on the old MPC8xxFADS. 

4•6•1 DRAM 16 Bit Operation 

To enhance evaluation capabilities, support is given to Dram with 16-bit and 32-bit data bus width. That 

way users can tailor dram configuration, to get best fit to their application requirements. When the DRAM 

is in 16 bit mode, half of it can not be used, i.e., the memory portion that is connected to data lines D(16:31). 

To configure the DRAM for 16 bit data bus width operation, the following steps should be taken: 

1) Set the Dram_Half_Word bit in BCSR1 to Half-Word. See TABLE 4-11. "BCSR1 Description" on 

page 60 

2) The Port Size bits of BR2~ (and of BR3~ for a 2-bank DRAM simm) should be set to 16 bits. 

3) The AM bits in OR2 register should be set to 1/2 of the nominal single-bank DRAM simm volume 

or to 1/4 of the nominal dual-bank DRAM simm volume. 

If a Dual-Bank DRAM simm is being used: 

4) The Base-Address bits in BR3 register should be set to DRAM_BASE + 1/4 Nominal_Volume, 

that is, if a contiguous block of DRAM is desired. 

5) The AM bits of OR3 register, should be set to 1/4 Nominal_Volume. 

If the above is executed out of running code, than this code should not reside on the DRAM while executing, 

otherwise, erratic behavior is likely to be demonstrated, resulting in a system crash. 

4•6•2 DRAM Performance Figures 

The projected performance figures for the dram are shown in TABLE 4-2. "Regular DRAM Performance 





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Inc. 


Figures" on page 43 and in TABLE 4-3. "EDO DRAM Performance Figures" on page 43. 

4•6•3 Refresh Control 

TABLE 4-2. Regular DRAM Performance Figures 

Number of System Clock Cycles 

System Clock Frequency [MHz] 50 25 

DRAM Delay [nsec] 60 70 60 70 

Single Read 6 6 3 4 

Single Write 4 4 3 3 

Burst Read 6,2,3,2 6,3,2,3 3,2,2,2 4,2,2,2 

Burst Write 4,2,2,2 4,2,2,2 3,1,2,2 3,2,2,2 

Refresh 21a b 

a. Four-beat refresh burst. 

b. Not including arbitration overhead. 

The refresh to the dram is a CAS before RAS refresh, which is controlled by UPMA as well. The refresh 

logic is clocked by the MPC’s BRG clock which is not influenced by the MPC’s low-power divider. 


a b 

25 

a b 

13 

TABLE 4-3. EDO DRAM Performance Figures 



a b 

13 

DRAM Delay [nsec] 60 70 60 70 

Single Read 6 6 3 4 

Single Write 4 4 2 3 

Burst Read 6,2,2,2 6,3,2,2 3,1,1,1 4,1,2,2 

Burst Write 4,2,2,2 4,2,2,2 2,1,1,1 3,2,2,2 

a b 

Refresh 21 

a. Four-beat refresh burst. 

b. Not including arbitration overhead. 

25 

a b 

13 

a b 



13 

a b


BRG Clock 

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Inc. 


FIGURE 4-1 Refresh Scheme 

PTP PTA UPM 

As seen in FIGURE 4-1 "Refresh Scheme" above, the BRG clock is twice divided: once by the PTP (Periodic 

Timer Prescaler) and again by another prescaler - the PTA, dedicated for each UPM. If there are 

more than one dram banks, than refresh cycles are performed for consecutive banks, therefore, refresh 

should be made faster. The formula for calculation of the PTA is given below: 

PTA = 

Where: 

• PTA - Periodic Timer A filed in MAMR. The value of the 2’nd divider. 

• Refresh_Period is the time (usually in msec) required to refresh a dram bank 

• Number_Of_Beats_Per_Refresh_Cycle: using the UPM looping capability, it is possible to 

perform more than one refresh cycle per refresh burst (in fact upto 16). 

• Number_Of_Rows_To_Refresh: the number of rows in a dram bank 

• T_BRG: the cycle time of the BRG clock 

• MPTPR: the value of the periodic timer prescaler (2 to 64) 

• Number_Of_Banks: number of dram banks to refresh. 

If we take for example a MCM36200 SIMM which has the following data: 

• Refresh_Period == 16 msec 

• Number_Of_Beats_Per_Refresh_Cycle: on the ADS it is 4. 

• Number_Of_Rows_To_Refresh == 1024 

• T_BRG == 20 nsec (system clock @ 50 Mhz) 

• MPTPR arbitrarily chosen to be 16 

• Number_Of_Banks == 2 for that SIMM 

If we assign the figures to the PTA formula we get the value of PTA should be 97 decimal or 61 hex. 

4•6•4 Variable Bus-Width Control 

DRAM BANKS 

Refresh_Period X Number_Of_Beats_Per_Refresh_Cycle 

Number_Of_Rows_To_Refresh X T_BRG X MPTPR X Number_Of_Banks 

Since a port’s width determines its address lines’ connection scheme, i.e., the number of address lines 

required for byte-selection varies (1 for 16-bit port and 2 for 32-bit port) according to the port’s width, it is 

necessary to change address connections to a memory port if its width is to be changed. E.g.: if a certain 

memory is initially configured as a 32-bit port, the list significant address line which is connected to that 

memory’s A0 line should be the MPC’s A29. Now, if that port is to be reconfigured as a 16-bit port, the LS 

address line becomes A30. 

If a linear A address scheme is to be maintained, all address lines connected to that memory are to be 

shifted one bit, this obviously involves extensive multiplexing (passive or active). If linear addressing 





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Inc. 


scheme is not a must, than only minimal multiplexing is required to support variable port width. 

In TABLE 4-4. "DRAM ADDRESS CONNECTIONS" below, the ADS’s dram address connection scheme 

is presented: 

TABLE 4-4. DRAM ADDRESS CONNECTIONS 

As can seen from the table above, most of the address lines remain fixed while only 2 lines (the shaded 

cells) need switching. The switching scheme is shown in FIGURE 4-2 "DRAM Address Lines’ Switching 

Scheme" on page 46. The switches on that figure are implemented by active multiplexers controlled by the 

BCSR1/Dram_Half_Word* bit. 

A. Consequent addresses lead to adjacent memory cells 

Width 32 - Bit 16 - Bit 

Depth Depth 

Dram ADD 4 M 1 M 4 M 1 M 

A0 BA29 BA29 BA29 BA29 

A1 BA28 BA28 BA28 BA28 

A2 BA27 BA27 BA27 BA27 

A3 BA26 BA26 BA26 BA26 

A4 BA25 BA25 BA25 BA25 

A5 BA24 BA24 BA24 BA24 

A6 BA23 BA23 BA23 BA23 

A7 BA22 BA22 BA22 BA22 

A8 BA21 BA21 BA21 BA21 

A9 BA20 BA20 BA20 BA30 

A10 BA19 BA30 





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Inc. 


FIGURE 4-2 DRAM Address Lines’ Switching Scheme 

BA(21:29) 

BA20 

BA30 

BA19 

BA30 

4•7 Flash Memory SIMM 

The MPC86xADS is provided with 2Mbyte of 90 nsec flash memory SIMM - the MCM29020 by Motorola. 

Support is given also to 4MBytes MCM29F040, 8 MBytes MCM29F080, 4 MBytes SM73218 and to 8 

MBytes SM73228 by Smart Technology. The Motorola SIMMs are internally composed of 1, 2 or 4 banks 

of 4 Am29F040 compatible devices, while the Smart SIMMs are arranged as 1 or 2 banks of four 28F008 

devices by Intel. The flash SIMM resides on an 80 pin SIMM socket. 

To minimize use of MPC’s chip-select lines, only one chip-select line (CS0~) is used to select the flash as 

a whole, while distributing chip-select lines among the internal banks is done via on-board programmable 

logic, according to the Presence-Detect lines of the Flash SIMM inserted to the ADS. 


A(0:8) 

A9 

A10 

DRAM 




CS0~ 

ADS’s 

Logic 

Freescale 




Inc. 


FIGURE 4-3 Flash Memory SIMM Architecture 

Flash Presence-Detect Lines 

ADD 

F_CS1~ 

F_CS2~ 

F_CS3~ 

F_CS4~ 

DATA 

M29F040 or M29F040 or M29F040 or M29F040 or 

1M X 8 1M X8 1M X 8 1M X 8 

M29F040 or M29F040 or M29F040 or M29F040 or 

1M X 8 1M X 8 1M X 8 1M X 8 

M29F040 M29F040 M29F040 M29F040 

M29F040 M29F040 M29F040 M29F040 

MCM29F020 MCM29F040 MCM29F080 

SM73218 SM73228 

The access time of the Flash memory provided with the ADS is 90 nsec, however, 120 nsec devices may 

be used as well. Reading the delay section of the Flash SIMM Presence-Detect lines, the debugger establishes 

(via OR0) the correct number of wait-states (considering 50MHz system clock frequency). 

The Motorola SIMMs are built of AMD’s Am29F0X0 devices which are 5V programmable, i.e., there is no 

need for external programming voltage and the flash may be written almostA as a regular memory. 

The SMART parts however, require 12V ± 0.5% programming voltage to be applied for programming. If 

on-boards programming of such device is required, a 12V supply needs to be connected to the ADS (P12). 

Otherwise, for normalB Flash operation, 12V supply is not required. 

The control over the flash is done using the GPCM and a dedicated CS0~ region, controlling the whole 

bank. During hard - reset initializations, the debugger reads the Flash Presence-Detect lines via BCSR2 

and decides how to program BR0 & OR0 registers, within which the size and the delay of the region are 

determined. 

The performance of the flash memory is shown in TABLE 4-5. "Flash Memory Performance Figures" below 

: 

TABLE 4-5. Flash Memory Performance Figures 



Flash Delay [nsec] 90 120 90 120 

Read / Write a Access [Clocks] 8 10 4 5 

A. A manufacturer specific dedicated programming algorithm should be implemented during flash programming. 

B. I.e., Read-Only. 





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Inc. 


a. The figures in the table refer to the actual write access. The write operation continues internally 

and the device has to be polled for operation completion. 

The Flash module may disabled / enabled at any time by writing’1’ /’0’ the FlashEn~ bit in BCSR1. 

4•8 Synchronous Dram 

To enhance performance, especially in higher operation frequencies - 8 MBytes of SDRAM is provided on 

board. The SDRAM is unbuffered from the MPC bus and is configured as 4 X 512K X 32. Use is done with 

MT48LC2M32B2 chips by Micron or compatibles. 

To enhance performance, the SDRAM is unbuffered from the MPC, saving the delay associated with 

address and data buffers. Since only 1 memory chip is involved, it does not adversely effect overall system 

performance. The SDRAM does not reside on a SIMM but is soldered directly to the ADS pcb. The SDRAM 

may be enabled / disabled at any time by writing 1 / 0 to the SDRAMEN bit in BCSR1. See TABLE 4-11. 

"BCSR1 Description" on page 60. 

The SDRAM’s timing is controlled by UPMB via its assigned CS (See TABLE 4-1. "MPC86xADS Chip 

Selects’ Assignment" on page 41) line. Unlike a regular dram the synchronous dram has a CS input in 

addition to the RAS and CAS signals. 

The sdram connection scheme is shown in FIGURE 4-4 "SDRAM Connection Scheme" on page 50. 

The SDRAM’s performance figures, are shown in TABLE 4-8. "Estimated SDRAM Performance Figures": 

This SDRAM has 11 ROW and 8 Column. The suggested interface between an MPC8xx and an 

SDRAM is illustrated in Figure bellow is clear that this is a glue less interface. For a 32 bit bus, one 

32 bit SDRAM devices is connected.The control is driven by the UPMB on the MPC8xx, so the CS on the 

SDRAM is interfaced to CS4 on the MPC8xx. Any other chip select line excluding CS0 would do.The DQM 

signals of the used SDRAM devices select byte lanes and are connected to the appropriate Byte 

Strobe (BS0:3)signals on the MPC8xx. A10 SD is connected to GPL0,since this has the functionality 

to either drive an address on the line, or a defined level. This is required as A10 SD acts as both an 

address line and a control line. RAS and CAS are generated by GPL1 and GPL2 respectively. The 

WE is generated by GPL3. CLK is driven by the MPC8xx’s CLKOUT signal which is a reference point with 

respect to the MPC8xx’s Memory Controller. As the SDRAM used in the example has 2048 rows and 256 

columns, we have to use 11 row address lines and 8 column address lines.The BS line are connected 

to line A10, A9 MPC and are used as high order address bit. Please remember that the MPC8xx 

address lines have a different numbering scheme than the SDRAM address lines when reading the address 

line mapping for 32 bit in the Table below. 

TABLE 4-6. SDRAM ADD pin refer to MPC8xx Pins 

MPC8xx SDRAM 

A9, A10 BS1, BS0 

A11:A21 11 ROW 

A22:A29 8 Column 

Via the UPM Register AMx =0b000, the address bits A11:21 MPC are mapped to lines A19:29 MPC 

as row addresses. As we start with line A21 MPC to connect to A8 SD, A20 MPC to A9 SD we need 





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Inc. 


to provide the left over row address A10 SD not by using line A19 MPC (which would show A10 

MPC as multiplexed row address), but by using GPL0 as described above. In the UPM Register 

MxMR, we program GPL0 to show A10 MPC to complete row addressing. 

As in this case there are 4 banks in the SDRAM device, Sometimes, a single 32 bit SDRAM bank 

is not enough memory for an application. Connecting multiple 32 bit SDRAM based banks to the 

MPC8xx is fairly straightforward. Extending the interface described above is easy. 

Above, the most significant row address bit is connected to BS SD.A10 MPC is used due to the 

address size of 

19 bits (8/11 address multiplex!) covered by the example SDRAM device. For an SDRAM device with two 

BS lines,BS0 SD and BS1 SD, we simply use the next address bit,e.g.,A10, A9 MPC, with more 

significance to keep the memory mapping linear. In essence, we use address lines for the binary 

encoding of the bank 

selection. 

MPC output 

ADD 

TABLE 4-7. SDRAM Connected to MPC 

SDRAM ADD 

MPC Internal 

Column ADD 

A29 A0 A29 A21 

A28 A1 A28 A20 

A27 A2 A27 A19 

A26 A3 A26 A18 

A25 A4 A25 A17 

A24 A5 A24 A16 

A23 A6 A23 A15 

A22 A7 A22 A14 

A21 A8 A13 

A20 A9 A12 

GPL0 A10 (AP) A11 

A10 Note1 NC(A11) 

A10 / A9 

Note1 

BS0 A10 

A9 / A8 Note 1 BS1 A9 

MPC Internal 

Row ADD 

Note1 Incase of the user wonts to change the SDRAM to a larger one 16M A11 of the SDRAM is connected 

to A10, this connection is already exist on the board layout, the user has to connect BS0, BS1 to MPC add 





Freescale 




Inc. 


A9 & A8 this will be done by moving a resistors on board called RJ1 and RJ2 from pins 1, 2 to 2, 3. 

CS4 

GPL1 

GPL2 

TABLE 4-8. Estimated SDRAM Performance Figures 

GPL3 

GPL0 

A(9,10) 

A(20:29) 

SDRAMEN 

SYSCLK 

BS0_B 

BS1_B 

BS2_B 

BS3_B 

D(0:31) 

4•8•1 SDRAM Programming 


System Clock Frequency [MHz] 50 25 a 

Single Read 5 3 

Single Write 3+1 b 

2 + 1 b 

Burst Read 5,1,1,1 3,1,1,1 

Burst Write 3,1,1,1 + 1 b 2,1,1,1 + 1 b 

Refresh 21 c 

a. In fact upto 32MHz. 

b. One additional cycle for RAS precharge 

c. 4-beat Refresh Burst, not including arbitration overhead. 

(A11) 

FIGURE 4-4 SDRAM Connection Scheme 

CS 

RAS 

CAS 

W 

A10 

BS(1:0) 

A(9:0) 

CKE 

CLK 

DQM3 

DQM2 

DQM1 

DQM0 DQ(31:0) 

After power-up, the sdram needs to be initialized by means of programming, to establish its mode of oper- 


13 b 




Freescale 




Inc. 


ation. The Sdram is programmed by issuing a Mode Register Set command. During that command, data 

is passed to the Mode Register through the Sdram’s address lines. This command is fully supported by the 

UPM by means of a dedicated Memory Address Register and the UPM command run option. 

Mode Register programming values are shown in TABLE 4-9. "SDRAM’s Mode Register Programming" 

below: In order to operate the SDRAM in higher speed then 50Mhz the user should read the application 

note in "http://e-www.motorola.com/brdata/PDFDB/docs/AN2066.pdf" 

and also use the MPC860COD09 MPC860 UPM Programming Tool - UPM860 

and MPC860COD10 UPM860 Manual for MPC860 UPM Programming Tool on web page 

http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp?code=MPC860&nodeId=01M98657 

TABLE 4-9. SDRAM’s Mode Register Programming 

Value @ Frequency 

SDRAM Option 50MHz 25MHz 

Burst Length 4 4 

Burst Type Sequential Sequential 

CAS Latency 2 1 

Write Burst Length Burst Burst 

4•8•1•1 SDRAM Initializing Procedure 

After Power-up the SDRAM needs to be initialized in a certain manner, described below: 

1) UPMB should be programmed with values described in TABLE 3-11. "UPMB Initialization for 

KS643232C-TC60 upto 32MHz" on page 36 or in TABLE 3-12. "UPMB Initialization for 

KS643232C-TC60, 32+MHz - 50MHz" on page 37. 

2) Memory controller’s MPTPR, MBMR, OR4 and BR4 registers should be programmed according 

to TABLE 3-9. "Memory Controller Initializations For 20Mhz" on page 32 or TABLE 3-5. "Memory 

Controller Initialization For 50Mhz with DRAM-EDO" on page 26. 

3) MAR should be set with proper value (0x48 for upto 32MHz or 0x88 for 32 - 50 MHz) 

4) MCR should be written with 0x80808105 to run the MRS command programmed in locations 5 

- 8 of UPMB. 

5) MBMR’s TLFB field should be changed to 8, to constitute 8-beat refresh Bursts. 

6) MCR should be written with 0x80808130 to run the refresh sequence (8 refresh cycles are performed 

now) 

7) MBMR’s TLFB field should be restored to 4, to provide 4-beat refresh Bursts for normal operation. 

The SDRAM is initialized and ready for operation. 

4•8•2 SDRAM Refresh 

The SDRAM is refreshed using its auto-refresh mode. I.e., using UMPB’s periodic timer, a burst of four 

auto-refresh commands is issued to the SDRAM every 62.4 µsec, so that all 2048 SDRAM rows are refreshed 

within specified 32.8 msec. 





4•9 Communication Ports 

Freescale 




Inc. 


Since the ADS board is meant to serve all the MPC86x family, it contains all the modules that are possible 

to be configured on the MPC86x. The various communication ports are as below: 

• SCC1 10BaseT Ethernet. 

• SCC3 IRD 

• SMC1, SMC2 RS232. 

• TDMB Serial ATM on E1/T1 

• FETHC - Fast Ethernet Controller. On PCMCIA Port or Port - D 

• ATM mux/Split, Mux On Port - D or Split on both PCMCIA and Port - D MultyPhy or SinglePhy 

4•9•1 Ethernet Port 

An Ethernet port with T.P. (10-Base-T) I/F is provided on the MPC86xADS. The comm. port over which this 

port resides, is determined according to the MPC typeA . Use is done with the MC68160 EEST 10-base-T 

transceiver, used also with the MPC86xADS. 

To allow alternative use of the Ethernet’s SCC pins, they appear at the expansion connectors. Ports expansion 

connector (P7) of the this board, while the Ethernet transceiver may be Disabled / Enabled at any 

time by writing’1’ /’0’ to the EthEn~ bit in BCSR1. 

4•9•2 Infra-Red Port 

An infra-Red communication port is provided with the ADS - the Temic’s TFDS 6000 integrated transceiver, 

which incorporates both the receiver and transmitter optical devices with the translating logic and supports 

Fast IrDA (upto 4 Mbps). The comm. port over which this port resides, is determined according to the MPC 

typeA . 

To allow alternative use of the I/Or’s SCC or its pins, the infra-red transceiver may be disabled / enabled 

at any time, by writing ’1’ /’0’ to the IrdEn~ bit in BCSR1, while all pins appear expansion connector, P7 of 

this board. 

4•9•2•1 Infra-Red Port Rate Range Selection 

The TFDS6000 has 2 bit-rate ranges: 

1) 9600 Bps to 1.2 MBps 

2) 1.2 MBps to 4 MBps. 

Selection between the 2 ranges is determined by the state of the transceiver’s TX input on the falling edge 

of IrdEn~. 

When TX input is LOW at least 200 nsec before the falling edge of IrdEn~, then, the LOWER range is selected. 

If TX is HIGH for that period of time, then, the HIGHER range is selected. 

4•9•3 RS232 Ports 

To assist user’s applications and to provided convenient communication channels with both a terminal and 

a host computer, two identical RS232 ports are provided on the ADS. The MPC’s communication ports to 

which these RS232 ports is routed, is established according to the type of MPC. Use is done with 

MAX3241ECAI transceivers which generates RS232 levels internally using a single 3.3V supply and are 

equipped with OE and shutdown mode. When the RS232EN1 or RS232EN2 bits in BCSR1 are asserted 

(low), the associated transceiver is enabled. When negated, the associated transceiver enters standby 

mode, in which the receiver outputs are tri-stated, enabling use of the associated port’s pins, off-board via 

A. I.e., routing is done on the daughter board. 





Freescale 




Inc. 


the expansion connectors. The SMC2 are conflict with the ATM address pins. In order to work with SMC2 

the user should work in ATM single phy, look J4 description. 

Use is done with 9 pins, female D-Type stacked connector, configured to be directly (via a flat cable) connected 

to a standard IBM-PC like RS232 connector. 

FIGURE 4-5 RS232 Serial Ports’ Connector 

DCD 

TX 

TX 

4•9•3•1 RS-232 Ports’ Signal Description 

In the list below, the direction’,’I/O’ are relative to the ADS board. (I.e.’I’ means input to the ADS) 

• CD (O) - Data Carrier Detect. This line is always asserted by the ADS. 

• TX (O) - Transmit Data. 

• RX (I) - Receive Data. 

• DTR (I) - Data Terminal Ready. This signal may be used by the software on the ADS to detect if 

a terminal is connected to the ADS board. 

• DSR (O) - Data Set Ready. This line is always asserted by the ADS. 

• RTS (I) - Request To Send. This line is not connected in the ADS. 

• CTS (O) - Clear To Send. This line is always asserted by the ADS. 

4•9•4 Utopia Bus and MII Operation & Interface 

The MPC862DB supports multy phy, single phy, muxed and split Utopia bus operation. The muxing logic 

is shown in FIGURE 4-6 "UTOPIA and MII Buses interfaces & control" on page 54 and is realized by using 

a series of logic switches on the data lines as appropriate. In the split bus configuration the transmit and 

receive data signals are separated. In this configuration the MPC86xADS limits the operation of several 

other port functions including disabling of the MII, 100BaseT Ethernet interface. In the muxed bus configuration 

the MPC86xADS multiplexes (“mux”s) the transmit and receive data, soc and clock utopia signals. 

This configuration allows the MPC86xADS to provide the operation of other port functions such as 

100BaseT Ethernet (MII). The board also allows the MPC862/6 to be exercised as both a Utopia level 2 

“master” and as a Utopia level 2 “slave” device. In master mode the MPC862/6 Utopia interface is software 

programmable to use either the bus muxing (combined TX and RX bus) or the split bus configurations (separate 

TX and RX bus). The HW on the board can select the mode of operation by set of switches, 

SW2(2,3,4) select the ATM FastEthernet mode of operation.The ATM25 interface and the ATM155 interface 

can be used as slave devices. The ATM on the MPC should be configured to output the Utopia clock. 

NOTE: 

DTR 

GND 

1 

2 

3 

4 

5 

6 DSR 

7 RTS 

8 CTS 

9 N.C. 

In the split bus configuration (master or slave modes) 

the 100BaseT Ethernet interface is necessarily disabled. 

The MPC862/6 provides simultaneous control and support of multiple physical interfaces connected to the 

Utopia bus. The Utopia bus addressing allows up to 31 physical devices to be connected. In this board 

there is use of only one ATM25 and one ATM155. only 4 of 10 ATM ADDRESS pin is used on the Board 

2 for receive an 2 for transmit. PB16 for RXADD0, PB17 for RXADD1, PB20 for TXADD0 and PB21 for 





Freescale 




Inc. 


TXADD1. 

Note in case of using ATM, RS232-2 can not be use. (marked as RS2 on the board silk) 

NOTE: 

The device interrupts are ANDed together to provide a single interrupt to the MPC86x. 

The Fast Ethernet will be able to connect to PCMCIA port or to Port D. It will be according to a control logic. 

The figure below shows all the connections to Port-D and PCMCIA port with the control logic that selects 

each mode of operation. 

Set of 

Jumpers 

4•9•5 ATM25 

FIGURE 4-6 UTOPIA and MII Buses interfaces & control 

Control 

Logic 

ATM 25M PHY is connected to Utopia bus. Supports MUX mode through port-D for transmit and receive 

utopia signals or in split modetransmit signals through Port-D and receive utopia signals through PCMCIA 

port. Implementation is done using IDT IDT77107 device. The ATM25 memory mapped to ADD 

0x2000000. 

4•9•6 ATM155 

Utopia 

ATM 

PHYs 

Switch Control 

Port-D Select function signals 

TX signals 

RX signals 

Bus 

Switch 

Expanion 

Connector 

Fast Ethernet 

MII BUS 

Expansion 

Connector 

PCMCIA Select function signals 

Port-D 

MPC 

PCMCIA 

Port 

ATM 155 PHY is connected to Utopia bus. Supports MUX mode through port-D for transmit and receive 

utopia signals or in split modetransmit signals through Port-D and receive utopia signals through PCMCIA 

port. I. Implementation is done using NEC uPD98404 device. 

Note: in order to operate the NEC-uPD98404 correctly the SW should init the ATM on the MPC devise and 

also init the PIO and then reset the ATM PHY by driving to address 0x2000300 the value 0x08 (reset the 

uPD98404). The ATM155 is mapped to 0x2000100. 




Mux 4 to 1 Bus switch Mux 4 to 1 Bus switch 

Logic 

MPC


4•9•7 Serial ATM (Over E1/T1) 

Freescale 




Inc. 


The MPC862/6 has the capability to perform ATM TC layer. The ATM layer is a serial ATM output connected 

to TDMB. Implementation is done using Infineon PEB2256 E1/T1 PHY device. The MPC862/6 drive it 

through TDMB. The PEB2256 is mapped to ADD 0x2000200. 2.048M osc supplied in the board box for E1. 

4•9•8 Fast Ethernet. 

The MPC8626ADS provides a 100BaseT Ethernet interface connected to the MPC862/6 via an MII inteface. 

The MPC862 provides simultaneous operation of both fast ethernet and the Utopia bus. 

The board provides the necessary hardware interfaces and bussing logic to support this simultaneous 

feature. 

The phy address is 0b01111. 

Note: inorder to configure the board for the desire configuration ATM, Fast-Ethernet use TABLE 2-2. "ATM 

& Fast-Ethernet configuration." on page 11 table. 

4•10 PCMCIA Port 

To enhance PCMCIA i/f development, a dedicated PCMCIA port is provided on the ADS. Support is given 

to 5V only PC-Cards, PCMCIA standard 2.1+ compliant. All the necessary control signals are generated 

by the MPC itself. To protect MPC signals from external hazards, and to provide sufficient drive capability, 

a set of buffers and latches is provided over PC-Card’s address, data & strobe lines. 

To conform with the design spirit of the ADS, i.e., making as much as possible MPC resources available 

for external application development, input buffers are provided for input control signals, controlled by the 

PCC_EN~ bit in BCSR1, so the PCMCIA port may be Disabled / Enabled at any time, by writing ’1’ / ’0’ to 

that bit. When the PCMCIA channel is disabled, its associated pins are available for off-board use via the 

expansion connectors. 

A loudspeaker is provided on board and connected to SPKROUT line of the MPC. The speaker is buffered 

from the MPC and low-pass filtered. When the PCC_EN~ bit in BCSR1 is negated (high) the speaker buffer 

is tri-stated so the SPKROUT signal of the MPC may be used for alternate function. 

Since it is not desirableA to apply control signals to unpowered PC-Card, the strobe / data signal buffers / 

transceivers are tri-stated and may be driven only when the PC-Card is powered. 

The block diagram of the PCMCIA port is shown in FIGURE 4-7 "PCMCIA Port Configuration" on page 56. 

A. This since the PC-Card might have protection diodes on its inputs, which will force down input signals regardless 

of their driven level. 





MPC8XX 

On Daughter - Board 

Freescale 




Inc. 

1 

1 

26 

3 

1 

1 

2 

4 

1 

2 

8 

8 

1 

1 

1 

1 


FIGURE 4-7 PCMCIA Port Configuration 

1 

D[8:15] 

D[0:7] 

From BCSR 

R/W 

CE1_A(B) 

CE2_A(B) 

WE/PGM 

OE 

IORD,IOWR 

RESET_A(B) 

POE_A(B) 

A[6:31] 

REG 

ALE_A(B) 

SPKROUT 

From BCSR 

WAIT_A(B), IOIS16_A(B) 

RDY/BSY_A(B), BVD(1:2)_A(B) 

VDD 

PCMCIA POWER CONTROL 

PCMCIA_EN 

buffer 

with OE 

Transparent latch 

with OE 

CD(1:2)_A(B),VS(1:2)_A(B) 

Power Logic 

LTC1315 

or equiv. 

Data_A[15:8] 

Data_A[7:0] 

WE/PGM 

Address_A[25:0] 


LPF 

OE 

VDD 



5V 

12V 

OE 

PCCVCC 

PCCVPP 

CE1 

CE2 

OE 

1 

1 

1 

8 

8 

1 

1 

1 

1 

IORD,IOWR 2 

VDD 

RESET 

VDD 

PCMCIA SOCKET 

1 

26 

REG 1 

2 

35 

4


4•10•1 PCMCIA Power Control 

Freescale 




Inc. 


To support hot-insertion A the socket’s power is controlled via a dedicated PCMCIA power controller the 

LTC1315 made by LINEAR TECHNOLOGY. This device, controlled by BCSR1, switches 12V VPP for card 

programming and controls gates of external MOSFET transistors, through which the PC Card VCC is 

switched. 

When a card is inserted while the channel is enabled via BCSR1, i.e., both of the CD(1:2)* (Card Detect) 

lines are asserted (low), the status of the voltage select lines VS(1:2)* should be read to determine the PC 

Card’s operation voltage level according to which, PCCVCC(0:1) bits in BCSR1 should be set, to drive the 

correct VCC (5V) to the PC-Card. 

When a card is being removed from the socket while the channel is enabled via BCSR1, the negation of 

CD1~ and CD2~ may be sensed by the MPC and power supply to the card may be cut. 

WARNNING 

Any application S/W handling the PCMCIA channel must 

check the Voltage-Sense lines before Power is applied 

to the PC-Card. Otherwise, if 5V power is applied to a 

3.3V-Only card, permanent damage will be inflicted to 

the PC-Card. 

4•11 Board Control & Status Register - BCSR 

Most of the hardware options on the MPC86xADS are controlled or monitored by the BCSR, which is a 32B bit wide read / write register file. The BCSR is accessed via the MPC’s CS1 region and in fact includes 5 

registers: BCSR0 to BCSR4. Since the minimum block size for a CS region is 32KBytes, BCSR0 - BCSR4 

are multiply duplicated within that region. See also TABLE 3-3. "Memory Map in Compatible Mode" on 

page 23. 

The following functions are controlled / monitored by the BCSR: 

1) MPC’s Hard Reset Configuration. 

2) Flash Module Enable / Disable 

3) Dram Module Enable / Disable 

4) Dram port width - 32 bit / 16 bit. 

5) SDRAM Module Enable / Disable. 

6) Ethernet port Enable / Disable. 

7) Infra-Red port Enable / Disable. 

8) RS232 port 1 Enable / Disable. 

9) RS232 port 2 Enable / Disable. 

10) BCSR Enable / Disable. 

11) Hard Reset Configuration Source - BCSR0 / FlashC Memory 

12) PCMCIA control which include: 

• Channel Enable / Disable. 

A. I.e., card insertion when the ADS is powered 

B. In fact only the upper 16 bits - D(0:15) are used, but the BCSR is mapped as a 32 bit wide register and should be 

accessed as such. 

C. Provided that support is provided also within the MPC. 





Freescale 




Inc. 


• PC Card VCC appliance. 

• PC Card VPP appliance. 

13) Ethernet Port Control. 

14) Dram Type / Size and Delay Identification. 

15) Flash Size / Delay Identification. 

16) External (off-board) tools identification or S/W option selection switch - SW7status. 

17) Daughter Board ID. 

18) Board Revision code 

19) Reset E1/T1 device 

20) Reset ATM155. 

21) Reset ATM25. 

22) Reset Fast Ethernet PHY. 

4•11•1 BCSR Disable Protection Logic 

The BCSR itself may be disabled in favor of off-board logic. To avoid accidental disable of the BCSR, an 

event from which only power re-appliance recovers, protection logic is provided: 

The BCSR_EN~ bit resides on BCSR1. This bit wakes-up active (low) during power-up and may not be 

changed A unless BCSR_EN_PROTECT~ bit in BCSR3 is written with ’1’ previously. 

After the BCSR_EN_PROTECT~ is written with ’1’ to unprotect the BCSR_EN~ bit there is only one shot 

at disabling the BCSR, since, immediately after any write to BCSR1, BCSR_EN_PROTECT~ is re-activated 

and BCSR_EN~ is re-protected and the disabling procedure has to be repeated if desired. 

4•11•2 BCSR0 - Hard Reset Configuration Register 

BCSR0 is located at offset 0 on BCSR space. It may be read or written at any time B . BCSR0 gets its 

defaults upon MAIN C Power-On reset. During Hard-Reset data contained in BCSR0 is driven on the data 

bus to provide the Hard-Reset configuration for the MPC, this, if the Flash_Configuration_Enable~ bit in 

BCSR1 is not active. BCSR0 may be written at any time to change the Hard-Reset configuration of the 

MPC. The new values become valid when the next Hard-Reset is issued to the MPC regardless of the 

Hard-Reset source. The description of BCSR0 bits is shown in TABLE 4-10. "BCSR0 Description" on page 

A. It may be written but will not be influenced. 

B. Provided that BCSR is not disabled. 

C. I.e., when VDDH to the MPC is powered. 





59. 

Freescale 




Inc. 


TABLE 4-10. BCSR0 Description 

BIT MNEMONIC FUNCTION 

0 ERB External Arbitration. When ’0’ during Hard-Reset, Arbitration is performed 

internally. When ’1’ during Hard-Reset, Arbitration is performed externally. 

1 IP Interrupt Prefix. When ’0’ during Hard-Reset, Interrupt prefix set to 

0xFFF00000, if ’1’ Interrupt Prefix set to 0. 

2 Reserved Implemented a 

3 BDIS Boot Disable. When ’0’ during Hard-Reset, CS0~ region is enabled for boot. 

When ’1’, CS0~ region is disabled for boot. 

4 - 5 BPS(0:1) Boot Port Size. Determines the port size for CS0~ at boot. ’00’ - 32 bit, ’01’ - 

8 bit, ’10’ - 16 bit, ’11’ - reserved. 

6 Reserved Implemented a 

7 - 8 ISB(0:1) Initial Space Base. Value during Hard-Reset determines the initial base 

address of the internal MPC memory map. When ’00’ - initial space at 0, 

when ’01’ - initial space at 0x00F00000, when ’10’ - initial space at 

0xFF000000, when ’11’ - initial space at 0xFFF00000. 

9 - 10 DBGC(0:1) Debug Pins Configuration. Value during Hard-Reset determines the function 

of the PCMCIA channel II pins. When ’00’ - these pins function as PCMCIA 

channel II pins, when ’01’ - they serve as Watch-Points,’10’ - Reserved, 

when ’11’ - they become show-cycle attribute pins, e.g., VFLS, VF... 

11-12 DBPC(0:1) Debug Port Pins Configuration. Value during Hard-Reset determines the 

location of the debug port pins. When ’00’ - debug port pins are on the JTAG 

port, when ’01’ - debug port non-existent, ’10’ - Reserved, when ’11’ debug 

port is on PCMCIA channel II pins. 

13 - 14 EBDF(0:1) b 

External Bus Division Factor. Value during Hard Reset determines the factor 

upon which the CLKOUT of the MPC external bus, is divided with respect to 

its internal MPC clock. When ’00’ - CLKOUT is GCLK2 divided by 1, when 

’01’, CLKOUT is GCLK2 divided by 2. 

4•11•3 BCSR1 - Board Control Register 1 

The BCSR1 serves as a control register on the ADS. It is accessed at offset 4 from BCSR base address. 

It may be read or written at any time A . BCSR1 gets its defaults upon Power-On reset. . BCSR1 fields are 

described in TABLE 4-11. "BCSR1 Description" on page 60. 

PON 

DEF. 

a. May be read and written as any other fields and are presented at their associated data pins during Hard-Reset. 

b. Applicable for MPC’s revision A or above. Otherwise have no influence. 


ATT 

0 R,W 

0 R,W 

0 R,W 

0 R,W 

’00’ R,W 

0 R,W 

’10’ R,W 

’11’ R,W 

’00’ R,W 

’00’ R,W 

15 Reserved Implemented a . ’0’ R,W 

16 - 31 Reserved Un-Implemented - - 

A. Provided that BCSR is not disabled. 




Freescale 




Inc. 


TABLE 4-11. BCSR1 Description a 

BIT MNEMONIC Function 

0 FLASH_EN Flash Enable. When this bit is active (low), the Flash memory module is 

enabled on the local memory map. When in-active, the Flash memory is 

removed from the local memory map and CS0~, to which the Flash memory 

is connected may be used off-board via the expansion connectors. 

1 DRAM_EN Dram Enable. When this bit is active (low), the DRAM module is enabled 

on the local memory map. When in-active, the DRAM is removed from the 

local memory map and CS2~ and CS3~ b , to which the DRAM is connected 

may be used off-board via the expansion connectors. 

2 ETHEN Ethernet Port Enable. When asserted (low) the EEST connected to SCC1 

is enabled. When negated (high) that EEST is in standby mode, while all its 

system i/f signals are tri-stated. 

3 IRDEN Infra-Red Port Enable. When asserted (low), the Infra-Red transceiver, 

connected to SCC2 is enabled. When negated, the Infra-Red transceiver is 

put in shutdown mode. And SCC2 pins are available for off-board use via 

the expansion connectors. 

4 FLASH_CFG_EN Flash Configuration Enable. When this bit is asserted (low): (A) - the 

Hard-Reset configuration held in BCSR0 is NOT driven on the data bus 

during Hard-Reset and (B) - configuration data held at the 1’st word of the 

flash memory is driven to the data bus during Hard-Reset. c 

5 CNT_REG_EN_P 

ROTECT 

Control Register Enable Protect. When this bit is active (low) the 

BCSR_EN bit in that register can not be written. When in-active, BCSR_EN 

may be written to remove the BCSR from the memory map. After any write 

to BCSR1 this bit becomes active again. This bit is a read-only d bit on that 

register. 

6 BCSR_EN BCSR Enable. When this bit is active (low) the Board Control & Status 

Register is enabled on the local memory map. When inactive, the BCSR 

may not be read or written and its associated CS1~ is available for off-board 

use via the expansion connectors. 

This bit may be written with ’1’ only if CNT_REG_EN_PROTECT bit is 

negated (1). 

When the BCSR is disabled it still continues to configure the board 

according the last data held in it even during Hard-Reset. 

7 RS232EN_1 RS232 port 1 Enable. When asserted (low) the RS232 transceiver for port 

1, is enabled. When negated, the RS232 transceiver for port 1, is in standby 

mode and the relevant MPC communication port pins are available for offboard 


8 PCCEN PC Card Enable. When asserted (low), the on-board PCMCIA channel is 

enabled, i.e., address and strobe buffers are enabled to / from the card. 

When negated, all buffers to / from the PCMCIA channel are disabled 

allowing off-board use of its associated lines. 




PON 

DEF 

ATT. 

0 R,W 

0 R,W 

1 R,W 

1 R,W 

1 R,W 

0 R 

0 R,W 

1 R,W 

1 R,W


Freescale 




Inc. 


TABLE 4-11. BCSR1 Description a 


9 PCCVCC0 Pc Card VCC Select 0. These signal in conjunction with PCCVCC1 

determine the voltage applied to the PCMCIA card’s VCC. Possible values 

are 0 / 3.3 / 5 V. For the encoding of these lines and their associated 

voltages see TABLE 4-12. "PCCVCC(0:1) Encoding" on page 62. 

10 - 11 PCCVPP(0:1) PC Card VPP. These signals determine the voltage applied to the PCMCIA 

card’s VPP. Possible values are 0 / 5 / 12 V. For the encoding of these lines 

and their associated voltages see TABLE 4-13. "PCCVPP(0:1) 

Encoding" on page 62. 

12 Dram_Half_Word Dram Half Word. When this bit is active (low) and the steps listed in 4•6•1 

"DRAM 16 Bit Operation" on page 42, are taken, the DRAM becomes 

16 bit wide. When inactive the DRAM is 32 bit wide. 

13 RS232EN_2 RS232 port 2 Enable. When asserted (low) the RS232 transceiver for port 

2, is enabled. When negated, the RS232 transceiver for port 2, is in standby 

mode and the relevant MPC communication port pins are available for offboard 


14 SDRAMEN SDRAM Enable. When this bit is active (high), the SDRAM module is 

enabled on the local memory map. When in-active, the DRAM is place in 

low-power mode, in fact removed from the local memory map, allowing its 

associated CS line, to be used off-board via the expansion connectors. 

15 PCCVCC1 Pc Card VCC Select 1. These signal in conjunction with PCCVCC0 

determine the voltage applied to the PCMCIA card’s VCC. Possible values 

are 0 / 3.3 / 5 V. For the encoding of these lines and their associated 

voltages see TABLE 4-12. "PCCVCC(0:1) Encoding" on page 62. 


0 R,W 

’11’ R,W 

1 R,W 

1 R,W 

1 R,W 

0 R,W 

16 - 31 Reserved Un-implemented - - 

a. Shaded areas are additions with respect to the MPC86xADS. 

b. In case a Single Bank DRAM SIMM is used CS3~ is free as well. 

c. Provided that this option is supported by the MPC by driving address lines low and asserting 

CS0~ during Hard-Reset. 

d. It is written in BCSR3. 



PON 

DEF 

ATT.


Freescale 




Inc. 


TABLE 4-12. PCCVCC(0:1) Encoding 

PCCVCC(0:1) 

PC-Card VCC 

[V] 

00 0 

01 5 

10 3.3 

11 0 

TABLE 4-13. PCCVPP(0:1) Encoding 

PCCVPP(0:1) 

PC Card VPP 

[V] 

00 0 

01 5 

10 12 a 

11 Hi-Z 

a. Provided that a 12V 

power supply is applied. 

4•11•4 BCSR2 - Board Control / Status Register - 2 

BCSR2 is a status register which is accessed at offset 8 from the BCSR base address. Its a read only 

register which may be read at any time A . BCSR2’s various fields are described in TABLE 4-14. "BCSR2 

Description" on page 63. 






Freescale 




Inc. 




0 - 3 FLASH_PD(4:1) Flash Presence Detect(4:1). These lines are connected to the Flash SIMM 

presence detect lines which encode the type of Flash SIMM mounted on the 

Flash SIMM socket. There are additional 3 presence detect lines which 

encode the SIMM’s delay but appear in BCSR3. For the encoding of 

FLASH_PD(4:1) see TABLE 4-15. "Flash Presence Detect (4:1) 



PON 

DEF 

- R 

4 Reserved Un-implemented - - 

5 - 8 DRAM_PD(4:1) Dram Presence Detect. These lines are connected to the DRAM SIMM 

presence detect lines which encode the size and the delay of the DRAM 

SIMM mounted on the DRAM SIMM socket. For the encoding of 

DRAM_PD(4:1) see TABLE 4-16. "DRAM Presence Detect (2:1) 

Encoding" on page 64 and TABLE 4-17. "DRAM Presence Detect 

(4:3) Encoding" on page 64. 

- R 

9 - 12 Un used - R 

13 - 15 Un used - R 

13 - 31 Reserved Un-implemented. - - 

TABLE 4-15. Flash Presence Detect (4:1) Encoding 

FLASH_PD(4:1) FLASH TYPE / SIZE 

0 - 3 Reserved 

4 SM732A2000 / SM73228 - 8 Mbyte SIMM, by SMART Modular Technologies. 

5 SM732A1000A / SM73218 - 4 Mbyte SIMM, by SMART Modular 

Technologies. 

6 MCM29080 - 8 MByte SIMM, by Motorola 



9 - F Reserved 



ATT.


Freescale 




Inc. 


TABLE 4-16. DRAM Presence Detect (2:1) Encoding 

DRAM_PD(2:1) DRAM TYPE / SIZE 

00 MCM36100 by Motorola or MT8D132X by Micron- 4 MByte SIMM 

01 MCM36800 by Motorola or MT16D832X by Micron - 32 MByte SIMM 



TABLE 4-17. DRAM Presence Detect (4:3) Encoding 

DRAM_PD(4:3) DRAM DELAY 

00 Reserved 

01 Reserved 

10 70 nsec 

11 60 nsec 

WARNING 

Since EXTOLI(0:3) lines may be DRIVEN LOW (’0’) by the 

dip-switch, OFF-BOARD tools should NEVER DRIVE 

them HIGH. Failure in doing so, might result in PERMA- 

NENT DAMAGE to the ADS and / or to OFF-BOARD logic. 

4•11•5 BCSR3 - Board Control / Status Register 3 

BCSR3 is an additional control / status register which may be accessed at offset 0xC from BCSR base 

address. BCSR3 gets its defaults during Power-On reset and may be read or written at any time. The description 

of BCSR3 is shown in TABLE 4-18. "BCSR3 Description" on page 65. 





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Inc. 




0 - 1 Reserved Implemented ’00’ R 

2 - 7 Reserved . - R 

5 a 

a. 

CNT_REG_EN_P 

ROTECT 

Control Register Enable Protect. When this bit is active (low) the 

BCSR_EN bit in that register can not be written. When in-active, BCSR_EN 

may be written to remove the BCSR from the memory map. After any write 

to BCSR1 this bit becomes active again. This bit is a write-only bit on that 

register. 


The BCSR4 serves as a control register on the ADS. It is accessed at offset 10H from BCSR base address. 

It may be read or written at any time A . BCSR4 gets its defaults upon Power-On reset. BCSR4 fields are 


PON 

DEF 

ATT. 

0 W 

6 - 7 Reserved Un-Implemented - - 

8 Reserved . - R 

9 - 11 FLASH_PD(7:5) Flash Presence Detect(7:5). These lines are connected to the Flash SIMM 

presence detect lines which encode the Delay of Flash SIMM mounted on 

the Flash SIMM socket - U43. There are additional 4 presence detect lines 

which encode the SIMM’s Type but appear in BCSR2. For the encoding of 

FLASH_PD(7:5) see TABLE 4-19. "FLASH Presence Detect (7:5) 


12 Reserved - R 

13 Reserved Implemented ’0’ R 

14 - 15 Reserved - R 

TABLE 4-19. FLASH Presence Detect (7:5) Encoding 

FLASH_PD(7:5) Flash Delay [nsec] 

000 Not Supported 

001 150 

010 120 

011 90 

100 - 111 Not Supported 



-


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Inc. 


described in TABLE 4-20. "BCSR4 Description" on page 66. 

. 


The BCSR5 serves as a control register on the ADS. It is accessed at Address 0x2000300 on CS5. It may 

be written at any time. BCSR5 gets its defaults upon Power-On reset. BCSR5 fields are described in 

TABLE 4-21. "BCSR5 Description" on page 67 




0 ETHLOOP Ethernet port Diagnostic Loop-Back. When active (high), the MC68160 

EEST is configured into diagnostic Loop-Back mode, where the transmit 

output is internally fed back into the receive section. 

1 TFPLDL~ Twisted Pair Full-Duplex. When active (low), the MC68160 EEST is put 

into full-duplex mode, where, simultaneous receive and transmit are 

enabled. 

2 TPSQEL~ Twisted Pair Signal Quality Error Test Enable. When active (low), a 

simulated collision state is generated within the EEST, so the collision 

detection circuitry within the EEST may be tested. 

3 SIGNAL_LAMP Signal Lamp. When this signal is active (low), a dedicated LED illuminates. 

When in-active, this led is darkened. This led is used for S/W signalling to 

user. 


PON 

DEF 

ATT. 

0 R,W 

1 R,W 

1 R,W 

1 R,W 

4 un used 1 R,W 



7 un used. 0 R,W 






13 - 31 Reserved Un-implemented - - 




4•12 Debug Port Controller 

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Inc. 




7 RESET_MII Reset Fast Ethernet phy. Driving 1 to this pin reset the PHY. On 

power up reset this pin drive the value of MPC poreset signal. 

Write 0x01 in order to reset the phy. 

6 MII_RX_EN MII RX-signals three-state. driving this pin to 1 disable the 

output of the fast ethernet phy RX signals. Write 0x02 in order 

to disable the RX-Signals. 

5 RESET_ATM25 Reset ATM25 phy. Driving 1 to this pin reset the PHY. On 



4 RESET_ATM155 Reset ATM155 phy. Driving 1 to this pin reset the PHY. On 



3 RESET_Framer Reset E1/T1 Framer. Driving 1 to this pin reset the FRAMER. 

On power up reset this pin drive the value of MPC poreset 

signal. Write 0x10 in order to reset the framer. 

The debug port of the MPC86xADS is implemented on-board, connected to the MPC via the JTAGA port. 

Since the locationB of the debug port is determined via the Hard-Reset configuration, It is important that 

the relevant configuration bits (see 4•1•5 "Reset Configuration" on page 38) are not changed, if working 

with the local debug port is desired. 

The debug port controller is interfaced to host computer via Motorola’s ADI port, which is an 8-bit wide 

parallel port. Since the debug port is serial, conversion is done by hardware between the parallel and serial 

protocols. 

The MPC’s debug port is configured at SOFT-Reset to “Asynchronous Clock Mode” i.e., the debug port 

generates the debug clock - DSCK, which is asynchronous with the MPC system clock. 

The debug port controller block diagram is shown in FIGURE 4-8 "Debug Port Controller Block Diagram" 

on page 68. 


PON 

DEF 

ATT 

0 Write only 

0 Write only 

0 Write only 

0 Write only 

0 Write only 

2 un used 0 Write only 

1 un used 0 Write only 

0 un used Write only 

A. The debug port location is determined by the HARD - Reset configuration. 

B. In terms of MPC pins. 




ADI Address 

Selection 

Control / Status Register 

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Inc. 


FIGURE 4-8 Debug Port Controller Block Diagram 

ADI Port Connector 

ADI - Handshake Logic 

& Port Control 

Data Register 

Parallel Serial 

Converter 

Debug Port Conn. 

To allow for an external debug port controller to be incorporated with the ADS and to allow target system 

debug by the ADS, a standard 10 pin, debug port connector is provided and the local debug port controller 

may be disabledA by removing the ADI bundle from the its connector. 

When the ADI’s 37 lead cable is disconnected from either the ADI connector or from the ADS’s 37 pin connector, 

the debug port controller is disabled allowing either the connection of an external debug port controller, 

or independent s/w run, i.e., the MPC boots from the flash memory to run user’s application without 

debug port controller intervention. This feature becomes especially handy regarding demo’s. 

In this state, VFLS(0:1) or FRZB signals are routed to the debug port connector, so that, the external debug 

port controller has run mode status information. 

The ADI I/F supports upto 8 boards connected on the same bundle. Address selection is done by SW1 / 

1,2,3. See 2•3•2 "ADI Port Address Selection" on page 9. 

The debug port I/F has two registers: a control / status register and a data register. The control / status 

register hold I/F related control / status functions, while the data register serves as the parallel side of the 

Transmit / Receive shift register. 

The control / status register is accessed when D_C~ bit is low while the data register is accessed when 

D_C~ is driven high by the host via the ADI port. 

4•12•1 MPC86xADS As Debug Port Controller For Target System 

MPC86x 

HRESET* 

SRESET* 

VFLS0 

VFLS1 

The ADS may be used as a debug port controller for a target system, provided that the target system has 

A. I.e., debug port controller outputs are tri-stated, allowing debug port to be driven by an external debug-tool. 

B. Depended on H/W settings. 


S 0 



1 

0 

1 

’1’ 

’0’ 

J1 

S 

1 

0 

1 

0 

FRZ 

CHINS*(GND) 

DSDI 

DSCK 

DSDO


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Inc. 


a 10 pin header connector matching the one on the ADS. 

In this mode of operation, the on-board debug port controller, is connected to the target system’s debugport 

connector (see 4•12•1•1 "Debug Port Connection - Target System Requirements" below). Since 

DSDO signal is driven by the MPC, it is a must, to remove the local MPC from its socket, to avoid contention 

over this line. 

When either the local MPC is removed from its socket or the daughter board is removed from the ADS, all 

ADS’s modules are inaccessible, except for the debug-port controller. All module-enable indications are 

darkened, regardless of their associated enable bits in the BCSR. Pull-up resistors are connected to Chip- 

Select lines, so they do not float when the MPC is removed from its socket, avoiding possible contention 

over data-bus lines. 

4•12•1•1 Debug Port Connection - Target System Requirements 

In order for a target system may be connected to the ADS, as a debug port controller, few measures need 

to be taken on the target system: 

1) A 10-pin header connector should be made available, with electrical connections matching FIG- 

URE 4-9 "Standard Debug Port Connector" on page 71. 

2) Pull-down resistors, of app. 1KΩ should be connected over DSDI A and DSCKA signals. These 

resistors are to provide normalB operation, when a debug-port controller, is not connected to the 

target system 

3) The debug-port should be enabled and routed to the desired pins. See the DBGC and DBPC 

fields within the HARD-RESET configuration word. 

4•12•2 Debug Port Control / Status Register 

The control / status register is an 8 bit register (bit 7 stands for MSB). For the description of the ADI control 

status register see TABLE 4-22. "Debug Port Control / Status Register" on page 70. 

A. Remember that the location of DSDI and DSCK is determined by the HARD-Reset configuration. 

B. Normal - i.e., boot via CS0~. 





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Inc. 


TABLE 4-22. Debug Port Control / Status Register 


7 MpcRst Mpc Reset. When this status only bit indicates when active (high) that 

either a SOFT or a HARD reset is driven by the MPC. 

6 TxError Transmit Error. When this status only bit is active (high) it indicates that 

the last transmission towards the MPC, was cut by an internal MPC866 

reset source. This bit is updated for each byte sent. 

5 InDebug In Debug Mode. When this status only bit is active (high) it indicates that 

the MPC is in debug mode a . 

4 - 3 DebugClockFreq Debug Clock Frequency Select. This field controls a frequency divider 

which divides DSCK. For the division factors and associated DSCK 

frequencies see TABLE 4-23. "DSCK Frequency Select" below. 

2 StatusRequest Status Request. When the host writes this bit active (low), the I/F will issue 

a status read request to the host by asserting ADS_REQ line to the host. 

When the host writes the control register with this bit negated, no status 

read request is issued. 

Upon I/F reset this bit wakes-up active. 

1 DiagLoopBack Diagnostic Loopback Mode. When this control bit is active (low) the I/F is 

placed in Diagnostic Loopback Mode. I.e., DSDI is connected internally to 

DSDO, DSDI is tri-stated, and each data byte sent to the I/F data register, is 

sampled back into the receive shift register. This mode allows for complete 

ADI I/F test, upto transmit and receive shift registers. 


0 DebugEntry Debug Mode Entry. When this bit is active (low), the MPC will enter debug 

mode instantly after SOFT reset. When inactive, the MPC will start 

executing normally and will enter debug mode only after exception. 



I/F 

Res 

et 

DEF 

- R 

- R 

- R 

a. Provided that the PCMCIA channel II pins are configured as debug pins - i.e, VFLS(0:1) signals are available. If 

not, the debug port can not be operated correctly. 

TABLE 4-23. DSCK Frequency Select 

DebugClockFreq 

DSCK 

Frequency 

[MHz] 

00 10 

01 5 

10 2.5 



ATT. 

’00’ R/W 

0 R/W 

0 R/W 

0 R/W


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Inc. 


TABLE 4-23. DSCK Frequency Select 

DebugClockFreq 

DSCK 

Frequency 

[MHz] 

11 1.25 

FIGURE 4-9 Standard Debug Port Connector 

VFLS0 

GND 

GND 

HRESET 

VDD 

4•12•3 Standard MPCXXX Debug Port Connector Pin Description 

1 

3 

5 

7 

9 

2 

SRESET 

4 

DSCK 

6 

VFLS1 

8 

DSDI 

10 

DSDO 

The pins on the standard debug port connector are the maximal group needed to support debug port controllers 

for both the MPC5XX and MPC866 families. Some of the pins are redundant for the MPC866 family 

but are necessary for the MPC5XX family. 

4•12•3•1 VFLS(0:1) 

These pins indicate to the debug port controller whether or not the MPC is in debug mode. When both 

VFLS(0:1) are at ’1’, the MPC is in debug mode. These lines may serve alternate functions with the MPC, 

in which case FRZ needs to selected, on either the ADS or target system A . 

4•12•3•2 HRESET* 

This is the Hard-Reset bidirectional signal of the MPC. When this signal is asserted (low) the MPC enters 

hard reset sequence which include hard reset configuration. This signal is made redundant with the 

MPC866 debug port controller since there is a hard-reset command integrated within the debug port protocol. 

However, the local debug port controller uses this signal for compatibility with MPC5XX existing 

boards and s/w. 

4•12•3•3 SRESET* 

This is the Soft-Reset bidirectional signal of the MPC866. On the MPC5XX it is an output. The debug port 

configuration is sampled and determined on the rising-edge B of SRESET* (for both processor families). On 

the MPC866 it is a bidirectional signal which may be driven externally to generate soft reset sequence. This 

signal is in fact redundant regarding the MPC866 debug port controller since there is a soft-reset command 

integrated within the debug port protocol. However, the local debug port controller uses this signal for compatibility 

with MPC5XX existing boards and s/w. 

4•12•3•4 DSDI - Debug-port Serial Data In 

Via the DSDI signal, the debug port controller sends its data to the MPC. The DSDI serves also a role 

A. If a target system needs to use VFLS(0:1) alternate function, then, FRZ line should be connected to both VFLS(0:1) 

pins on the debug port connector. 

B. In fact that configuration is divided into 2 parts, the first is sampled 3 system clock cycles prior to the rising edge 

of SRESET* and the second is sampled 8 clocks after that edge. 





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Inc. 


during soft-reset configuration. (See 4•1•5•3 "Soft Reset Configuration" on page 39). 

4•12•3•5 DSCK - Debug-port Serial Clock 

During asynchronous clock mode, the serial data is clocked into the MPC according A to the DSCK clock. 

The DSCK serves also a role during soft-reset configuration. (See 4•1•5•3 "Soft Reset Configuration" on 

page 39). 

4•12•3•6 DSDO - Debug-port Serial Data Out 

DSDO is clocked out by the MPC according to the debug port clock, in parallel B with the DSDI being 

clocked in. The DSDO serves also as "READY" signal for the debug port controller to indicate that the 

debug port is ready to receive controller’s command (or data). 

4•13 Power 

There are 3 power buses with the MPC866s: 

1) I/O 

2) Internal Logic 

3) PLL 

and there are 4 power buses on the MPC86xADS: 

1) 5V bus 

2) 3.3V bus. 

3) 12V bus. 

A. I.e., DSDI must meat setup / hold time to / from rising edge of the DSCK. 

B. I.e., full-duplex communication. 





5V 

12V 

ADS Logic & Peripherals 

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Inc. 

3.3V 


FIGURE 4-10 MPC86xADS Power Scheme 

PCMCIA 

Power 

Control 

PCMCIA 

Buffers 

VCC 

VPP 

PC-Card Socket 

To support off-board application development, the power buses are connected to the expansion connectors, 

so that external logic may be powered directly from the board. The maximum current allowed to be 

drawn from the board on each bus is shown in TABLE 4-24. "Off-board Application Maximum Current Consumption" 

below. 

TABLE 4-24. Off-board Application Maximum Current Consumption 

Power BUS Current 

5V 1.5A 

3.3V 1.5A 

12V 100 mA. 

To protect on board devices against supply spikes, decoupling capacitors (typically 0.1µF) are provided 

between the devices’ power leads and GND, located as close as possible to the power leads. 


1.8V 

VDDSYN 



K.A. 

MPC8XX 

VDDL 

VDDH 

Expansion Con.


4•13•1 5V Bus 

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Inc. 


Some of the ADS peripherals reside on the 5V bus. Since the MPC is not 5V friendly, a 3.3V to 5V buffers 

added between the MPC and the 5v devices, so it may operate with 5V levels on its lines with no damage. 

The 5V bus is connected to an external power connector via a fuse (5A). 

To protect against reverse-voltage or over-voltage being applied to the 5V inputs a set of high-current 

diodes and zener diode is connected between the 5V bus GND. When either over or reverse voltage is 

applied to the ADS, the protection logic will blow the fuse, while limiting the momentary effects on board. 

4•13•2 3.3V Bus 

The MPC itself as well as the SDRAM, the address and data buffers are powered by the 3.3 A bus, which 

is produced from the 5V bus using a special low-voltage drop, linear voltage regulator made by Micrel, the 

MIC29500-3.3BT which is capable of driving upto 5A, facilitating operation of external logic as well. 

4•13•3 12V Bus 

The sole purpose of the 12V bus is to supply VPP (programming voltage) for the PCMCIA card and for the 

Flash SIMM B . It is connected to a dedicated input connector via a fuse (1A) and protected from over / 

reverse voltage application. 

If the 12V supply is not required for either the PC-Card and for the flash SIMM, the 12V input to the ADS 

may be omitted. 

A. At full speed. When lower performance is needed the internal logic may be powered from the 2V bus. 

B. If necessary. 





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Inc. 

Support Information 

5 - Support Information 

In this chapter all information needed for support, maintenance and connectivity to the MPC86xADS is provided. 

5•1 Interconnect Signals 

The MPC86xADS interconnects with external devices via the following set of connectors: 

1) P1 - 10BaseT Ethernet port 

2) P2A - RS232 port 1 

3) P2B - RS232 port 2 

4) P3 - T1/E1 RJ45 Connector. 

5) P4 - ATM25 RJ45 Connector. 

6) P5 - ATM155 multy mode optical connector. 

7) P6 - ADI Port connector. 

8) P7 - Serial Ports’ Expansion connector. 

9) P8, P11, P14, P16, P17 and P19 Mictor, Logic Analyser connectors. 

10) P9 - External Debug port controller input / output 

11) P10 - 100BaseT Ethernet port. RJ45. 

12) P12 - 12V Power In. 

13) P13 - 3 Pin 5V Power In 

14) P13A - Power Jack connector 2.1mm. Will be connected to the supplied power supply. 

15) P15 - ISP connector for Mach programing. 

16) P18 - BNC connector - not populated. 

17) P20 - JTAG connector for Altera programing. 

18) P21 - MPC862/6 Address Data & control signals, Expansion connector. 

19) P22 - PCMCIA port 

20) IR1 - Infra - Red interface. 

5•1•1 P1 - 10BaseT Ethernet Port Connector 

The Ethernet connector on the MPC86xADS - P1, is a Twisted-Pair (10-Base-T) compatible connector. 

Use is done with 90 o , 8-pin, RJ45 connector, signals of which are described in TABLE 5-1 "P1 - Ethernet 

Port Interconnect Signals" below. 

TABLE 5-1 P1 - Ethernet Port Interconnect Signals 

Pin No. Signal Name Description 

1 TPTX Twisted-Pair Transmit Data positive output from the MPC86xADS. 

2 TPTX~ Twisted-Pair Transmit Data negative output from the MPC86xADS. 

3 TPRX Twisted-Pair Receive Data positive input to the MPC86xADS. 

4 - Not connected 





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Inc. 


TABLE 5-1 P1 - Ethernet Port Interconnect Signals 



6 TPRX~ Twisted-Pair Receive Data negative input to the MPC86xADS. 



5•1•2 PA2, PB2 - RS232 Ports’ Connectors 

The RS232 ports’ connectors - PA2 and PB2 are 9 pin, 90 o , female D-Type Stacked connectors, signals of 

which are presented in TABLE 5-2. "PA2, PB2 Interconnect Signals" below 

5•1•3 P3 - T1/E1 RJ45 Connector. 

TABLE 5-2. PA2, PB2 Interconnect Signals 


1 CD Carrier Detect output from the MPC86xADS. 

2 TX Transmit Data output from the MPC86xADS. 

3 RX Receive Data input to the MPC86xADS. 

4 DTR Data Terminal Ready input to the MPC86xADS. 

5 GND Ground signal of the MPC86xADS. 

6 DSR Data Set Ready output from the MPC86xADS. 

7 RTS (N.C.) Request To Send. This line is not connected in the MPC86xADS. 

8 CTS Clear To Send output from the MPC86xADS. 


The T1/E1 connector on the MPC86xADS - P3, is a Twisted-Pair 8 pin connector. signals of which are described 

in TABLE 5-3. "P3 - T1/E1 RJ45 Connector." below. 

TABLE 5-3. P3 - T1/E1 RJ45 Connector. 




3 GND Connected to GND 







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Inc. 

6 GND Connected to GND 



5•1•4 P4 - ATM25 RJ45 Connector. 


TABLE 5-3. P3 - T1/E1 RJ45 Connector. 


The ATM25 connector on the MPC86xADS - P4, is a Twisted-Pair 8 pin connector. signals of which are 

described in TABLE 5-4. "P4 - ATM25 RJ45 Connector." below. 

5•1•5 P5 - ATM155 multy mode optical connector. 

This connector is optical connector with RX and TX SC type also for receive and transmit. 

5•1•6 P6 ADI - Port Connector 

TABLE 5-4. P4 - ATM25 RJ45 Connector. 


1 TPTX Twisted-Pair Transmit Data positive input to the MPC86xADS. 

2 TPTX~ Twisted-Pair Transmit Data negative input to the MPC86xADS. 

3 Not Connected Not Connected 

4 Not Connected Not connected 

5 Not Connected Not connected 

6 Not connected Not connected 

7 TPRX Twisted-Pair Receive Data positive output from the MPC86xADS. 

8 TPRX~ Twisted-Pair Receive Data positive output from the MPC86xADS. 

The ADI port connector - P6, is a 37-pin, Male, 90 o , D-Type connector, signals of which are described in 

TABLE 5-5. "P1 - ADI Port Interconnect Signals" below: 

TABLE 5-5. P1 - ADI Port Interconnect Signals 


1 Not connected with this application 

2 D_C~ Data / Control selection. When ’1’, the debug port controller’s data register is accessed, 

when ’0’ the debug port controller’s control register is accessed. 

3 HST_ACK Host Acknowledge input signal from the host. 

4 ADS_SRESET When asserted (’1’) and the ADS is selected by the host, generates Soft Reset to the 

MPC. 

5 ADS_HRESET When asserted (’1’) and the ADS is selected by the host, generates Hard Reset 

to the MPC. 

6 ADS_SEL2 ADI I/F address line 2 (MSB). 





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Inc. 


TABLE 5-5. P1 - ADI Port Interconnect Signals 


7 ADS_SEL1 ADI I/F address line 1. 

8 ADS_SEL0 ADI I/F address line 0 (LSB). 

9 HOST_REQ HOST Request input signal from the host 

10 ADS_REQ ADS Request output signal from the MPC86xADS to the host 

11 ADS_ACK ADS Acknowledge output signal from the MPC86xADS to the host 





16 PD1 Bit 1 of the ADI port data bus 




20 - 25 GND Ground. 


27 - 29 HOST_VCC HOST VCC input from the host. Used to qualify ADS selection by the host. When host 

is off, the debug port controller is disabled. 

30 HOST_ENABLE~ HOST Enable input signal from the host. (Active low). Indicates that the host computer 

is connected to ADS. Used, in conjunction with HOST_VCC and ADS_SEL(2:0) to 

qualify ADS selection by the host. 

31 - 33 GND Ground. 





5•1•7 MPC86XADS’s P7 - Serial Ports’ Expansion Connector 

P8 is a 96 pin, 900, DIN 41612 connector, which allows for convenient expansion of the MPC’s serial ports. 

Note: 





Freescale 




Inc. 


The contents of TABLE 5-6. "MPC86XADS’s P7 - Interconnect 

Signals" below, might conflict with MPC8XXFADS’s 

schematic page 14. This since, that the schematic page 

is named in MPC821/860 terms. In such case, this table 

overrides! 

TABLE 5-6. MPC86XADS’s P7 - Interconnect Signals 

Pin No. Signal Name Attribute Description 

A1 ETHRX I/O 10Base-T Ethernet port receive data. 

A2 ETHTX I/O 10Base-T Ethernet Port transmit data. 

A3 IRDRXD I/O IrDA port receive data. 

A4 IRDTXD I/O IrDA port transmit data. 

A5 MPD11 I/O This pin connected through Bus Switch to MPC PORT D11, and 

controlled by SW3(2,3,4). 







A9 ETHTCK I/O 10Base-T Ethernet port transmit clock. 

A10 ETHRCK I/O 10Base-T Ethernet port receive clock. 

A11 PA5 I/O MPC86x PA5 Pin. 

A12 PA4 I/O MPC86X PA[4] PIN. 





A17 VCC - 





A22 GND - 

A23 GND - 

A24 IRQ7~ I, L This pin connected through Bus Switch to MPC IRQ7~, and 






Freescale 




Inc. 




A25 FRZ I/O MPC86x FRZ pin. 

A26 ETHEN~ O Ethernet Enable Pin from mach. 

A27 IRQ3~ I, L MPC86x RQ3~ Pin. 

A28 IRQ2~ I, L RSV/IRQ2~. See PM2(26). 

A29 IRQ1~ I, L MPC86x RQ1~ Pin. 

A30 NMI~ I, L MPC86x NMI~ Pin. 

A31 RS_EN1~ O,L RS232 _1Enable from mach. 

A32 GND - 

B1 PB31 I/O MPC86x PB31 Pin. 






B7 RSTXD1 I/O MPC86x PB25 / This pin use on the board as RS232_1 TXD 

signal. 

B8 RSRXD1 I/O MPC86x PB24 / This pin use on the board as RS232_1 RXD 

signal. 

B9 RSDTR1~ I/O MPC86x PB23 / This pin use on the board as RS232_1 DTR 

signal. 

B10 RSDTR2~ I/O MPC86x PB22 / This pin use on the board as RS232_2 DTR 

signal. 

B11 TXD2. I/O MPC86x PB21 / This pin use on the board as RS232_2 TXD 

signal. 

B12 RSRXD2 I/O MPC86x PB20 / This pin use on the board as RS232_2 RXD 

signal. 

B13 E_TENA I/O MPC86x PB19 / This pin use on the board as Ethernet 10Base-T 

TENA signal. 

B14 PB18 I/O MPC86x PB18 PIN. 

B15 PB17 I/O MPC86x PB17 PIN. 

B16 PB16 I/O MPC86x PB16 PIN 



B19 GND - 





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Inc. 




B20 RXCLAV I/O MPC86x PC15 / Use as RXCLAV for ATM or INPACK for 

PCMCIA, The selection is done by SW3(2,3,4). 

B21 PC14 I/O MPC86x PC14 PIN. 



B24 E_CLSN I/O 10Base-T Ethernet port collision signal. 

B25 E_RENA I/O 10Base-T Ethernet port RENA signal. 

B26 PC9 I/O PMC86x PC9 PIN. 






B32 GND - 

C1 VCC 

C2 

C3 

C4 

C5 

C6 RS_EN2~ O, L RS232 _2Enable from mach. 

C7 GND 

C8 

C9 

C10 

C11 

C12 

C13 

C14 

C15 MPD15 I/O This pin connected through Bus Switch to MPC PORT D15, and 








Freescale 




Inc. 












C21 VCC - 

C22 HRESET~ I/O, L MPC86x Hreset PIN 

C23 SRESET~ I/O, L MPC86x Sreset PIN 

C24 N.C. - Not Connected 

C25 VCC - 



C27 VPPIN I/O +12V input for PCMCIA flash programming. Parallel to P12 of the 

MPC86xADS. 

C28 

C29 GND - 



C31 GND - 







Freescale 




Inc. 


5•1•8 P8, P11, P14, P16, P17 and P19 Mictor, Logic Analyser connectors. 

These connectors are 38 pin, receptacle MICTOR connectors made by AMP. Each connector connects to 

a dedicated adaptor for HP 16500 series of logic analyzer, which interconnects to two 16 bit pods. 

TABLE 5-7. P17 Interconnect Signals 

Pin# 

MPC862/6 

Signal 

Name 


Pin# 

1 N.C. 2 N.C. 

3 GND 4 N.C. 

MPC862/6 

Signal 

Name 

5 EXTCLK 6 ALEA 

7 N.C. 8 IRQ2b 

9 AT1 10 IRQ3b 

11 TEXP 12 DP0 

13 RESETA 14 DP1 

15 PDEAb 16 DP2 

17 MODCK1 18 DP3 

19 MODCK2 20 FRZ 

21 PORSTb 22 SPKROUT 

23 RSTCNFb 24 IPA0 

25 HRESETb 24 IPA1 

27 SRESETb 28 IPA2 

29 WAITBb 30 IPA3 

31 WAITAb 32 IPA4 

33 GPL4Ab 34 IPA5 

35 GPL4Bb 36 IPA6 

37 CE1Ab 38 IPA7 

TABLE 5-8. P19 - Interconnect Signals 

Pin# 

MPC862/6 

Signal 

Name 

Pin# 

1 N.C. 2 N.C. 

3 GND 4 N.C. 

MPC862/6 

Signal 

Name 




Freescale 




Inc. 



Pin# 

5 TAb 6 TEAb 

7 VFLS0 8 FCSb 

9 VFLS1 10 BCSRCSb 

11 AT2 12 DRMCS1b 

13 VF2 14 DRMCS2b 

15 VF0 16 SDRMCSb 

17 VF1 18 CS5b 

19 AT0 20 CS6b 

21 AT3 22 CS7b 

23 BCD1~ 24 BS0Ab 

25 BGb 26 BS1Ab 

27 BRb 28 BS2Ab 

29 BIb 30 BS3Ab 

31 GPL5Bb 32 WE0b 

33 BURSTb 34 WE1b 

35 RWb 36 WE2b 

37 TSb 38 WE3b 


Pin 

# 

MPC862/6 

Signal 

Name 

MPC862/6 

Signal 

Name 


Pin# 

Pin 

# 

1 N.C. 2 N.C. 

3 GND 4 N.C. 

MPC862/6 

Signal 

Name 

5 DRMWb 6 CE2Ab 

7 GPL5Ab 8 PA0 

9 GPL3b 10 PA1 

11 GPL2b 12 PA2 

13 EDOOEb 14 PA3 

15 PC4 16 PA4 

17 PC5 18 PA5 

MPC862/6 

Signal 

Name 




Freescale 




Inc. 



Pin 

# 

19 PC6 20 ETHRCK 

21 PC7 22 ETHTCK 

23 PC8 24 PA8 

25 PC9 26 PA9 

27 ERENA 28 PA10 

29 ECLSN 30 PA11 

31 PC12 32 IRDTXD 

33 PC13. 34 IRDRXD 

35 PC14 36 ETHTX 

37 BINPAKb 38 ETHRX 


Pin 

# 

MPC862/6 

Signal 

Name 

MPC862/6 

Signal 

Name 


Pin 

# 

Pin 

# 

1 GND 2 N.C. 

3 N.C. 4 N.C. 

MPC862/6 

Signal 

Name 

5 SYSCLK 6 MODCK1 

7 A0 8 A16 

9 A1 10 A17 

11 A2 12 A18 

13 A3 14 A19 

15 A4 16 A20 

17 A5 18 A21 

19 A6 20 A22 

21 A7 22 A23 

23 A8 24 A24 

25 A9 26 A25 

27 A10 28 A26 

MPC862/6 

Signal 

Name 




Freescale 




Inc. 



Pin 

# 

29 A11 30 A27 

31 A12 32 A28 

33 A13 34 A29 

35 A14 36 A30 

37 A15 38 A31 


Pin 

# 

MPC862/6 

Signal 

Name 

MPC862/6 

Signal 

Name 


Pin 

# 

Pin 

# 

1 N.C. 2 N.C. 

3 GND 4 N.C. 

MPC862/6 

Signal 

Name 

5 IRQ1b 6 IRQ7b 

7 NMIb 8 PB16 

9 PD3 10 PB17 

11 PD4 12 PB18 

13 PD5 14 ETENA 

15 PD6 16 RSRXD2 

17 PD7 18 RSTXD2 

19 PD8 20 RSDTR2b 

21 PD9 22 RSDTR1b 

23 PD10 24 RSRXD1 

25 PD11 26 RSTXD1 

27 PD12 28 PB26 

29 PD13 30 PB27 

31 PD14 32 PB28 

33 PD15 34 PB29 

35 PB14 36 PB30 

37 PB15 38 PB31 

MPC862/6 

Signal 

Name 




Freescale 




Inc. 



Pin 

# 

MPC862/6 

Signal 

Name 


Pin 

# 

1 N.C. 2 N.C. 

3 GND 4 N.C. 

MPC862/6 

Signal 

Name 

5 REGAb 6 TSIZ1 

7 D0 8 D16 

9 D1 10 D17 

11 D2 12 D18 

13 D3 14 D19 

15 D4 16 D20 

17 D5 18 D21 

19 D6 20 D22 

21 D7 22 D23 

23 D8 24 D24 

25 D9 26 D25 

27 D10 28 D26 

29 D11 30 D27 

31 D12 32 D28 

33 D13 34 D29 

35 D14 36 D30 

37 D15 38 D31 




Freescale 




Inc. 


5•1•9 P9 - External Debug Port Controller Input Interconnect. 

The debug port connector - P9, is a 10 pin, Male, header connector, signals of which are described in 

TABLE 5-16. "P13 - Interconnect Signals" below 



1 VFLS0 O Visible history FLushes Status 0. Indicates in conjunction with 

VFLS1, the number of instructions flushed from the core’s history 

buffer. Indicates also whether the MPC is in debug mode. If not 

using the debug port, may be configured for alternate function. 

When the ADS is disconnected from the ADI bundle, it may be 

FRZ signal, depended on J1’s position. 

2 SRESET~ I/O Soft Reset line of the MPC. Active-low, Open-Drain. 

3 GND Ground. 

4 DSCK I/O Debug Serial Clock. Over the rising edge of which serial date is 

sampled by the MPC from DSDI signal. Over the falling edge of 

which DSDI is driven towards the MPC and DSDO is driven by 

the MPC. Configured on the MPC’s JTAG port. 

When the debug-port controller is on the local MPC or when the 

ADS is a debug-port controller for a target system - OUTPUT, 

when the FADI bundle is disconnected from the ADS - INPUT. 

5 GND Ground 

6 VFLS1 O See VFLS0. When the ADS is disconnected from the ADI bundle, 

it may be FRZ signal, depended on J1’s position. 

7 HRESET~ I/O Hard Reset line of the MPC. Active-low, Open-Drain 

8 DSDI I/O Debug Serial Data In of the debug port. Configured on the MPC’s 

JTAG port. 


ADS is a debug-port controller for a target system - OUTPUT, 

when the ADI bundle is disconnected from the ADS - INPUT. 

9 V3.3 O 3.3V Power indication. This line is merely for indication. No 

significant power may be drawn from this line. 

10 DSDO I/O Debug Serial Data Output from the MPC. Configured on the 

MPC’s JTAG port. 


ADI bundle is disconnected from the ADS - OUTPUT, when the 

ADS is a debug-port controller for a target system - INPUT. 

5•1•10 P10 - 100BaseT Ethernet Port Connector 

The Ethernet connector on the MPC86xADS - P1, is a Twisted-Pair (100-Base-T) compatible connector. 

Use is done with 90 o , 8-pin, RJ45 connector, signals of which are described in TABLE 5-14. "P10 - Ethernet 

Port Interconnect Signals" below. 





Freescale 




Inc. 

5•1•11 P12 - 12V Power Connector 


TABLE 5-14. P10 - Ethernet Port Interconnect Signals 










The 12V power connector - P12, is a two-lead, 2 part, terminal block connector, identical in type to the 5V 

connector. P12 supplies, when necessary, programming voltage to the Flash SIMM and / or to the PCMCIA 

Pin 

Number 

5•1•12 P13 - 5V Power Connector 


Signal Name Description 

1 12V 12V input from external power supply. 

2 GND GND line from external power supply. 

The 5V power connector - P13, is a 3-lead, two-part terminal block. The male part is soldered to the pcb, 

while the receptacle is connected to the power supply. That way fast connection / disconnection of power 

is facilitated and physical efforts are avoided on the solders, which therefore maintain solid connection over 

time. 

Pin 

Number 


Signal Name Description 

1 5V 5V input from external power supply. 







Freescale 




Inc. 


5•1•13 P13A - Power Jack connector 2.1mm. 

P13A is a Plug Jack connector 2.1mm that is connected to the power supply supplied with the board. 

Inorder to operate the board the user shpould plug in the connector of the power supply to this connector. 

5•1•14 P15 - Mach’s In System Programming (ISP) 

This is a 10 pin generic 0.100" pitch header connector, providing In System Programming capability for 

Vantis made programmable logic on board. The pinout of P11 is shown in TABLE 5-17. ". P15 - ISP Connector 

- Interconnect Signals" below: 

TABLE 5-17. . P15 - ISP Connector - Interconnect Signals 

Pin No. Pin Name Attribute Description 

1 ISPTCK I ISP Test port Clock. This clock shifts in / out data to / from the 

programmable logic JTAG chain. 

2 N.C. - Not Connected. 

3 ISPTMS I ISP Test Mode Select. This signal qualified with ISPTCK, changes the 

state of the prog. logic JTAG machine. 

4 GND O Digital GND. Main GND plane. 

5 ISPTDI I ISP Transmit Data In. This is the prog. logic’s JTAG serial data input. 

6 VCC O 5V/3.3 power supply bus. the power can be change by RJ4 by 

connecting a resistor from 1, 2 to power 5V, or 2, 3 to power 3.3V 

7 ISPTDO O ISP Transmit Data Output. This the prog. logic’s JTAG serial data output 

driven by Falling edge of TCK. 




5•1•15 P18 - BNC connector - not populated. 

Is a BNC connector in order to drive clock in to MPC EXTCLK pin this BNC is not populated. the user can 

use this connector but he should first connect RJ3 pins 2, 3. It is factory connect pins 1, 2. 

5•1•16 P20 - JTAG connector for Altera programing. 

This is a 10 pin generic 0.100" pitch header connector, providing In System Programming capability for 

altera made programmable logic on board. The pinout of P11 is shown in TABLE 5-18. "P20 - JTAG connector 

for Altera programing." below: 

TABLE 5-18. P20 - JTAG connector for Altera programing. 


1 TCK I Test port Clock. This clock shifts in / out data to / from the 

programmable logic JTAG chain. 






Freescale 




Inc. 


TABLE 5-18. P20 - JTAG connector for Altera programing. 


3 TDO O Transmit Data Output. This the prog. logic’s JTAG serial data output 

driven by Falling edge of TCK. 

4 VCC O 5V power supply bus. 

5 TMS I Test Mode Select. This signal qualified with TCK, changes the state of 

the prog. logic JTAG machine. 




9 TDI I Transmit Data In. This is the prog. logic’s JTAG serial data input. 


5•1•17 Expansion Connector ADD, Data control & PCMCIA Port. 

P21 is a 96 pin, 900, DIN 41612 connector, which allows for convenient expansion of the MPC’s.This connector 

include the necessary signals inorder to connect external peripherals with address data and control 

signals, also in this connector there are the PCMCIA signals that can be use for ATM Split mode. in order 

to use ATM Split from the Expansion connectors the user should control it through SW3(2,3,4) most of the 

pins are on P7 and the PCMCIA pins are on P21. This connector is also include MII signals for using in 

external board the signals are CRS, MDIO, TXEN and COL. For using external Fast ethernet the user 

should connect P21(A25) to GND. 





Freescale 




Inc. 




A1 EXATMRSC O In External ATM Split connected to the Expansion connectors, P7 

& P21 when putting SW3(2 =,ON 3 = ON, 4 = ON). This pin is the 

RXSOC. 

A2 EXATMRD0 O In External ATM Split connected to the Expansion connectors, P7 


RXD0. For external MII this pin is MIIRXD3. 












RXD4. For external MII this pin is MIIRXCLK. 



RXD5. For external MII this pin is MIIRXERR 



RXD6. For external MII this pin is MIITXERR. 



RXD7. For external MII this pin is MIIRXDV. 

A10 GND GND 

A11 EXATMRCK O In External ATM Split connected to the Expansion connectors, P7 


RXCLK. For external MII this pin is MIITXD0. 

A12 GND GND 

A13 N.C 

A14 BWE0b O MPC86x WE0 Pin. For external peripheral. 

A15 BDRMWb O MPC86x GPL0 signal use for DRAM write signal. 

A16 BEDOOEb O MPC86x GPL1 Pin use for DRAM oe~ signal. 

A17 BGPL2b O MPC86x GPL2 Pin. 

A18 BGPL3b O MPC86x GPL3 Pin. 





Freescale 




Inc. 




A19 GPL4Ab O MPC86x GPL4A Pin. 

A20 GPL4Bb O MPC86x GPL4B Pin. 

A21 GPL5Ab O MPC86x GPL5A Pin. 

A22 GPL5Bb O MPC86x GPL5B Pin 

A23 GND 

A24 BSYSCLK3 O MPC86x CLKOUT Pin, drive by zero delay buffer. 

A25 GND GND. 

A26 BS0Ab O MPC86x BS0b Pin. (buffered) 

A27 GND GND. 

A28 BRW2b O MPC86x RWb Pin. (buffered) 

A29 BTSb O MPC86x TSb Pin (buffered). 

A30 TAb O MPC86x TA Pin. 

A31 CS7b I MPC86x CS7 Pin. 

A32 CS6b I MPC86x CS6 Pin 

B1 3.3V I/O Power 3.3V. 






B7 I/O 

B8 GND I/O 

B9 EXPMITXD3 I/O MPC86x CE2A / In External MII connected to the Expansion 

connectors, P7 & P21 when putting SW3(2 =,ON 3 = ON, 4 = 

ON). This pin is the MIITXD3. 

B10 EXPMITXD2 I/O MPC86x CE1A / In External MII connected to the Expansion 



B11 EXPMITXD1 I/O MPC86x ALE / In External MII connected to the Expansion 



B12 EXPCOL I/O MPC86x MIICOL / In External MII connected to the Expansion 


ON). This pin is the MIICOL, also P21(A25) must be connected to 

GND. 





Freescale 




Inc. 




B13 EXPTXEN I/O MPC86x MIITXEN / In External MII connected to the Expansion 


ON). This pin is the MIITXEN, also P21(A25) must be connected 

to GND. 

B14 EXPMDIO I/O MPC86x MIIDIO / In External MII connected to the Expansion 


ON). This pin is the MIIMDIO, also P21(A25) must be connected 

to GND. 

B15 EXPCRS I/O MPC86x MIICRS / In External MII connected to the Expansion 


ON). This pin is the MIICRS, also P21(A25) must be connected to 

GND. 

B16 GND I/O GND 

B17 N.C 


B19 N.C - 


B21 N.C 


B23 N.C 


B25 N.C 


B27 N.C 


B29 N.C 


B31 N.C 

B32 GND - GND 





Freescale 




Inc. 




C1 BD0 I/O MPC86x Buford D0 - D7 to connect and control the external 

peripheral connected to the expansion connectors. 

C2 BD1 I/O 

C3 BD2 I/O 

C4 BD3 I/O 

C5 BD4 I/O 

C6 BD5 I/O 

C7 BD6 I/O 

C8 BD7 I/O 

C9 BA16 MPC86x A16 - A31(buffered BA16 - BA31) to connect and control 

the external peripheral connected to the expansion connectors. 

C10 BA17 

C11 BA18 

C12 BA19 

C13 BA20 

C14 BA21 

C15 BA22 

C16 BA23 

C17 BA24 

C18 BA25 

C19 BA26 

C20 BA27 

C21 BA28 

C22 BA29 

C23 BA30 

C24 BA31 

C25 MIISELb 

C26 N.C 

C27 N.C I/O 

C28 N.C 

C29 N.C - 

C30 N.C I/O 

C31 N.C - 





C32 N.C 

Freescale 




Inc. 




5•1•18 PCMCIA Port Connector 

The PCMCIA port connector - P22, is a 68 - pin, Male, 90 0 , PC Card type, signals of which are presented 

in TABLE 5-20. "P22 - PCMCIA Connector Interconnect Signals" below 

TABLE 5-20. P22 - PCMCIA Connector Interconnect Signals 


1 GND Ground. 

2 PCCD3 I/O PCMCIA Data line 3. 





7 BCE1A~ O PCMCIA Chip Enable 1. Active-low. Enables EVEN numbered 

address bytes. 

8 PCCA10 O PCMCIA Address line 10. 

9 OE~ O PCMCIA Output Enable signal. Active-low. Enables data outputs 

from PC-Card during memory read cycles. 






15 WE~/PGM~ O PCMCIA Memory Write Strobe. Active-low. Strobes data to PC- 

Card during memory write cycles. 

16 RDY I +Ready/-Busy signal from PC-Card. Allows PC-Card to stall 

access from the host, in case a previous access’s processing is 

not completed. 

17 PCCVCC O 5V VCC for the PC-Card. Switched by the MPC86xADS, via 

BCSR1. 

18 PCCVPP O 12V/5V VPP for the PC-Card programming. 12V available only 

if12V is applied to P8. Controlled by the MPC86xADS, via 

BCSR1. 






Freescale 




Inc. 

















33 WP I Write Protect indication from the PC-Card. 

34 GND Ground 

35 GND Ground 

36 CD1~ I Card Detect 1~. Active-low. Indicates in conjunction with CD2~ 

that a PC-Card is placed correctly in socket. 






42 BCE2A~ O PCMCIA Chip Enable 2. Active-low. Enables ODD numbered 

address bytes. 

43 VS1 I Voltage Sense 1 from PC-Card. Indicates in conjunction with VS2 

the operation voltage for the PC-Card. 

44 IORD~ O I/O Read. Active-low. Drives data bus during I/O-Cards’ read 

cycles. 

45 IOWR~ O I/O Write. Active-low. Strobes data to the PC-Card during I/O- 

Card write cycles. 








Freescale 




Inc. 






51 PCCVCC O 5V VCC for the PC-Card. Switched by the MPC86xADS, via 

BCSR1. 

52 PCCVPP O 12V/5V VPP for the PC-Card programming. 12V available only 

if12V is applied to P8. Controlled by the MPC86xADS, via 

BCSR1. 





57 VS2 I Voltage Sense 2 from PC-Card. Indicates in conjunction with VS1 

the operation voltage for the PC-Card. 

58 RESET O Reset signal for PC-Card. 

59 WAITA~ I Cycle Wait from PC-Card. Active-low. 

60 INPACK~ I Input Port Acknowledge. Active-low. Indicates that the Pc-Card 

can respond to I/O access for a certain address. 

61 PCREG~ O Attribute Memory or I/O Space - Select. Active-low. Used to select 

either attribute (card-configuration) memory or I/O space. 

62 BVD2 I Battery Voltage Detect 2. Used in conjunction with BVD1 to 

indicate the condition of the PC-Card’s battery. 

63 BVD1 I Battery Voltage Detect 1. Used in conjunction with BVD2 to 

indicate the condition of the PC-Card’s battery. 




67 CD2~ I Card Detect 2~. Active-low. Indicates in conjunction with CD1~ 

that a PC-Card is placed correctly in socket. 

68 GND Ground. 





5•2 MPC86xADS Part List 

Freescale 




Inc. 


In this section the MPC86xADS’s bill of material is listed according to their reference designation. 

TABLE 5-21. MPC86xADS Part List 

Reference Designation Part Description Manufacturer Part # 

C1,C23,C45,C46,C47,C48, 

C49,C50,C55,C56,C57,C265, 

C2,C3,C4,C5,C6,C7,C8,C9, 

C10,C13,C14,C16,C17,C26, 

C27,C28,C30,C31,C32,C33, 

C37,C38,C39,C40,C41,C42, 

C44,C51,C52,C58,C60,C62, 

C64,C65,C66,C67,C68,C69, 

C74,C77,C81,C83,C84,C85, 

C89,C91,C92,C94,C95,C96, 

C97,C101,C102,C103,C104, 

C106,C107,C110,C111,C112, 

C113,C115,C120,C121,C125, 

C133,C134,C137,C139,C141, C142, 

C143,C144,C145,C146,C148, 

C150,C152,C154,C155,C157, 

C160,C161,C162,C163,C165, 

C167,C168,C169,C170,C172, 

C174,C175,C177,C180,C181, 

C183,C185,C188,C190,C191, 

C193,C194,C195,C196,C200, 

C201,C202,C203,C204,C205, 

C208,C211,C212,C213,C214, 

C217,C218,C219,C220,C221, 

C223,C225,C226,C227,C228, 

C230,C232,C233,C235,C236, 

C237,C238,C239,C241,C245, 

C247,C253,C254,C256,C257, 

C258,C259,C261,C262,C263, 

C264,C266,C268,C270,C272, 

C273,C276,C277,C279,C280, 

C281,C282,C283,C285,C288, 

C290,C295,C296,C297,C298, 

C300,C301,C302,C306,C308, 

C312,C313,C314,C315,C316, 

C317,C318,C319,C320,C321, 

C322,C323,C324,C325,C326, 

C327,C329,C330 

C11,C12,C15,C24,C25,C29, 

C34,C70,C71,C72,C75,C78, 

C79,C80,C82,C87,C88,C90, 

C93,C98,C99,C100,C105, 

C108,C109,C114,C116,C117, 

C118,C119,C126,C135,C136, 

C140,C147,C149,C151,C153, 

C156,C171,C176,C178,C179, 

C182,C184,C186,C187,C192, 

C198,C199,C206,C207,C209, 

C210,C216,C222,C224,C229, 

C231,C242,C243,C248,C250, 

C274,C275,C284,C291,C292, 

C303,C305,C307,C309,C310, 

C328,C331 

1000P(1nF) 50V 10% X7R 1206 SMD AVX AVX12065C102KA 

100NF(0.1uF)16V 10% X7R 0603 EPCOS 0603X7R104K016P07 

0.01uF 2KV X7R 1825 10% SMD JOHANSON 

DIELECTRIC 

202S49W103KV4E 

C18,C158,C289,C304 1uF 25V 10% SMD A TANT SPRAGUE 293D105X9025A2T 

C19,C21,C234,C249,C251,C255,C260,C2 

94,C299,C311 

120PF 50V 5% SMD COG 1206 AVX 1206 5A 121 JTR 

C20 68UF 20V 20% SIZE D or E CAP SPRAGUE 293D686X9020E2T 





C22,C59,C63,C73,C76,C122, 

C127,C128,C129,C130,C131, 

C132,C159,C189,C197,C267, 

C61,C164,C166,C173 

Freescale 




Inc. 


10uF 10V 10% SIZE A TANT SMD CAP SPRAGUE 293D106X9010A2T 

C35,C278 100UF/10V TNT D SMT 10% SIEMENS B45196-H2107K 

C36 10NF 50V 10% NPO 1210 VITRAMON VJ1210A103KXAT 

C43 4.7uF 10v/10% Size A TNT SMD T/R AVX TAJA475K10 

C54,C53 470PF 50V 5% COG SMD 1206 AVX 12065A471JA 

C86,C124 68PF 50V 5% COG SMD 1206 SIEMENS B37871K5680J62 

C123 39NF 5% 50V 1206 SMD SIEMENS B37872K5393J62 

C138 3900PF 50V 5% COG 1210 SMD SIEMENS B37949K5392J62 

C215 10nF-2KV 0.01uF 2KV X7R 1825 10% SMD JOHANSON 

DIELECTRIC 

202S49W103KV4E 

C244,C240 10PF 50V 5% COG 1206 AVX AV12065A100JATJ 

C246 0.56uF 16V X7R 1206 10% SMD AVX 1206YC564KAT2A 

C252 5.6nF 5600pF (5.6n) X7R 0603 5% SMD AVX 06035C562JAT2A 

C269 100PF 50V 10% COG 1206-SMD AVX 12065A101KAT00J 

C271 1uF 25V 10% SMD A TANT SPRAGUE 293D105X9025A2T 

D2,D1 LL4148D ON SEMICONDUCTOR RLS4148 

D3,D4,D5,D6,D11,D12,D13 LL4004G SMD TSC LL4004G 

D7,D10 MBRD620CT ON SEMICONDUCTOR MBRD620CT 

D8 1SMC12AT3 ZENER DIODE ON SEMICONDUCTOR 1SMC12AT3 

D9 DIODE 1SMC5.OAT3 ON SEMICONDUCTOR 1SMC5.OAT3 

FR1,FR2,FR3,FR4,FR5,FR6,FR7,FR8,FR9 

,FR10,FR11, 

FR12,FR13,FR14,FR15,FR16, 

FR17,FR18,FR19 

3 Pin Ferrite FERRITE NFM60R30T222T MURATA NFM60R30T222T 

F1 POLYSWITCH SMD DEVICE RAYCHEM SMD150/33-2 (X153) 

F2 SMD260 POLYSWITCH 5.2A RAYCHEM SMD260 

IR1 TFDS6500 OBSOLETE TELEFUNKEN TFDS6500 

LD1,LD3,LD6,LD11 LED_RED KINGBRIGHT KPT-3216ID 

LD2,LD9,LD12,LD14,LD16, 

LD17,LD18,LD19,LD20,LD21, 

LD22 



LED_YELLOW KINGBRIGHT KPT-3216YD 

LD4,LD5,LD7,LD8,LD10,LD13,LD15,LD23 LED_GREEN KINGBRIGHT KPT-3216SGD 

L1,L2,L3,L4,L5,L8,L9,L10,L11,L12 BLM18AG121SN1 CHIP FERRITE BID 120 

OHM 0603 

MURATA BLM18AG121SN1 

L6 PT12133 8,2MH INDUCTOR BOURNS PT12133 

L7 ACM1110-102-2P COMMON MODE CHOCK 

COIL TO DC LIN 

TDK ACM1110-102-2P 

L13 3.3uH 3.3uH CHIP INDUCTOR T/R TDK NL322522T-3R3J 





Freescale 




Inc. 




P1,P3,P4,P10 8P RJ45 90'PC TEL JACK ERIC-CAMBRIDGE 0170-88 

P2 RS232-PORT2 9P DUAL F/90'DCON+TAIL EDA 8LE009009D306H 

P5 HFBR-5205 ATM MULTIM FIBR TRANSC Agilent (HP) HFBR-5205 

P6 CON DB37. 37P D 90'+TAIL M 7.2/8.08mm KCC DNR 37P CB SG 

P7,P21 CONN-96 96P DIN C F 90'PC+TAIL ELCO 268477096002025 

P8,P11,P14,P16,P17,P19 MICTOR38 38P LOG ANL MICTOR CON AMP 2-767004-2 

P9,P15,P20 10PIN TERM STRIP SHORT SMD 5X2 SAMTEC TSM10501-SDV AP 

P12 PWR2 2PIN PC STRGHT POW CON WIELEND BAMBERG 8113S253303253 

P13 PWR3 3PIN PC STRGHT POW CON WIELEND BAMBERG 8113S253303353 

P18 SMB Straight Jack for PCB SUHNER 82SMB-50-0-1/111 

P22 PCMCIA TOP 90'SMD CON AMP AMP 822021-5 

Q1,Q2,Q3 MMDF3N03HD ON SEMICONDUCTOR MMDF3N03HD 

RJ1,RJ2,RJ3 00-ohm on 1-2 AVX 

RJ4,R10,R11,R12,R14,R15, 

R16,R29,R72,R75,R78,R79, 

R96,R103,R104,R105,R118, 

R124,R127,R138,R139,R144, 

R145,R146,R156,R163,R165, 

R166,R167,R188,R190,R208,R212, 

R217,R218,R221,R223 

R21,R22,R23,R55,R215,0 R226,R236 

R24,R25,R26,R222,R224, 

RN1,RN2,RN3,RN4,RN7,RN8, 

RN20,RN23,RN24,RN25,RN26, 

RN27,RN28,RN29 

RN5,RN6,RN9,RN11,RN12, 

RN14,RN15,RN16,RN17,RN18, 

RN19 

0 ohm 1% 0.1W 0603 SMD T/R AVX CJ10-000-T 

10K 5% 8R 10P SMD CHIP RE NETW ROHM RS8A1002J-OR- 

MNR15EORPJ103 

22ohm 5% 4R 8P SMD CHIP RE NETW AVX CRA3A4E220JT 

RN10,RN13,RN21,RN22 0ohm 5% 4R 8P SMD CHIP RE NETW DALE CRA06S0803 000 RT 

RP1,RP2 1K single-turn TRIMMING POT BOURNS 3362P-1-102 

R1,R27,R86,R135 2K 1% 1/4W METAL 1206 ROEDERSTEIN D25002KFCS 

R2 10 OHM 1% 1/4W SMD 1206 DRALORIK D25 010RFCS 

R3,R4,R9,R58,R59,R67,R69, 

R71,R74,R76,R80,R81,R84, 

R85,R87,R88,R89,R94,R134, 

R149,R189,R196,R206,R209, 

R210,R219,R220,R228,R229, 

R230,R231,R232,R233,R234, 

R235,R237 

10K 1% 0.1W 0603 SMD T/R ROEDERSTEIN D11 010KFCS 

R5,R66 47 OHM 1% 1/4W SMD1206 ROEDERSTEIN D25047RFCS 

R6,R61 820 OHM 5% 0805 SMD BOURNS CR0805-JW-821 

R8,R7 110 OHM 5%1/4W MTL1206 AVX CR32 111J-T 





R13,R20,R35,R36,R90,R91, 

R97,R98,R99,R107,R113, 

R114,R115,R116,R121,R123, 

R125,R136,R137,R140,R148, 

R151,R152,R155,R164,R182, 

R187,R191,R193,R194,R207, 

R213,R214 

Freescale 




Inc. 




1K 1% 0603 SMD T/R DRALORIK D11 001KFCS 

R17,R18 49.9 OHM 1% SMD 1206 ROEDERSTEIN D25 49R9FCS 

R19 5,1K 5% 1/4W 1206 SMD ROEDERSTEIN D25 05K1JCS 

R28,R37,R42,R52,R65,R172,R176,R177,R 

178,R179,R180, 

R181,R183,R185,R186 

150 OHM 1% 1/4W 1206 ROEDERSTEIN D25-150RFCS 

R30,R38,R73,R122,R126,R31,R32130 100 OHM 1% 1/4W 1206 ROEDERSTEIN D25-100RFCS 

R33,R34,R49 82.5 ohm 1% 0603 SMD T/R DRALORIK D11 82R5FCS 

R39,R44,R48,R56 5.6 Ohm 1% 1206 SMD DRALORIK D25-5R6-1% 

R40,R41 33.2 1% 1/8W 1206 SMD ROEDERSTEIN D25 33R2FCS 

R45,R43 2.7ohm 1% 1206 SMD RCD MC1206 2R74FT 

R47,R46 432 OHM 1% 0603 SMD DRALORIK D11 432RFCS 

R51,R50 63.4 ohm 1% 0603 SMD T/R DRALORIK D11 63R4FCS 

R54,R53 39 OHM 1% 1/4W 1206 DRALORIK D25039RFC5 

R57 620 OHM 1% 0603 SMD DALE CRCW0603-6200F 

R60,R62,R77,R82,R92,R93, 

R106,R108,R109,R110,R111, 

R133,R147,R169,R170,R171, 

R174 

510 OHM 0603 1% SMD DALE CRCW0603-5100F 

R64,R63 90.9 OHM 1% 0603 SMD DALE CRCW0603-90R9F 

R68,R102 243 OHM 1% 1/4W 1206 ROEDERSTEIN D25243RFCS 

R70,R128,R129,R130,R131, 

R132,R192,R195,R197,R198, 

R201,R203 

22.1ohm 1% 0.1W 0603 SMD T/R ROEDERSTEIN D11 22R1FCS 

R83 294 OHM 1% 1/4W 1206 DRALORIK D25294RFCS 

R95 143 OHM 1% 1/8W 1206 ROEDERSTEIN D25 143RFCS 

R100 243 OHM 1% 1/4W 1206 ROEDERSTEIN D25243RFCS 

R101,R175 51.1ohm 1% 0.1W 0603 SMD T/ ROEDERSTEIN D11 51R1FCS 

R112,R119,R141,R142,R205 75 ohm 1% 0603 SMD T/R DRALORIK D11 075RFCS 

R117 0 ohm or 510_1% ohm 0603 

R120 143 OHM 1% 1/8W 1206 ROEDERSTEIN D25 143RFCS 

R143,R150,R153,R154,R184 47.5K 1% 0603 SMD DALE CRCW0603-4752F 

R157,R158,R159,R160 24.9 Ohm 1% 1206 SMD DRALORIK D25 24R9FCS 

R161 20M 5% 1/4W 1206 SMD ROEDERSTEIN D25 020MJCS 

R162 200K 1% 1206 SMD RES ROEDERSTEIN D25 200KFCS 

R168,R173,R200,R204,R227 100 OHM 1% 1/4W 1206 ROEDERSTEIN D25-100RFCS 





Freescale 




Inc. 




R199,R202,R211,R216 124K 1% 1/8W 1206 ROEDERSTEIN D25 124KFCS 

SK1 SEP-1162 PIEZO SPEAKER SOUNDTECH SEP-1162 

SW1,SW3,SW6, SW DIP-4/SM 4POS 8PIN SEALD DIP SW. 

SMD 

SW2 E101MD1ABE SINGLE TOGGLE SW. 0N-ON 

TO PCB 

GRAYHIL 90HBW04PR 

MORS APM5236 

SW5 ABORT-BLACK SPDT BLK PUSHBUTTON C&K KS12R22-CQE 

SW6 SRESET-RED SPDT RED PUSHBUTTON C&K KS12R23-CQE 

U1 PE-68026T SMT PULSE ENG. PE-68026 T/R 

U2 T1144 T1/E1 Transformer 3.3V PULSE ENG T1144 

U3 PE-67583 PULSE ENG PE-67583D 

U4 19.44M 3V SMD CK OSC 20PPM 7X5mm AEL CRYSTALS 4303DS-019M440000S005 

U5 MC68160 Motorola MC68160 

U6 1.544MHz. 3V TH 25PPM HS CLK OSC 

2.048MHz. 3V TH 25PPM CLK OSC. 

U7 PEB2256 E1/T1/J1 FRAMER & LINE 

INTERFACE 

U8, U48 IDTQS32X384 CMOS 20 BIT BUS 

SWITCHES 

U9 IDT77V107L25PF SINGLE ATM PHY WITH 

UTOPIA 

M-TRON 1.544MHz. M3H16FCD 

2.048MHz M3H16FCD 

INFINEON 

TECHNOLOGIES 

PEB2256-V1.2 

IDT IDTQS32X384Q1 

IDT IDT77V107L25PF 

U10 uPD98404 ATM PHY NEC - Electronics UPD98404GJ-KEU 

U11,U30 74LS244DW ON-SEMICONDUCTOR SN74LS244DW 

U12,U18 LM317MDT Regulator. Motorola LM317MDT 

U13 QS3244D HIGH SPEED CMOS 24:6 MUX/ 

DEMUX 

IDT QS3244 

U14,U15,U19,U22,U25 QS33X253 IDT QS33X253Q1 

U16 M4A3-128/64-55VC MACH M4A3-128/64- 

55VC 

U17 20Mhz - 20.0M 3V SMD CLK OSC 20PPM 

7X5mm 

U20 MPC862/6 

Lattice MACH M4A3-128/64-55VC 

AEL CRYSTALS 4303DS-020M00000S005 

U21 74LCX08 ON SEMICONDUCTOR 74LCX08D 

U23 80225 10/100BaseT PHY LSI-LOGIC NQ80225 

U24 TG22-3506ND TRANSFORMETR TG22- 

3506 

HALO TG22-3506ND 

U26 25.0M 3V SMD CLK OSC 20PPM 7X5mm AEL CRYSTALS 4303DS-025M000000S005 

U27 74AC14D ON SEMICONDUCTOR 74AC14D 

28,U40,U42,U49,U50,U51,U57 IDT74LVCH162244APF IDT IDT74LVCH162244APF TVSOP 

U29 4.0MHz 3.3V TH CLK OSC 50PPM AEL CRYSTALS AEL1203BS-4.00MHZ 





Freescale 




Inc. 




U31 DS1818-10 3.3V 

ECONORESET+PUSHBUTTON 

DALLAS DS1818R-10/T&R (SOT23) 

U32 LTC1315 DUAL PCMCIA VPP SWITCH LINEAR TECH LTC1315CG 

U33, U46 74LCX125D ON SEMICONDUCTOR 74LCX125D 

U34 MIC29500-3.3BT TO220 MICREL MIC29500-3.3BT 

U35 74AC05D ON SEMICONDUCTOR 74AC05D 

U36 M4A3-192/96-6VC Lattice M4A3-192/96-6VC 

U37 PROGRAMABLE LOGIC DEVICE-ALTERA Altera EPM3128ATC144-10 

U38 SIMM72 4MB EDO DRAM TUSHIBA 

MICRON 

MICRON 

THM3210CSG-60 

MT2D132M-6X 

MT2D132M-60X 

U39,U41 IDT74LVCH162373APF IDT IDT74LVCH162373APF TVSOP 

U43 FLASH SIMM80 55132T9DX SIMM FLASH WHITE 

MICROELECTRONICS 

SOUTHLAND MICRO 

SYSTEM 

WPF512K32-70PSC5T 



55132T9DX 

U44,U45 MAX3241ECAI 28 SSOP MAXIM MAX3241ECAI/EEAI 

U47 32.0M 3V SMD CLK OSC 20PPM 7X5mm AEL CRYSTALS 4303DS-032M000000S005 

U52 IDT74CBTLV3253PG LOW VOLTG 1-OF-4 

DUAL MUX/DEMUX 

U53 CY2309SC-1H 3.3V ZD BUFFER 16P SOIC CYPRESS 

SEMICONDUCTOR 

IDT 

IDT IDT74CBTLV3253PG 

CY2309SC-1H 

IDT 2309-1HDC 

U54 MT48LC2M32B2TG-7 SDRAM 2MX32 MICRON MT48LC2M32B2TG-8 

U55,U56,U58 IDT74LVCHR162245APF IDT IDT74LVCHR162245APF 

Y1 20MHz SMD CRYSTAL MODERN 

ENTERPRISE 

CORPORATION 

HC49/USM4 20.00MHZ 

Y2 32768HZ, 32.768KHZ CRYSTAL SMD RALTRON RSM-200-32.768KHz. 





Freescale 




Inc. 


APPENDIX A - Schematics. 1-20. 





Freescale 




Inc. 





5 

4 

3 

2 

Size Document N umber R ev 

A3 

01-SDRAM A 

Da te: Tuesday, December 17, 2002 She et 1 of 20 

1 

MPC86 6ADS 

1 Shen kar st. 

Herz elia 

Isarel 46120 

Title 

A A 

Motorol a Semiconductor Israel Ltd. 

For 8M SDRAM (Factory default) A8 not connected to BA01 RJ2 

A8 

3 

RJ2 

2 

BS1 

0 

1 

A9 

For 8M SDRAM (Factory default) A9 connected to BA1 RJ2 1-2 

3 

44 

58 

Vss 

Vss 

72 

Vss 

86 

Vss 

12 

VssQ 

32 

VssQ 

38 

46 

VssQ 

VssQ 

84 

78 

VssQ 

VssQ 

52 

VssQ 

6 

VssQ 

A29 

25 

A28 

26 

A0 

D31 

A27 

A1 

DQ0 

2 

27 

D30 

C A26 

DQ1 

4 

60 

A2 

D29 

C 

A25 

A3 

DQ2 

5 

61 

D28 

A24 

A4 

MT48LC2M32B2TG-7 

DQ3 

7 

62 

D27 

A23 

DQ4 

8 

63 

A5 

D26 

A22 

A6 

DQ5 

10 

64 

D25 

A21 

DQ6 

11 

65 

A7 

D24 

A20 

A8 

DQ7 

13 

66 

D23 

DRMWb 

A9 

(GPL0b) 

24 

D22 

A10 

A10 

21 

A10(AP) 

D21 

BS0 

NC(A11) 

22 

D20 

BS1 

23 

BA0 

D19 

BA1 

D18 

WE3b 

16 

D17 

WE2b 

DQM0 

D16 

WE1b 

28 

D15 

WE0b 

DQM2 

DQ16 

31 

59 

D14 

DQM3 

DQ17 

33 

D13 

GPL3b 

DQ18 

34 

17 

D12 

GPL2b 

WE 

DQ19 

36 

18 

D11 

EDO OEb 

CAS 

DQ20 

37 

19 

D10 

SDRMCSb 

RAS 

DQ21 

39 

20 

D9 

CS 

DQ22 

40 

D8 

BSYSCL K2 

DQ23 

42 

68 

D7 

CLK 

DQ24 

45 

D6 

SDRAMEN 

DQ25 

47 

67 

D5 

For 8M SDRAM (Factory default) A10 connected to BA0 

CKE 

DQ26 

48 

D4 

DQ27 

50 

RJ1 1-2 

D3 

A10 

DQ28 

51 

D2 

A10 

DQ29 

53 

69 D1 

B 

0 

NC3 

DQ30 

54 

D0 

B 

57 

2 BS0 

NC4 

DQ31 

56 

30 

RJ1 

NC5 

14 

NC6 

D[0:31] 

NC2 

DQ8 

74 

DQ9 

76 

DQ10 

77 

DQ11 

79 

DQ12 

80 

DQ13 

82 

DQ14 

83 

71 

DQM1 

DQ15 

85 

73 

NC1 

70 



1 


Vdd 

1 

Vdd 

15 

Vdd 

43 

Vdd 

29 

VddQ 3 

VddQ 9 

VddQ 35 

VddQ 41 

VddQ 49 

VddQ 55 

VddQ 81 

VddQ 75 

U54 

A[6 :31] 

V3 U3 

D D 

C31 C2 66 C2 56 C2 54 C2 70 C30 

C34 C26 C29 C2 61 C24 C2 57 C2 50 

C268 

C253 

0.1uF 

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.01uF 0.1uF 0.0 1uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 

V3 U3 

5 


4 

3 

2 

1

5 

4 

3 

2 

1 

Da te: Tuesday , December 17, 2002 She et 2 of 20 

IPA[ 0:7] 


A3 A 

BRb 

BGb 

ASb 

BADDR28 

BADDR29 

BADDR30 

BURS Tb 

1 

2 

3 

4 

6 

7 

8 

9 

 

RN1 

10K. 

HRESE Tb 

S RESETb 

RN26 

1K. 

DRMCS2b 

MODIN 

IR Q1b 

TMS 

TAb 

BIb 

REG Ab 

IR Q3b 

IR Q2b 

A LEA 

WAI TBb 

FCSb 

ALEA 

CE1 Ab 

CE2 Ab 

WAI TAb 

IPA0 

IPA1 

IPA2 

IPA3 

IPA4 

IPA5 

IPA6 

IPA7 

A NM Ib 

BCSRCSb 

TSb 

A 

BBb 

T EAb 

DRMCS1b 

RWb 

Motorola Semiconductor Israel Ltd. 

1 

2 

3 

4 

6 

7 

8 

9 

1 

2 

3 

4 

6 

7 

8 

9 

1 

2 

3 

4 

6 

7 

8 

9 

RN24 

10K. 

TSb 

RWb 

REGAb 

TSIZ1 

BUR STb 

GPL5Bb 

IRQ2b 

IRQ3b 

SPKR OUT 

TAb 

TEAb 

BIb 

FCSb 

BCSRCSb 

DRMCS1b 

DRMCS2b 

SDRMCSb 

CS5b 

CS6b 

CS7b 

BS0Ab 

BS1Ab 

BS2Ab 

BS3Ab 


Herz elia 

Isarel 46120 

Title 

5 

10 

5 

10 

10K. 

RN23 

5 

10 

5 

10 

1K R140 

V3 U3 

V3 U3 

V3 U3 V3 U3 

IPA4 

A[0 :31] 

RN12-1 RN12 8 22 1 

RN12-2 RN12 7 22 2 

RN12-3 RN12 6 22 3 

RN12-4 RN12 5 22 4 

A0 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10 

A11 

A12 

A13 

A14 

A15 

A16 

A17 

A18 

A19 

A20 

A21 

A22 

A23 

A24 

A25 

A26 

A27 

A28 

A29 

A30 

A31 

RN18-1 RN18 8 22 1 

RN18-2 RN18 7 22 2 

RN18-3 RN18 6 22 3 

RN18-4 RN18 5 22 4 

RN17-1 RN17 8 22 1 

RN17-2 RN17 7 22 2 

RN17-3 RN17 6 22 3 

RN17-4 RN17 5 22 4 

RN16-1 RN16 8 22 1 

RN16-2 RN16 7 22 2 

RN16-3 RN16 6 22 3 

RN16-4 RN16 4 22 5 

10pF 

C2 40 

10pF 

C2 44 

32768HZ 

0R138 

0 R139 

R162 

200K 

R1 61 

20M 

Y2 

MPC86 2/6 

CHINSb 

IRQ7b 

MPCCRS 

MPC MDIO 

MPCTXEN 

MPCCOL 

B7 

H18 

V15 

H4 

W15 

SPARE1/MII_CRS 

SPARE2/MII_MDIO 

SPARE3/MII_TX_EN 

SPARE4/MII_COL 

IRQ7 /MII_TX_CLK 

GND 

R156 0 

SYSC LK 

PD4 

B PD3 W16 B 

PD4/REJECT3/MII_TXD[2]/UTPB[7] 

U16 PD5/REJECT2/MII_TXD[3]/UTPB[6] 



G7 

1K R125 

PD3/REJECT4MII_TXD[1]/UTP_SOC 

PD8 

PD9 

PD15 

PD14 

PD13 

PD12 

PD11 

PD10 

nnet3 10 

PD7 

PD6 

PD5 

E THTX 

ETHRX 

R1 18 0 

U15 PD6/SCC4_RTS4/MII_RX_DV/UTPB[5] 

V16 PD7/SCC3_RTS3/MII_RX_ERR/UTPB[4] 

W17 

PD8/SCC4_TXD4/MII_RX_CLK/MII_MDC(mux mode) 

T15 PD9/SCC4_RXD4/MII_TXD[0]/UTP_CLK 

V17 PD10/SCC3_TXD3/MII_RXD[0]/UTP_TxEnb 

W18 PD11/SCC3_RXD3/MII_TX_ERR/UTP_RxEnb 

T16 PD12/TDMB_L1RSYNCB/MII_MDC/UTPB[3] 

R16 PD13/TDMB_L1TSYNCB/MII_RXD[1]/UTPB[2] 

V18 PD14/TDMA_L1RSYNCA/MII_RXD[2]/UTPB[1] 

U17 

PD15/TDMA_L1TSYNCA /MII_RXD[3]/UTPB[0] 

V19 

F2 

CR/IRQ3 

C4 

CS7/CE(2)B 

K2 

B3 

A3 

R3 

T5 

T4 

U3 

W2 

U4 

U5 

T6 

T3 

ALE_A/MII_TXD[1] 

CE1_A/MII_TXD[2] 

CE2_A/MII_TXD_3] 

WAIT_A/UTPBsplit_SOC 

IP_A0/UTPBsplit_MRXD[0]/MII_RXD[3] 


IP_A2/IOIS16_A/UTPBsplit_MRXD[2]/MII_RXD[1] 


IP_A4/UTPBsplit_MRXD[4]/MII_RXCLK 

IP_A5/UTPBsplit_MRXD[5]/MII_RX-ERR 

IP_A6/UTPBsplit_MRXD[6]/MII_TX-ERR 

IP_A7/UTPBsplit_MRXD[7]/MII_RXDV 

D8 

C8 

A7 

B8 

BS_A0 

BS_A1 

BS_A2 

BS_A3 

CS6/CE(1)B 

D5 CS5 

B4 CS4 

A4 CS3 

E4 CS2 

D4 CS1 

A2 CS0 

B19 

B18 

A18 

C16 

B17 

A17 

B16 

A16 

D15 

C15 

B15 

A15 

C14 

B14 

A14 

D12 

C13 

B13 

D9 

D11 

C12 

B12 

B10 

B11 

C11 

D10 

C10 

A13 

A10 

A12 

A11 

A9 

A0 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

A8 

A9 

A10 

A11 

A12 

A13 

A14 

A15 

A16 

A17 

A18 

A19 

A20 

A21 

A22 

A23 

A24 

A25 

A26 

A27 

A28 

A29 

A30 

A31 

F3 

B2 

B9 

C9 

F1 

D2 

H3 

K1 

C2 

D1 

E3 

TS 

RD/WR 

TSIZ0/REG 

TSIZ1 

BURST 

BDIP/GPL_B5 

RSV/IRQ2 

KR/RETRY/IRQ4/SPKROUT 

TA 

TEA 

BI 

C3 

CLKOUT W3 

XTAL P1 

EXTAL N1 

CLK1/TIN1/TDMA_L1RCLKA/BRGO1/PA7 M19 

SCC4_TXD4/TDMA_L1RXDA/PA8 

L17 

SCC4_RXD4/TDMA_L1TXDA/PA9 K18 

SCC3_TXD3/TDMB_L1RXDB/PA10 

J17 

SCC3_RXD3/TDMB_L1TXDB/PA11 G16 

SCC2_TXD2/PA12 F17 

SCC2_RXD2/PA13 E17 

SCC4_TXD4/SCC1_TXD1/PA14 D17 

SCC4_RXD4/SCC1_RXD1/PA15 C18 

PA8 

PA9 

PA10 

PA11 

IRDTXD 

IRDRXD 

510 R108 

ETHRCK 

ET HTCK 

PA0 

PA1 

PA2 

PA3 

PA4 

PA5 

IDT74CBTLV3253 PG 

R1 07 

OEA 

OEB 

GNDD 

PB18 

ETENA 

RSRXD2 

RSTXD2 

RSD TR2b 

RSD TR1b 

RSRXD1 

RSTXD1 

PB26 

PB27 

PB28 

PB29 

PB30 

PB31 

NOTE1: 

IN EACH SCC FOR ETHERNET 10BT THE SIGNALS: 

RTSx=TEN Ax 

CDx=REN Ax 

CTSx=CLS Nx 

NOTE2: 

IF ATM MUX IS USED The ATM US E PORT-D 

AND MII USE IP_A 

NOTE3: 

IF ATM SPLIT IS USED The ATM USE POR T-D & IP_A 

IN THIS CASE MII IS NO T USED 

CLK8/TOUT4/TDMB_L1TCLKB/PA0 U19 

CLK7/TIN4/BRGO4/PA1 T19 

CLK6/TOUT3/TDMB_L1RCLKB/BRGCLK2/PA2 R18 

CLK5/TIN3/BRGOUT3/PA3 P17 

CLK4/TOUT2/PA4 P19 

CLK3/TIN2/TDMA_L1TCLKA/BRGOUT2/PA5 N18 

CLK2/TOUT1/BRGCLK1/PA6 M17 

8 

15 

AT3 

VF0 

VF1 

VF2 

WAIT Bb 

RE SETA 

POEAb 

MOD CK2 

MOD CK1 

S1 

0.1uF 

PB16 

PB15/UTP_TxClav/BRGO3 

AT1 

C N16 

1 

1K 

PB17 

PB16/UTP_RXADDR[0]/L1RQA/L1ST4/SCC4_RTS4 

ALE_B/DSCK/AT1 

J1 

P18 

AT2 

C 

MODIN 

SEL866 

2 S0 

14 

C2 47 

PB14 

PB15 

ND conne ct 

o V SSSYN 

V3 U3 

TM124 

nnet2 43 

I0B 

I1B 

I2B 

I3B 

TMS 

T RSTb 

5.6nF 

0.56uF 

DSDI 

DSCK 

DSDO 

C2 52 

C2 46 

0.1uF 

C2 45 

nnet2 42 

6 

5 

4 

3 

10 

11 

12 

13 

nnet2 46 

TM123 

RRN14-1 N14 1 22 8 DRMWb 

U7C6 2 22 7 RN14-2 R N14 EDO OEb 

U7 B53 

22 6 RN14-3 R N14 GPL2b 

U7C5 4 22 5 RN14-4 R N14 GPL3b 

GPL4Ab 

GPL4Bb 

GPL5Ab 

VFL S0 

VFL S1 

AT0 

nnet2 45 

U52 

I0A 

I1A 

I2A 

I3A 

3V3 

ZA 7 

ZB 9 

T1 

VDDSYN 

H17 

TDI/DSDI 

H16 

G17 

TCK/DSCK 

TDO/DSDO 

G18 

TMS 

G19 

TRST 

U18 

R17 

PB14/UTP_RXADDR[2]/RSTRT1 

N17 

PB17/UTP_RXADDR[1]/L1RQB/L1ST3/SCC3_RTS3 

PB18/UTP_RXADDR[4]/SCC2_RTS2/L1ST2 

N19 

PB19/SCC1_RTS1/L1ST1 

L16 

PB20/UTP_TXADDR[0]/SMRXD2/TDMA_L1CLKOA 

K16 

PB21/UPT_TXADDR[1]/SMTXD2/TDMB_L1CLKOB 

L19 

PB22/UTP_TXADDR[4]/SMSYN2/SDACK2 

K17 

PB23/UTP_TXADR[2]/SMSYN1/SDACK1 

J18 

PB24/UTP_TXADDR[3]/SMRXD1 

J16 

PB25/UTP_RXADDR[3]/SMTXD1 

F19 

PB26/I2CSCL/BRGO2 

E19 

PB27/I2CSDA/BRGO1 

D19 

PB28/SPIMISO/BRGO4 

E16 

C19 

PB29/SPIMOSI 

PB30/RSTRT2/SPICLK 

C17 

PB31/SPISEL/REJECT1 

VSSSYN 

U1 VSSSYN1 

V1 

T2 

XFC 

16 

C2 31 

0.0 1uF 

0.1uF 

C2 32 

V3 U3 

U7C7 

U7 A6 

U7B 66 

U7A 55 

1 22 8 RN15-1 R N15 WE0b 

2 22 7 RN15-2 R N15 WE1b 

3 22 6 RN15-3 R N15 WE2b 

4 22 5 RN15-4 R N15 WE3b 

Jumper 

2 

V3P 

V3P 

U20B 

2 

1 

JP4 

C267 + 

10uF 

0.1uF 

C2 64 

D0 W14 

D1 W12 

D2 W11 

D3 W10 

D4 W13 

D5 W9 

D6 W7 

D7 W6 

D8 U13 

D9 T11 

D10 V11 

D11 U11 

D12 T13 

D13 V13 

D14 V10 

D15 T10 

D16 U10 

D17 T12 

D18 V9 

D19 U9 

D20 V8 

D21 U8 

D22 T9 

D23 U12 

D24 V7 

D25 T8 

D26 U7 

D27 V12 

D28 V6 

D29 W5 

D30 U6 

D31 T7 

IRQ0 V14 

IRQ1 U14 

DP0/IRQ3 V3 

DP1/IRQ4 V5 

DP2/IRQ5 W4 

DP3/IRQ6 V4 

FRZ/IRQ6 G3 

SCC4_CD4/TDMA_L1RSYNCA/PC4 T17 

SCC4_CTS4/TDMA_L1TSYNCA/SDACK1/PC5 T18 

SCC3_CD3/TDMB_L1RSYNCB/PC6 R19 

SCC3_CTS3/TDMB_L1TSYNCB/SDACK2/PC7 M16 

SCC2_CD2/TGATE2/PC8 M18 

L18 

SCC2_CTS2/PC9 

SCC1_CD1/TGATE1/PC10 K19 

SCC1_CTS1/PC11 

J19 

DREQ1/SCC2_RTS2/L1ST2/PC14 D18 

DREQ0/SCC1_RTS1/L1ST1/UTP_RxClav/PC15 D16 

L1RQB/L1ST3/SCC3_RTS3/PC13 E18 

L1RQA/L1ST4/SCC4_RTS4/PC12 F18 

GPL_A3/GPL_B3/CS3 C5 

UPWAITB/GPL_B4 B1 

UPWAITA/GPL_A4 C1 

GPL_A5 D3 

IP_B0/IWP0/VFLS0 H2 

IP_B1/IWP1/VFLS1 

J3 

IP_B2/IOIS16_B/AT2 J2 

IP_B3/IWP2/VF2 G1 

IP_B4/LWP0/VF0 G2 

IP_B6/DSDI/AT0 

IP_B5/LWP1/VF1 

J4 

K3 

IP_B7/PTR/AT3 H1 

WAIT_B R4 

OP0/UTPBsplit_RXCLK/MII_TXD[0] L4 

OP1 

L2 

OP3/MODCK2/DSDO M4 

OP2/MODCK1/STS L1 


510 R109 

CLK4IN_EXTCLK N2 

GPL_A0/GPL_B0 D7 

OE/GPL_A1/GPL_B1 C6 

GPL_A2/GPL_B2/CS2 B5 

R1 

KAPWR 

PORESET R2 

RSTCONF P3 

HRESET N4 

SRESET P2 

TEXP N3 

BADDR30/REG K4 

BADDR29 M2 

BADDR28 M3 

AS L3 

WE0/BS_B0/IORD C7 

WE1/BS_B1/IOWR A6 

WE2/BS_B2/PCOE B6 

WE3/BS_B3/PCWE A5 

BR G4 

BG E2 

BB E1 

3 

2 

3 

1 

NMIb 

IRQ1b 

DP0 

DP1 

DP2 

DP3 

FRZ 

V3P 

nnet2 1 36 L6 2 

8.2 mH 

VDDSYN 

4 

5 

P18 

SMB 

1 nnet2 40 

RJ3 

0 

2 

D0 

D1 

D2 

D3 

D4 

D5 

D6 

D7 

D8 

D9 

D10 

D11 

D12 

D13 

D14 

D15 

D16 

D17 

D18 

D19 

D20 

D21 

D22 

D23 

D24 

D25 

D26 

D27 

D28 

D29 

D30 

D31 

PC4 

PC5 

PC6 

PC7 

PC8 

PC9 

ERENA 

ECLSN 

PC12 

PC13 

PC14 

RXCLAV 

RPORIb 

RSTCNFb 

SRESETb 

HRES ETb 

TEXP 

MODIN 

D D 

1 

BADDR28 

BADDR29 

BADDR30 

ASb 

BRb 

BGb 

BBb 

74LCX08 

4 

5 

D[0:31] 

6 

nnet2 39 

4 

U21B 

nnet2 37 

R1 88 

0 

0.1uF 

C2 76 

4/10M hz 

vdd 

CLK OUT 5 

C2 75 gnd 

0.01uF U29 

8 

74LCX 08 

2 

3 

EX TCLK 

onne ct it through PS 

V3 U3 

5 

nnet2 38 

1 

U21A 


4 

3 

2 

1

U28 

WE3b WE3b 47 

nnet1 46 0 RN22-1 BWE3b 

WE2b WE2b 

D0 

Q0 

2 

1 8 

46 


WE1b WE1b 

D1 

Q1 

3 

2 7 

44 

nnet1 48 

BWE1b 

WE0b WE0b 

D2 

Q2 

5 

3 0 6 RN22-3 

43 


BS3Ab B S3Ab 

D3 

Q3 

6 

4 5 

41 

nnet1 50 0 RN21-1 BBSA3b 

BS2Ab B S2Ab 

D4 

Q4 

8 

1 8 

40 


BS1Ab B S1Ab 

D5 

Q5 

9 

2 7 

38 


BS0Ab B S0Ab 

D6 

Q6 

11 

3 6 

37 


nnet1 45 D7 

Q7 

12 

4 5 

48 

V3 U3 

OE2 

1 

OE1 

A A 


GPL2b 

36 

BGPL2b 

U33A 

GPL3b 

D8 

Q8 

13 

35 

BGPL3b 

D9 

Q9 

14 

VCC-14 


33 

D10 

Q10 

16 

74LC X125D 

Herz elia 

32 

D11 

Q11 

17 

Isarel 46120 

30 

SPKRO UT 2 3 BSPKOUT 

1K 

D12 

Q12 

19 

29 

Title 

R1 87 

27 

D13 

Q13 

20 

D14 

Q14 

22 

MPC852TADS 

26 

D15 

Q15 

23 

24 

GND 7 


25 

OE4 

OE3 

A3 

PCCENb 

03-BUFF ERS A 


5 

4 

3 

2 

1 

0.1uF C273 

0.1uF C279 

0.1uF C281 

0.1uF C280 

1 

IDT74LVCH1 62244APA 

0.1uF C238 

0.1uF C230 

0.1uF C239 

0.1uF C233 

0.1uF C221 

0.1uF C212 

0.1uF C204 

0.1uF C205 

V3U3 

(7,18,31,42) 

GND 

(4,10,1 5,21,28,34,39,45) 

V3 U3 V3 U3 

0.1uF C190 

0.1uF C193 

0.1uF C191 

0.1uF C175 

R1 24 0 

DRMA8 

1K 

R113 

BA[6: 31] 

R137 

V3.3 7,18,31,42 

GND 4 ,10,15,21,28,34,39,45 

U50B 

A16 

B A16 

A17 

B A17 

A6 

BA6 

A18 

B A18 

A7 

BA7 A19 

B A19 

DRMWb 

nnet1 54 

BDRMWb 

A21 

A20 

B A20 

TEAb 

BTEAb 

BTEAb 

POEAb 

BPOEAb 

A21 

B A21 

TSb 

B TSb 

BBALEA 

BALEA 

A22 

B A22 

RWb 

BRW1b 

EDO OEb 

BEDO OEb 

A23 

B A23 

BRW2b 

BRW2b 

nnet1 42 

nnet1 43 

A24 

B A24 

A29 

nnet1 55 

DRMA0 

nnet1 44 SN74LV C32244GKER 

A25 

B A25 

A28 

nnet1 56 3 0 6 RN13-3 DRMA1 

A8 

J5 

BA8 

A26 

B A26 

A27 

nnet1 57 

DRMA2 

A9 

J6 

1A1 

1Y1 

J2 

BA9 

A27 

B A27 

A26 

nnet1 58 

DRMA3 

A10 

1A2 

1Y2 

J1 

K5 

B A10 

A28 

B A28 

A25 

nnet1 59 

DRMA4 

A11 

1A3 

1Y3 

K6 

B A11 

A29 

B A29 

A24 

nnet1 60 

DRMA5 

A12 

1A4 

L5 

B A12 

A30 

B A30 

A23 

nnet1 61 

DRMA6 

A13 

2A1 

L6 

B A13 

A31 

B A31 

A22 

nnet1 62 1 0 8 RN10-1 DRMA7 

V3 U3 

A14 

2A2 

M5 

B A14 

B A15 

2A3 

B A15 

B 

M6 

2A4 

J3 

1OE 

J4 

2OE 

DRMA[0:8] 

K2 

1Y4 K1 

2Y1 

L2 

2Y2 

L1 

2Y3 M2 

2Y4 M1 

N5 

3A1 

3Y1 

N6 

3A2 

P5 

3A3 

P6 

3A4 

R5 

R6 

4A1 

4A2 

T6 

4A3 

T5 

4A4 

T4 

3OE 

T3 

4OE 

N2 

3Y2 N1 

3Y3 P2 

3Y4 P1 

4Y1 R2 

4Y2 R1 

4Y3 T1 

4Y4 T2 

U50A 

U51 

TM67 

47 

D0 

Q0 

2 

46 

44 

D1 

Q1 

3 

D2 

Q2 

5 

43 

R15 0 

D3 

Q3 

6 

41 

D4 

Q4 

8 

40 

D5 

Q5 

9 

38 

37 

D6 

Q6 

11 

D7 

Q7 

12 

48 

OE2 

1 

OE1 

SN74LVC 32244GKER 

36 

4 0 5 RN13-4 

D8 

Q8 

13 

A5 

1A1 

1Y1 

35 

D9 

Q9 

14 

A6 

1A2 

33 

2 0 7 RN13-2 

32 

D10 

Q10 

16 

B5 

1 0 8 RN13-1 

D11 

Q11 

17 

B6 

1A3 

1A4 

30 

4 0 5 RN10-4 

D12 

Q12 

19 

C5 

2A1 

29 

D13 

Q13 

20 

C6 

0 RN10-3 

2A2 

3 6 

27 

2 0 7 RN10-2 

D14 

Q14 

22 

D5 

2A3 

26 

D15 

Q15 

23 

D6 

2A4 

24 

OE4 

A3 

1OE 

25 

OE3 

A4 

2OE 

1K 

1K R155 

A2 

1Y2 A1 

1Y3 B2 

1Y4 B1 

2Y1 C2 

2Y2 C1 

2Y3 D2 

2Y4 D1 

E5 

3A1 

3Y1 

E6 

F5 

3A2 

3A3 

F6 

3A4 

G5 

4A1 

G6 

4A2 

H6 

H5 

4A3 

4A4 

H4 

3OE 

H3 

4OE 

E2 

3Y2 E1 

3Y3 F2 

3Y4 F1 

4Y1 G2 

4Y2 G1 

4Y3 H1 

4Y4 H2 



IDT74LVCH 162244APA 


C A[6 :31] 

C 

BD[0:31] 

LBUFENb 

UBUFENb 

EXTOLI[0:3] 

V3 U3 

D0 

BD0 

D16 

BD16 

D1 

1A1 BD1 

D17 

BD17 

EXT OLI0 

D2 

BD2 

D18 

BD18 

EXT OLI1 

D3 

BD3 

D19 

BD19 

EXT OLI2 

D4 

BD4 

D20 

BD20 

EXT OLI3 

D5 

BD5 

D21 

BD21 

D D6 

BD6 

D22 

BD22 

D 

D7 

BD7 

D23 

BD23 

S/W OPTION S SELECTOR 

D8 

BD8 

D24 

BD24 

GND 

D9 

BD9 

D25 

BD25 

D10 

BD10 

D26 

BD26 

D11 

BD11 

D27 

BD27 

D12 

BD12 

D28 

BD28 

D13 

BD13 

D29 

BD29 

D14 

BD14 

D30 

BD30 

D15 

BD15 

D31 

BD31 

A5 

1A2 A6 

1A3 B5 

1A4 B6 

1A5 C5 

1A6 C6 

1A7 D5 

1A8 D6 

DIR1 A3 

OE1 A4 

A2 

1B1 

A1 

1B2 

B2 

B1 

1B3 

1B4 

C2 

C1 

1B5 

1B6 

D2 

1B7 

D1 

1B8 

2A1 E5 

2A2 E6 

2A3 F5 

2A4 F6 

2A5 G5 

2A6 G6 

2A7 H6 

2A8 H5 

DIR2 H3 

OE2 H4 

SW7 

1A1 

J5 

1A2 

J6 

1 

8 

2 

7 

1A3 

3 

6 

4 

5 

SW DIP-4/ SM 

E2 

2B1 

E1 

F2 

2B2 

2B3 

F1 

2B4 

G2 

2B5 

G1 

2B6 

H1 

H2 

2B7 

2B8 

K5 

1A4 K6 

1A5 

L5 

1A6 

L6 

1A7 M5 

1A8 M6 

J2 

1B1 

J1 

1B2 

K2 

K1 

1B3 

1B4 

L2 

L1 

1B5 

1B6 

M2 

1B7 

M1 

1B8 

DIR1 

J3 

OE1 

J4 

2A1 N5 

2A2 N6 

2A3 P5 

2A4 P6 

2A5 R5 

2A6 R6 

2A7 T6 

2A8 T5 

DIR2 T3 

OE2 T4 

N2 

2B1 

N1 

P2 

2B2 

2B3 

P1 

2B4 

R2 

2B5 

R1 

2B6 

T1 

T2 

2B7 

2B8 

0.1uF C28 

0.1uF C33 

0.1uF C32 

0.1uF C27 



0.1uF C263 

0.1uF C259 

0.1uF C258 

0.1uF C262 

U55A 

U55B 

V3 U3 

3V3 

D[0:31] 

5 


4 

3 

2 

1

5 

4 

3 

2 

1 



A3 

04-LOGIC ANALYZER A 

MPC8 66ADS 


Herz elia 

Isarel 46120 

Title 

A Motorola Semiconductor Israel Ltd. 

A 

B B 



C C 


A[0: 31] 

D[0:31] 

IPA[ 0:7] 

A11 

A12 

A13 

A14 

A15 

29 

31 

33 

35 

37 

D5 

D4 

D3 

D2 

D1 

D0 

A27 

D11 D5 D5 

30 

29 

32 A28 

D12 31 

D4 D4 

34 A29 

D13 D3 D3 

33 

36 A30 

D14 D2 D2 

35 

38 A31 

D15 D1 D1 

37 

D0. 

D0 

D27 

BRb 

D6 

30 

27 

32 D28 

BIb 29 

D5 

D29 

GPL5Bb 

D4 

34 

31 

36 D30 

BURS Tb 

D3 

33 

38 D31 

RWb 

D2 

35 

TSb 

D1 

37 

D0. 

BS2Ab 

BS3Ab 

WE0b 

WE1b 

WE2b 

WE3b 

SRESETb 

WAIT Bb 

WAIT Ab 

GPL4Ab 

GPL4Bb 

CE1 Ab 

IPA2 

IPA3 

IPA4 

IPA5 

IPA6 

IPA7 

ECLSN 

PC12 

PC13 

PC14 

RXCLAV 

PA11 

IRDTXD 

IRDRXD 

E THTX 

ETHRX 

PD13 

PD14 

PD15 

PB14 

PB15 

PB27 

PB28 

PB29 

PB30 

PB31 

A8 23 

A24 

D8 

D24 

AT3 

CS7b 

RPORIb 

SPKRO UT 

PC8 

PA8 

RSRXD1 

A9 D7 D7 

24 

23 

A25 

D9 D7 D7 

24 

21 

D25 

D BGb 

D8 D8 

22 

21 

BS0Ab 

RSTCNFb 

D8 D8 

22 

23 

PD10 

IPA0 

PC9 

D7 D7 

24 

23 

25 

PA9 

D7 D7 

24 

PD11 

RSTXD1 D 

A10 27 

D6 D6 

26 

25 

28 A26 

D10 27 

D6 D6 

26 

23 

28 D26 

BBb 25 

D7 D7 

24 

23 

25 

26 BS1Ab 

HRESE Tb 

D7 

25 

IPA1 

ERENA 

D6 

PA10 

D6 

PD12 27 

D6 

26 

27 

D6 

26 

25 

D7 

24 

26 

28 

28 PB26 

. 

. 

D5 

D4 

D3 

D2 

D1 

D0 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

28 

30 

32 

34 

36 

38 

27 

29 

31 

33 

35 

37 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

. 

. 

. 

. 

D5 

D4 

D3 

D2 

D1 

D0 

D5 

D4 

D3 

D2 

D1 

D0 

29 

31 

33 

35 

37 

D5 

D4 

D3 

D2 

D1 

D0 

30 

32 

34 

36 

38 

29 

31 

33 

35 

37 

. 

P14 MICTOR 38 

EVEN ODD 

1 

VDC SCL 

2 

3 

BSYSCL K4 

GND SDA 

5 

MOD CK1 

A0 7 

CLK 

A16 

A1 D15 

9 

A17 

A2 11 

D14. 

A18 

A3 D13 

13 

A19 

A4 D12 

15 

A20 

A5 17 

D11 

A21 

A6 D10 

19 

A22 

A7 21 

D9. 

A23 

D8 

4 

CLK 6 

D15 

8 

D14 

10 

D13 

12 

D12 

14 

D11 

16 

D10 

18 

D9 

20 

D8 

22 

REG Ab 

D0 

D1 

D2 

D3 

D4 

D5 

D6 

D7 

TEAb 

FCSb 

BCSRCSb 

DRMCS1b 

DRMCS2b 

SDRMCSb 

CS5b 

CS6b 

AT1 

TE XP 

RE SETA 

POEAb 

MOD CK1 

MOD CK2 

EXT CLK 

1 

3 

DRMWb 5 

GPL5Ab 7 

GPL3b 9 

GPL2b 11 

EDO OEb13 

PC4 15 

PC5 17 

PC6 19 

PC7 21 

IRQ1b 

NMIb 

PD3 

PD4 

PD5 

PD6 

PD7 

PD8 

PD9 

. 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

5 

The Mictors Connections is suitable to HP DISasembler Product 

P16 MICTOR 38 4 

EVEN ODD 

VDC . SCL 

2 

GND SDA 

TSIZ1 

CLK 

D16 

TAb 

D15 

D17 

VFLS0 

D14. 

D18 

VFLS1 

D13 

D19 

AT2 

D12 

D20 

VF2 

D11 

D21 

VF0 

D10 

D22 

VF1 

D9. 

D23 

AT0 

D8 

4 

CLK 6 

P19 MICTO R38 

EVEN ODD 

1 

VDC . SCL 

2 

3 

D15 

8 

5 

GND SDA 

CLK 

D14 

10 

7 

D13 

12 

9 

D15 

D14 

D12 

14 

11 

D13. 

D11 

16 

13 

D10 

18 

15 

D12 

D11 

D9 

20 

17 

D8 

22 

19 

D10 

D9 

4 

CLK 6 

D15 

8 

D14 

10 

D13 

12 

D12 

14 

D11 

16 

D10 

18 

D9 

20 

. 

. 

. 

. 

. 

. 

. 

D6 

D5 

D4 

D3 

D2 

D1 

D0 

28 

30 

32 

34 

36 

38 

P8 MICTOR 38 

EVEN ODD 

VDC SCL 

2 

GND SDA 

IRQ7b 

CLK 

PB16 

D15 

PB17 

D14 

PB18 

D13 

ETENA 

D12 

RSRXD2 

D11 

RSTXD2 

D10 

RSD TR2b 

D9 

RSD TR1b 

D8 

4 

CLK 6 

D15 

8 

D14 

10 

D13 

12 

D12 

14 

D11 

16 

D10 

18 

D9 

20 

D8 

22 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 

21 

3 

2 

P11 MICTOR 38 

EVEN ODD 

VDC SCL 

2 

GND SDA 

CE2Ab 

CLK 

PA0 

D15 

PA1 

D14 

PA2 

D13 

PA3 

D12 

PA4 

D11 

PA5 

D10 

ETHRCK 

D9 

ET HTCK 

D8 

4 

CLK 6 

D15 

8 

D14 

10 

D13 

12 

D12 

14 

D11 

16 

D10 

18 

D9 

20 

D8 

22 

. 

. 

. 

. 

. 

D5 

D4 

D3 

D2 

D1 

D0 

30 

32 

34 

36 

38 

1 

3 

5 

7 

9 

11 

13 

15 

17 

19 


P17 MICTO R38 

EVEN ODD 

VDC SCL 

2 

GND SDA 

ALEA 

CLK 

IRQ2b 

D15 

IRQ3b 

D14 

DP0 

D13 

DP1 

D12 

DP2 

D11 

DP3 

D10 

FRZ 

D9 

4 

CLK 6 

D15 

8 

D14 

10 

D13 

12 

D12 

14 

D11 

16 

D10 

18 

D9 

20 

1 

.

5 

4 

3 

2 


A3 

05-FLASH&DRAM A 


1 

BD7 TM122 

BD6 TM83 

BD5 TM121 

BD4 TM82 

BD3 TM120 

BD2 TM81 

BD1 TM119 

BD0 TM80 

BD15 TM118 

BD14 TM79 

BD13 TM117 

BD12 TM78 

BD11 TM116 

BD10 TM77 

BD9 TM115 

BD8 TM114 

BD23 TM89 

BD22 TM88 

BD21 TM90 

BD20 TM87 

BD19 TM91 

BD18 TM61 

BD17 TM92 

BD16 TM62 

A BD31 TM93 

A 

BD30 TM63 

BD29 TM94 


BD28 TM64 

BD27 TM95 

1 Shenka r street 

BD26 TM98 

Herzeli a 46120 

BD25 TM68 

Israel 

BD24 TM99 

Title 

MPC86 6ADS 

B B 

BD[0:31] 



1 

GND1 

GND2 

25 GND3 

54 GND4 

80 

DRAM 

FLASH 

72 

GND3 

GND2 

39 GND1 

1 


C3 08 C3 10 C3 05 

C3 29 C3 28 

0.01uF 0.0 1uF 

BA[7 :31] 0.0 1uF VCC 

DRMA[0:8] 

0.1uF 

0.1uF 

DRMA9 

C3 06 C3 09 C3 07 

C3 30 C3 31 

0.01uF 0.0 1uF 

B A29 TM113 

0.0 1uF 

DRMA10 

U38 

0.1uF 

D B A28 TM75 

0.1uF 

VCC VCC VCC VCC D 

B A27 TM112 

U42 

B A26 TM111 

B A25 TM110 

TM40 DRMA0 

DRMA0 12 

B A24 TM36 

B A29 52 

TM41 DRMA1 

DRMA1 13 

A0 

B A23 TM34 

B A28 

A0 

DRMA2 

DRMA2 

A1 

51 

TM52 

14 

B A22 TM74 

B A27 

A1 

DRMA3 

DRMA3 

A2 

50 FLASH SIMM80 

TM42 

15 

BD31 

B A21 

B A26 

DRMA4 

DRMA4 

DQ0 

2 

TM30 

49 

A2 

TM53 

A3 

BD30 

B A20 TM109 

B A25 

A3 

16 

TM43 DRMA5 

DRMA5 

A4 DQ1 

4 

48 

17 

BD29 

B A19 

B A24 

BD7 

DRMA6 

DRMA6 

DQ2 

6 

R2 28 

TM108 

A4 

47 

A5 

BD28 

10K 

B A18 TM107 

B A23 

DQ0 

70 

TM54 

18 

BD6 

DRMA7 

DRMA7 

DQ3 

8 

10K 

A5 

A6 

46 

BD27 

R2 20 

B A17 

B A22 

DQ1 

69 

TM59 

28 

BD5 

DRMA8 

DRMA8 

DQ4 

20 

TM105 

A6 

A7 

45 

BD26 

B A16 

B A21 

DQ2 

68 

TM60 

31 

BD4 

DRMA9 

DRMA9 

DQ5 

22 

TM106 

44 

A7 

A8 

BD25 

B A15 TM104 

B A20 

DQ3 

67 

TM44 

A8 

32 

BD3 

A9 DQ6 

24 

43 

BD24 

BD24 

B A14 

B A19 

DQ4 

66 

BD2 

DQ7 

26 

TM73 

A9 

42 

11 

DP3 DP3 

B A13 

B A18 

BD1 

TM55 DRMA10 

DRMA10 

DQ8 

36 

TM103 

A10 DQ5 

65 

NC1 

41 

19 

B A12 TM72 

B A17 

A11 DQ6 

64 

BD0 

RAS 1b 

NC2 

40 

BD8 

BD8 

B A11 TM102 

B A16 

DQ7 

63 

TM57 

29 

TM50RAS 

2b 

DQ9 

49 

39 

A12 

NC3 

BD9 

R2 19 

B A10 TM71 

B A15 

A13 

BD15 

TM46RAS1DDb 

DQ10 

51 

38 

BD10 

10K 

BA9 

B A14 

DQ8 

62 

BD14 

RAS 1b 

DQ11 

53 

TM101 

A14 

37 

BD11 

BA8 

B A13 

DQ9 

61 

44 

BD13 

RAS 2b 

DQ12 

55 

TM70 

A15 

RAS0 

36 

BD12 

BA7 TM100 

B A12 

A16 DQ10 

60 

45 

BD12 

RAS1DDb 

NC4 DQ13 

57 

35 

BD13 

B A11 

DQ11 

59 

34 

BD11 

RAS2DDb 

DQ14 

61 

34 

A17 

RAS2 

BD14 

B A10 

A18 DQ12 

58 

33 

BD10 

NC5 DQ15 

63 

33 

BD15 

BA9 

DQ13 

57 

TM45 

BD9 

BBSA3b 

BBSA3b 

DQ16 

65 

32 

A19 

DP1 DP1 

BA8 

DQ14 

56 

TM47 

A20 

40 

BD8 

BBSA1b 

BBSA1b 

CAS0 DQ17 

37 

31 

BA7 

DQ15 

55 

TM49 

A21 

43 

BBSA2b 

BBSA2b 

CAS1 

30 

TM48 

BD16 

BD16 

A22 

41 

BD23 

TM56 BBSA0b 

BBSA0b 

CAS2 DQ18 

3 

42 

BD17 

TM97 FCS1b 

FCS1b 

DQ16 

8 

BD22 

CAS3 DQ19 

5 

24 

BD18 

C TM66 FCS2b 

FCS2b 

DQ17 

9 

BD21 

BDRMWb 

DQ20 

7 

23 

CE0 

47 

BD19 

R2 29 

C 

TM96 FCS3b 

FCS3b 

CE1 DQ18 

10 

BD20 

TM51 

WE DQ21 

9 

22 

BD20 

10K 

TM65 FCS4b 

FCS4b 

CE2 DQ19 

11 

BD19 

DQ22 

21 

21 

BD21 

CE3 DQ20 

12 

BD18 

BEDO OEb 

DQ23 

23 

46 

BD22 

TM84 BWE0b 

BWE0b 

DQ21 

13 

BD17 

TM58 

NC6 DQ24 

25 

5 

48 

BD23 

BWE1b 

BWE1b 

DQ22 

14 

BD16 

NC7 DQ25 

27 

TM86 

6 

WE0 

71 

DP2 DP2 

BWE2b 

BWE2b 

DQ23 

15 

NC9 DQ26 

35 

TM69 

WE1 

29 

TM76 BWE3b 

BWE3b 

WE2 

53 

BD31 

DRMPD[1:4] 

66 

BD0 

BD0 

TM85 

WE3 DQ24 

16 

BD30 

DRMPD1 

PD_EDO DQ27 

50 

67 

BD1 

FOEb 

DQ25 

17 

BD29 

DRMPD2 

PD1 DQ28 

52 

4 

68 

BD2 

FPD[1:7] 

OE DQ26 

18 

BD28 

DRMPD3 

PD2 DQ29 

54 

69 

BD3 

FPD1 

DQ27 

19 

BD27 

DRMPD4 

PD3 DQ30 

56 

73 

70 

BD4 

FPD2 

PD1 DQ28 

20 

BD26 

PD4 DQ31 

58 

74 

BD5 

FPD3 

PD2 DQ29 

26 

BD25 

DQ32 

60 

75 

BD6 

FPD4 

PD3 DQ30 

27 

BD24 

DQ33 

62 

76 

BD7 

FPD5 

PD4 DQ31 

28 

DQ34 

64 

77 

DP0 DP0 

FPD6 

PD5 

DQ35 

38 

78 

FPD7 

PD6 

79 

PD7 

7 

NC1 

72 

VCC2 

VCC1 

2 

71 

VPP2 

VPP1 

3 

VCC3 

59 

VCC2 

30 

VCC1 

10 

VPP 

DRMPWR 

DRMPWR 

5 


4 

3 

2 

1

5 

4 

3 

2 

1 



A3 

06-ATM25 A 

MPC8 66ADS 


Herz elia 

Isarel 46120 

Title 


A 

ALEA TM25 

CS ATM25b 

RDATM25b 

WRATM 25b 

IRQ3b 

RS T25b 

MP11 

MP12 

MP13 

AD0 

AD1 

AD2 

AD3 

AD4 

AD5 

AD6 

AD7 

MP8 

IDT77V107 L25PF 

2 

2K 

3 OUTCLK 

32Mhz gnd 

0.0 1uF 

0.1uF 

R86 

59 

60 

61 

62 

64 

65 

66 

67 

AD0 

AD1 

AD2 

AD3 

AD4 

AD5 

AD6 

AD7 

58 

57 

56 

55 

53 

54 

ALE 

CS 

RD 

WR 

INT 

RST 

0 

R10 

C12 

C13 

ATMTX AD1 

M1 

B 74LCX 125D 

e vdd U46 

B 

1 

4 

U45A 

V3 U3 

20 

TxParity 

nnet3 02 

RSTXD2 

2 3 

DA 75 

SE 

M0 

100 

99 

76 

R11 

0 

1 

PB15 

ATMTX ENB 

ATMTX SOC 

ATMTX CLK 

ATMTXD0 

ATMTXD1 

ATMTXD2 

ATMTXD3 

ATMTXD4 

ATMTXD5 

ATMTXD6 

ATMTXD7 

C 

V3 U3 

MP7 

JP2 

BRIDGE 

13 

MP9 

MP10 

LED_GR EEN 

A 

LD8 

V3 U3 

MP6 

RSRXD2 

24 

21 

22 

27 

7 

8 

9 

10 

11 

12 

13 

14 

TxClav 

TxEn 

TxSoc 

TxCLK 

TXD0 

TXD1 

TXD2 

TXD3 

TXD4 

TXD5 

TXD6 

TXD7 

RXD- 

74LCX 125D 

12 11 

84 

3.3uH 

2 

Chassis 

63.4 

R41 

33.2 

C54 

U45D 

R51 

470pF 

L13 

PE-6 7583 

ATMTXA D0 

15 

16 

17 

18 

19 

TXADDR0 

TXADDR1 

TXADDR2 

TXADDR3 

TXADDR4 

1 

10K 

0.1uF 

C68 

R59 

RxParity 

16 

15 

RX+ 

RX- 

13 

MID3 

12 

AGND2 

MID4 

14 

11 

NC2 

RJ_RX+ 

RJ_RX- 

38 

10 

9 

ATMRXD7 

RXD6 

C 39 

82.5 63.4 R58 

C53 

ATMRXAD0 

RXD7 

C 

10K 

8 

BLUE 

ORANGE 

7 BLACK 



OSC 79 

510 

R93 

RCO 69 

RPLI 

48 

RXLED 51 

RXREF 2 

CHASSI 

CHASSI 

RJ4 5_Eth 


13 

14 

33 

RXADDR0 

RXADDR1 

34 RXADDR2 

35 RXADDR3 

36 RXADDR4 

37 

30 

RxClav 

29 

31 

RxEn 

RxSOC 

28 

RxCLK 

47 

46 

RXD0 

RXD1 

45 

RXD2 

44 

RXD3 

42 

RXD4 

41 

40 

RXD5 

U45C 74LCX 125D 

ATMRXD0 

ATMRXD1 

ATMRXD2 

ATMRXD3 

ATMRXD4 

ATMRXD5 

ATMRXD6 

470pF 

R49 

R50 

AVDD 

33.2 

PB16 

9 8 

RXD+ 

85 

R40 

TXD- 

6 RED 

5 GREEN 

4 YELLOW 

3 BROWN 

92 

10 

R66 

47 

620 

MP3 

R57 

ATMADCNT 

1 

2 

U3 

TX+ 

TX- 

MID1 

3 

MID2 

4 

NC1 

6 

AGND1 

5 

2 GRAY 

1 

RJ_TX+ 

RJ_TX- 

P4 

7 

8 

RXCLAV 

ATMRXENB MP1 

ATMRXSOC 

ATMRXCLK 

MP4 

MP5 

TXD+ 

93 

R5 

47 

4 

MP2 

PB17 

74LCX 125D 

5 6 

TXLED 4 

TXREF 3 

U45B 

510 

R92 

ATMRXAD1 

U9 

0.1uF 

GND0 

GND1 

GND2 

GND3 

GND4 

GND5 

GND6 

1 

25 

26 

32 

50 

63 

91 

VDD0 

VDD1 

VDD2 

VDD3 

VDD4 

VDD5 

6 

23 

43 

68 

94 

98 

AGND0 

AGND1 

AGND2 

AGND3 

77 

80 

82 

87 

AVDD0 

AVDD1 

AVDD2 

AVDD3 

78 

81 

83 

86 

10uF 

0.0 1uF 

0.01uF0.1uF 

0.1uF 0.01uF0.1uF 

0.0 1uF 

0.1uF 

0.0 1uF 

C1 48 

C1 09 C1 10 

0.0 1uF 0.1uF 

C1 29 

C89 

C75 

C1 08 

D + 

C74 C93 

C1 11 

D 

C1 35 C1 45 C1 47 

VDD25 

LD7 

LED_GR EEN 

C 

A 

V3 U3 

10uF 

0.0 1uF 

0.1uF 

0.0 1uF 

0.1uF 

+ C1 28 

0.0 1uF 0.1uF 

C70 

C94 

C95 

C72 

AVDD 

C71 

C96 

3PI N_FERRITE 

5 


4 

V3 U3 

FR6 

3 

FR9 

3PI N_FERRITE 

2 

1

5 

4 

3 

2 

1 


2 


A3 

07-ATM155 A 

0.1uF 

V3U3 

uPD98 404 


A 

R72 

0 

nnet3 03 

19.44Mhz_ 3.3V 

vdd e 

CLK OUT 3 

C99 

0.0 1uFgnd 

U4 

MPC8 66ADS 

C1 01 

0 

R12 

4 

1 


Herz elia 

Isarel 46120 

Title 

28 

VDD155 

IRQ3b 

RST155b 

A155 CSb 

RDb 

WRb 

MD0 

MD1 

MD2 

MD3 

MD4 

MD5 

MD6 

MD7 

AD3 

AD4 

AD5 

AD6 

AD0 

AD1 

AD2 

78 

79 

80 

81 

82 

83 

84 

87 

88 

89 

90 

91 

92 

93 

94 

96 

97 

98 

99 

100 

101 

77 

MADD0 

MADD1 

MADD2 

MADD3 

MADD4 

MADD5 

MADD6 

MD0 

MD1 

MD2 

MD3 

MD4 

MD5 

MD6 

MD7 

CS_B 

DS_B/RD_B 

R/W_B/WR_B 

ACK_BRDY_B 

PHINT_B 

RESET_B 

MSEL 

REFCLK 

TEST0 

TEST1 

TEST2 

7 

8 

9 

JCK 2 

JDO 3 

JDI 

4 

JMS 5 

JRST_B 6 

TPD0 

TPD1 

TPD2 

TPD3 

TPD4 

TPD5 

TPD6 

TPD7 

TDI7 

RPD3 

RPD4 

RPD5 

RPD6 

RPD7 

ATMTXD6 

TDI5 

RPD1 

117 

B ATMTXD7 

TDI6 

RPD2 

63 

118 

64 

B 



65 

66 

67 

68 

17 

18 

19 

20 

21 

22 

23 

24 

R82 

510 

ATMTXD0 

ATMTXD1 

ATMTXD2 

ATMTXD3 

ATMTXD4 

ATMTXD5 

PB15 

ATMTXE NB 

ATMTXS OC 

ATMTXC LK 

FULL_B/TCLAV 

TENBL_B 

TSOC 

TCLK 

TDI0 

TDI1 

TDI2 

TDI3 

TDI4 

VDD155 

3PI N_FERRITE 

V3U3 

R110 

510 

0.0 1uF 

C1 17 

ATMTXA D0 

ATMTXA D1 

TADD0 

TADD1 

TADD2 

TADD3 

TADD4 

155MPSEL 

UMPSEL 

nnet3 01 

do not rout lines near t his pin 

Chassis 

CHASIS GRO UND 

ATMRXD1 

ATMRXD2 

ATMRXD3 

ATMRXD4 

ATMRXD5 

ATMRXD6 

ATMRXD7 

90.9 

90.9 

820 

820 

130 

R1 06 

510 

131 

132 

133 

134 

135 

136 

137 

85 

103 

104 

105 

106 

107 

123 

121 

122 

120 

111 

112 

113 

114 

115 

116 

RPC 59 

RCIC 

RPD0 

61 

62 

52 

TFKC 41 

PSEL1 

70 

PSEL0 

69 

TFC 26 

PMDALM 76 

TFSS 13 

FR11 

AIN1 

31 

TPC 25 

PHYALM2 

12 

PHYALM1 

11 

PHYALM0 

10 

TCL 

15 

RCL 

75 

TxFP 14 

RxFP 74 

RDO0 

RDO1 

RDO2 

RDO3 

RDO4 

RDO5 

RDO6 

RDO7 

130 

RCIT 51 

TCOT 43 

TCOC 44 

TFKT 40 

1K 

R36 

R67 

10K 

R64 

R63 

R61 

1K 

R35 

R6 

R31 

R32 

P5 

RCLK 

RXDN 

C ATMRXD0 130 

R71 10K 

C 

ATMRXSOC 

ATMRXCLK 

VDD155 

ATMRXENB 

RXCLAV 

EMPTY_B/RCLAV 

RENBL_B 

RSOC 

ATMRXAD1 

ATMRXAD0 

142 

141 

140 

139 

138 

125 

127 

126 

128 

0.1 uF 

RDIT 54 

RDIC 55 

C64 

4 

2 

3 

10 

CHASSIS1 

CHASSIS2 

9 

TX_GND 

11 

RX_GND 

1 


R77 

510 

0.1 uF 

Photodiode 

C65 

SD 

RXDP 

RADD4 

RADD3 

RADD2 

RADD1 

RADD0 

0.1 uF 

TDOT 47 

TDOC 48 

C67 

0.1 uF 

C66 

8 

7 

TXDP 

TXDN 

Led 

U10A 

432 R47 

432 R46 

82.5 R33 

82.5 R34 

1 

2 

3 

4 

6 

7 

8 

9 

110 R8 

110 R7 

510 R62 

HFBR-52 05 

TX_VCC 6 

RX_VCC 5 

510 R60 

3PI N_FERRITE 

FR2 

10 

5 

RN8 

10K. 

VCC 

C51 

VDD155 

2 

C58 

0.1 uF 

3PI N_FERRITE 

C59+ 

10uF 

0.1 uF 

1 

D FR3 

D 

VCC 

0.1 uF 

C52 

0.1 uF 

VCC 

3PI N_FERRITE 

C60 

FR4 

5 


4 

3 

2 

1

U33C 

BWE3b BWE3b 

J5 

nnet2 48 

BWE2b BWE2b 

1A1 

1Y1 

J2 

J6 

nnet2 49 

BWE0b BWE0b 

1A2 

1Y2 

J1 

74LCX 125D 

K5 

nnet2 50 

BWE1b BWE1b 

1A3 

1Y3 

K6 

nnet2 51 

BCD2b 

BRESETA 

1A4 

9 8 

L5 

nnet2 52 

2A1 

L6 

2A2 

M5 

V3 U3 

2A3 

M6 

BSPKOUT R205 75 nnet2 53 

PCCENb 

2A4 

J3 

BPOEAb 

1OE 

J4 

2OE 

1K 

CRDY 

BRDY 

R2 07 

CWP 

BWP 

CW AITAb 

BWAI TAb 

CINPACKb 

RXCLAV 

A CVS1 

V3U3 

BVS1 

A 

CVS2 

BVS2 

CBVD1 

BBVD1 


CBVD2 

BBVD2 

PCCENb 



BRDY 

1 

Israel 

BWAI TAb 

2 

BBV D1 

3 

RN28 

Title 

BBV D2 

4 

10K. 

MPC8 66ADS 

SN74LV C32244GKER 

BWP 

6 

RXCLAV 

7 


B VS1 

8 

A3 

08-PCMCIA I /F 

A 

B VS2 

9 


5 

4 

3 

2 

1 

K2 

1Y4 K1 

2Y1 

L2 

2Y2 

L1 

2Y3 M2 

2Y4 M1 

N5 

3A1 

3Y1 

N6 

3A2 

P5 

3A3 

P6 

3A4 

R5 

4A1 

R6 

4A2 

T6 

4A3 

T5 

4A4 

T4 

3OE 

T3 

4OE 

N2 

3Y2 N1 

3Y3 P2 

3Y4 P1 

4Y1 R2 

4Y2 R1 

4Y3 T1 

4Y4 T2 

PCMCIA_CO NN 

1 

2 

SEP- 1162 

SK1 

5 

10 

C300 

0.1uF 

C282 

0.1uF 

10 

V3.3 7, 18,31,42 

V3 U3 

C GND 4,10, 15,21,28,34,39,45 

P22 

C 

BD[0:15] 

PCCA0 

29 

PCCD0 

U57 

PCCA1 

A0 

D0 

30 

28 

PCCD1 

BD15 

2 

PCCD8 

PCCA2 

PCCD2 

BD14 

B0 

A0 

47 

27 

A1 

D1 

31 

PCCD9 

PCCA3 

A2 

D2 

32 

3 

PCCD3 

CRDY 

BD13 

B1 

A1 

46 

26 

5 

PCCD10 

PCCA4 

PCCD4 

BD12 

B2 

A2 

44 

25 

A3 

D3 

2 

PCCD11 

PCCA5 

A4 

D4 

3 

6 

PCCD5 

BD11 

B3 

A3 

43 

24 

PCCD12 

PCCA6 

A5 

D5 

4 

8 

PCCD6 

CWP 

BD10 

B4 

A4 

41 

23 

9 

PCCD13 

PCCA7 

PCCD7 

BD9 

B5 

A5 

40 

22 

A6 

D6 

5 

R2 30 10K 

PCCD14 

PCCA8 

A7 

D7 

6 

11 

BD8 

B6 

A6 

38 

12 

12 

PCCD15 

PCCA9 

PCCD8 

B7 

A7 

37 

11 

A8 

PCCA10 

A9 

D8 

64 

PCCD9 

T/R1 

1 

8 

PCCA11 

A10 

D9 

65 

PCCD10 

OE1 

48 

10 

PCCA12 

A11 

D10 

66 

21 

PCCD11 

BD7 

PCCD0 

PCCA13 

A12 

D11 

37 

13 

PCCD12 

BD6 

B8 

A8 

36 

13 

14 

PCCD1 

PCCA14 

PCCD13 

BD5 

B9 

A9 

35 

14 

A13 

D12 

38 

PCCD2 

PCCA15 

A14 

D13 

39 

16 

PCCD14 

CW AITAb 

BD4 

B10 

A10 

33 

20 

PCCD3 

PCCA16 

A15 

D14 

40 

17 

PCCD15 

CINPACKb 

BD3 

B11 

A11 

32 

19 

R2 34 10K 

19 

PCCD4 

PCCA17 

CBVD1 R2 33 10K 

BD2 

B12 

A12 

30 

A16 

D15 

41 

46 

20 

PCCD5 

PCCA18 

A17 

CBVD2 

BD1 

B13 

A13 

29 

47 

R2 32 10K 

PCCD6 

PCCA19 

R2 31 

PCCVCC 

22 

10K 

BD0 

B14 

A14 

27 

A18 

48 

23 

PCCD7 

PCCA20 

A19 

B15 

A15 

26 

49 

PCCA21 

A20 

CRDY 

T/R2 

24 

50 

PCCA22 

CWP 

IDT74LVCH R162245APA 

OE2 

25 

53 

A21 

RDY/BSY 

V3U3 

PCCA23 

A22 

54 

CW AITAb 

PCEENb 

PCCA24 

A23 

55 

CINPACKb 

PCOENb 

PCCA25 

A24 

56 

CBVD2 

A25 

CBVD1 

7 

CVS1 

B CVS2 

B 

PCRWb 

CE1 

42 

74LCX 125D 

PCREGb 

61 

CE2 

CCD1b 

REG 

5 6 

15 

CCD2b 

BCD1b 

WE/PCM 

9 

U33B 

44 

OE 

BCE1 Ab 

IORD 

45 

58 

IOWR 

BCE2 Ab 

RESET 

U40B 

16 

WP 33 

WAIT 59 

INPACK 60 

R2 35 10K 

BVD2 

62 

BVD1 

63 

VS1 

43 

VS2 

57 

CD1 

36 

CD2 

67 



1 

34 

GND1 

35 

GND2 

GND3 

68 

GND4 

4 

C41 

0.1uF 

C42 

0.1uF 

C313 

0.1uF 

C327 

0.1uF 

C320 

0.1uF 

C321 

0.1uF 

VCC1 

17 

VCC2 

51 

VPP1 

18 

VPP2 

52 


PCCVCC 

PCCVCC 

PCCD[0:15] 

PCCVPP 

PCCVPP 

PCCA[0:25] 

BPOEAb 

BALEA 



0.1uF 

C316 

0.1uF 

C317 

BA8 

BA9 

B A10 

B A11 

B A12 

B A13 

B A14 

B A15 

PCCA23 

PCCA22 

PCCA21 

PCCA20 

PCCA19 

PCCA18 

PCCA17 

PCCA16 

B A16 

B A17 

B A18 

B A19 

B A20 

B A21 

B A22 

B A23 

PCCA15 

PCCA14 

PCCA13 

PCCA12 

PCCA11 

PCCA10 

PCCA9 

PCCA8 

CVS1 

CVS2 

CCD1b 

CCD2b 

BCD1b 

BCD2b 

1 

2 

3 

4 

6 

7 

8 

9 

RN27 

10K. 

C322 

0.1uF 

C323 

0.1uF 

36 

35 

33 

32 

30 

29 

27 

26 

25 

24 

D8 

D9 

D10 

D11 

D12 

D13 

D14 

D15 

LE2 

OE2 

Q8 

Q9 

Q10 

Q11 

Q12 

Q13 

Q14 

Q15 

13 

14 

16 

17 

19 

20 

22 

23 

36 

35 

33 

32 

30 

29 

27 

26 

25 

24 

D8 

D9 

D10 

D11 

D12 

D13 

D14 

D15 

LE2 

OE2 

Q8 

Q9 

Q10 

Q11 

Q12 

Q13 

Q14 

Q15 

13 

14 

16 

17 

19 

20 

22 

23 

5 

10 

BA[6 :31] 

V3.3 7, 18,31,42 

V3.3 7, 18,31,42 

GND 4,10, 15,21,28,34,39,45 

GND 4,10, 15,21,28,34,39,45 

V3 U3 

V3 U3 

U39 

U41 

47 

B A24 

PCCA7 

46 

D0 Q0 

2 

47 

B A25 

PCCA6 

D1 Q1 

3 

46 

D0 Q0 

2 

B A26 D1 Q1 

3 

44 

PCCA5 

D2 Q2 

5 

44 

B A27 D2 Q2 

5 

43 

PCCA4 

41 

D3 Q3 

6 

43 

B A28 

PCCA3 

REGAb 

D4 Q4 

8 

41 

D3 Q3 

6 

40 

PCREGb 

B A29 D4 Q4 

8 

PCCA2 

BA6 38 

D5 Q5 

9 

40 

PCCA25 

B A30 

PCCA1 

D BA7 

D6 Q6 

11 

38 

D5 Q5 

9 

37 

PCCA24 

B A31 D6 Q6 

11 

PCCA0 

V3 U3 

D 

D7 Q7 

12 

37 

D7 Q7 

12 

48 

LE1 

48 

LE1 

1 

V3U3 

OE1 

1 

OE1 

C324 

0.1uF 

C318 

0.1uF 

C325 

0.1uF 

C319 

0.1uF 

5 


4 

3 

2 

1

5 

4 

3 

2 

1 


A3 

09-FAST- ETHERNET A 


MPC8 66ADS 


Herz elia 

Isarel 46120 

Title 

A A 


LED_GR EEN 

A C 

LD10 

LED_YELL OW 47. 5K 

R154 

A 

LD9 

C 510 

R169 

LED_R ED 

A C 

LD11 

LED_YELLOW 

A C 

LD12 

47. 5K 

R153 

nnet2 15nnet2 14 

nnet2 17 nnet2 16 

LD9 

LD 10 

LD 12 

LD 11 

510 

R170 

47.5K 

R150 

V3 U3 

R174 

510 

nnet2 11 

nnet2 12 

0.1uF 

nnet2 10 

C2 41 

nnet2 13 

Chassis 


nnet2 18 

0 

R16 

5 

6 

7 

8 

nnet3 0 04 

JP1 

B 25Mhz 

BRIDGE 

B 



510 

R171 

R143 47.5K 

2 

U26 

0.01uF 

C2 42 

vdd e 

CLK OUT 

gnd 

3 

JP1 

4 

1 

R1 65 

V3 U3 

OSCI 

nnet2 19 

37 

REXT 39 

RPTR 23 

nnet2 06 

R149 

10K 

RSTMIIb 

RESET 

L-LED/MDA0 

C_LED/MDA2 

510 

R244 

38 

R1 34 

10K 

R1 35 

2K 

FD_LED/MDA1 

LA_LED/MDA3 

nnet2 09 

VDDFE 

SPEED 11 

DPLX 42 

ANEG 40 

nnet2 08 

R1 36 

1K 

R1 51 

1K 

MIIMDC 

MIIM DIO 

Chassis 

510 

R147 

VDDFE 

MII RXCLK 

MIIRXDV 

MIIRXENC 

MIICRS 

MIIRXERR 

25 

RX_CLK 

16 

RX_DV 

15 

CRS 

RX_EN 

26 

17 

RX_ER 

12 

MDC 

13 

MDI0 


80255 

MIIRXD0 

MIIRXD1 

MIIRXD2 

MIIRXD3 

18 

RXD3 

RXD2 

19 RXD1 

20 RXD0 

21 

TPO+ 

43 

nnet2 21 

510 

R133 

MIICOL 

R1 32 nnet1 95 

22.1 

R N11 

8 22 1 RN11-1 nnet1 96 

7 22 2 RN11-2 nnet1 97 

6 22 3 RN11-3 nnet1 98 

5 22 4 RN11-4 nnet1 99 

R1 28 22.1 nnet2 00 

R1 30 22.1 nnet2 01 

nnet2 02 

R1 31 22.1 

nnet2 03 

C215 

10nF-2KV 

8 

9 

14 

COL 

TPO- 

44 

nnet2 20 

TX_EN 

14 

15 

* 

* 

* * 

* 

* 

* 

* 

12 

11 

MIITXE RR 

22.1 

TX_CLK 

nnet2 26 YELLOW 

C 34 

MIITXEN 

TX_ER 

2 

35 

16 

10 

nnet2 27 BROWN 

1 C 

MIITXCLK 

R1 29 

nnet1 94 

nnet2 25 

MIITXD0 

MIITXD1 

MIITXD2 

MIITXD3 

33 

TXD3 

29 

TXD2 

32 TXD1 

31 TXD0 

30 

TPI+ 2 

TPI- 

3 

nnet2 05 

nnet2 23 

nnet2 24 

nnet2 04 

VDDFE 

nnet2 31 

24.9 

R1 57 

0.01uF 

nnet2 32 

nnet2 28 

75 

24.9 C2 43 R142 

R1 59 

nnet2 33 

U24 TG22-3506 

24.9 

1 

R158 

* * * 

nnet2 29 

2 * 

3 5 24.9 

R1 60 

7 

75 

6 

R141 

R119 

75 


P10 

GRAY 

13 

CHASSI 

8 

BLUE 

7 

ORANGE 

6 

BLACK 

5 

RED 

4 

3 

GREEN 

CHASSI 

14 

nnet2 30 

R112 

75 

nnet2 22 

U23 

GND1 

GND2 

GND3 

GND4 

GND5 

GND6 

41 

4 

9 

36 

22 

27 

VDD1 

VDD2 

VDD3 

VDD4 

1 

10 

24 

28 

Chassis 

RJ45_Eth 

49.9 

R18 

49.9 

R17 

0.1uF 

C2 20 

0.0 1uF 

C2 24 

C228 

0.1uF 

VDDFE 

D D 

0.0 1uF 

C2 29 

C2 08 

0.1uF 

3PI N_FERRITE 

10uF 

C1 97 

0.01uF 

C209 

V3 U3 

+ C197 

C2 11 

FR18 

0.1uF 

0.01uF 

C2 10 

VDDFE 

5 


4 

3 

2 

1

5 

4 

3 

2 

1 


A3 

10- CONTROL A 


MPC8 66ADS 


Herz elia 

Isarel 46120 

Title 

A A 


R1 94 

1K 

BSYSCL K1 

8 

10 

nnet1 34 

GND1 

4 

nnet1 32 

AT MCKSEL 

B VCC TDI 

9 

EPM3128ATC14 4-10 

6 

nnet1 33 

B 



2 

nnet1 31 

VCC 

TCK 

HEADER_2x5 

1 

TDO 3 

TMS 5 

NC_1 

NC_3 

GND NC_2 

7 

33 

77 

64 

3 

135 

126 

26 

13 

94 

17 

124 

52 

105 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

85 

57 

114 

59 

129 

GND 

GND 

GND 

GND 

GND 

P20 

AD_ATM7 

63 

AD_ATM6 

96 

AD_ATM5 

65 

AD_ATM4 

83 

AD_ATM3 

82 

AD_ATM2 

80 

AD_ATM1 

93 

AD_ATM0 

69 

MD7 

98 

MD6 

97 

MD5 

78 

MD4 

79 

MD3 

81 

MD2 

67 

MD1 

100 

40 

ALE_ATM25 

IPASEL1 

45 

IPASEL0 

61 

nMII_RX_EN 

nCS_Framer 

117 

nCS_ATM155 

71 

nCS_ATM25 

55 

MUXSEL 

86 

68 

nRD_Dual 

nRD_ATM25 

116 

113 

nRESET_MII 

nRESET_Framer 

119 

nRESET_ATM155 

74 

nRESET_ATM25 

70 

60 

PDSEL1 

56 

PDSEL0 

84 

nWR_Dual 

102 

nWR_ATM25 

88 

SPARE2 

109 

SPARE1 

118 

SPARE0 

110 

TP4 

101 

TP3 

91 

TP2 

87 

TP1 

111 

R213 

1K 

R2 14 

ATMADCNT 

nnet1 24 TM23 

nnet1 23 

nnet1 25 TM21 

nnet1 26 TM28 

TM20 

1K 

1K 

R1 93 

128 

CLKIN 

CONN PLUG 3 

nnet1 27 

89 

4 

104 

20 

155MPSEL 

V3 U3 

PCCENb 

HRESE Tb 

V3 U3 

RWb 

TSb 

WE0b 

EDOO Eb 

CS5b 

RPORIb 

nOE 

nCS 

nPORESET 

RD_nWR 

nTS 

nWE 

CE1 

CE2 

CLK 

FUNC_SEL0 

FUNC_SEL1 

FUNC_SEL2 

TCK 

TDI 

TDO 

TMS 

BD7 

IPASE L0 

IPASE L1 

PDS EL0 

PDS EL1 

WRb 

WRATM 25b 

RDb 

RDATM25b 

RSTMIIb 

RSTFRMRb 

RS T155b 

RS T25b 

MIIRXENC 

CSFRM Rb 

A155C Sb 

CS ATM25b 

MUXSELb 

10K 

3 

2 

1 

3 

2 

1 

J4 

134 

140 

127 

143 

53 

125 

38 

141 

142 

136 

137 

139 

R1 96 

14 

BDAT6 

BDAT7 

nnet1 30 

BD5 

BDAT4 

MD0 

C 10 

BD6 

BDAT5 

11 

72 

ALEA TM25 

C 


10K 

R210 

BD0 

BD1 

BD2 

BD3 

BD4 

5 

6 

7 

8 

9 

BDAT0 

BDAT1 

BDAT2 

BDAT3 

V3 U3 

MD7 

MD6 

MD5 

MD4 

MD3 

MD2 

MD1 

MD0 

nnet1 29 

BA21 

BA22 

BA23 

BA24 

BA25 

BA26 

BA27 

BA28 

BA29 

BA30 

BA31 

AD7 

AD6 

AD5 

AD4 

AD3 

AD2 

AD1 

AD0 

10K 

ADDR_PQ21 

ADDR_PQ22 

ADDR_PQ23 

ADDR_PQ24 

ADDR_PQ25 

ADDR_PQ26 

ADDR_PQ27 

ADDR_PQ28 

ADDR_PQ29 

ADDR_PQ30 

ADDR_PQ31 

R2 09 

15 

16 

18 

21 

22 

23 

25 

27 

28 

29 

30 

1 0 

V3 U3 

0 0 0 00 EXCON 11 EXCON 

SW DIP-4 /SM 

ON=0 

0 0 1 00 EXCON 10 xxx 

OFF=1 

0 1 0 ATMMUX 00 PCMCIA 

R2 06 

10 

D 0 1 1 ATMMUX 10 MII 

D 

10K 

10 

nnet1 28 

FR21 

PW RALTRA 

1 0 0 10 ATMSPLIT 01 ATMSPLIT 

1 0 1 MUX 11 EXCON 

3PI N_FERRITE 

10 

U37 

V3 U3 

1 1 0 11 MII 00 PCMCIA 

1 1 1 11 MII 00 EXCON 

VCCINT 51 

VCCINT 58 

VCCINT 130 

VCCINT 123 

VCCIO 115 

VCCIO 50 

VCCIO 95 

VCCIO 73 

VCCIO 24 

VCCIO 76 

VCCIO 144 

0.01uF 

C303 

0.1uF 

C296 

0.01uF 

C291 

C285 

0.1uF 

0.01uF 

C284 

0.1uF 

C288 

0.01uF 

C292 

C295 

0.1uF 

1 

2 

3 

4 

8 

7 

6 

5 

SEL866 

SW3 

PDSEL 

IPASEL 

DS2 DS3 DS4 1 0 PORT-D POR-IPA 

10K 

R2 37 

SW3 

V3U3 

5 

V3 U3 


4 

3 

2 

1

5 

4 

3 

2 

1 



A3 A 

 

1 She nkar st. 

Her zelia 

Isarel 46120 

Title 

C11 

A A 

0.01uF 

C10 

0.1uF 


3 

2 

V3 U3 

In the TTM board 1 & 2 a nd all the 3.3V regulator 

will be popu lated. 

RP1 

1K 

1 

nnet1 63 

This 3pin Jumper is not a solder 

ju mper 

It is for VD DH 

testing 

In the re gular ADS it will be solder 2 & 3 

R1 00 

243 

J2 CONN PLUG 3 

3 

3 

2 

2 

1 

1 

nnet1 68 

C1 39 

0.1uF 

nnet1 64 

2 

nnet2 54 

V3 U3 

+ C158 

1uF 

PWRVDH86 

1 

ADJ OUT 

1 

MPC86 2/6 

P14 

GND 

GND 

3 

B IN 

4 

GND 

P12 

GND VDDH 

P13 

B 

F15 

PWRVDL 86 

U18 

PWRA1553 

IN 

0.1uF LM3 17MDT 

C154 

nnet1 67 

0.0 1uF 

C153 

PWRA1554 

For 3.3V (862) the 510ohm should be 0ohm 

C1 96 

10uF 

510o hm is for fix 1.8V 

0.1uF 

0.1uF C76 + 

in this case the potensiometer 

C152 

C76 

should not be populated. 

0.0 1uF 

nnet1 65 

C151 

0.1uF PWRA1555 

C150 

0.1uF nnet1 66 

C146 C 1K 

C 

For 3. 3V (862) the 51.1ohm should be 

2 

0ohm 

RP2 

VCC 

LL4004 

D3 

C A 

LM3 17MDT 

U12 

3 

VDD7 

119 

129 

VDD8 VDD-RPE 

VDD9 

4 

OUT 

16 

37 

GND1 

GND2 

71 

GND3 

72 

86 

GND4 

GND5 

102 

109 

GND6 

FR5 

GND7 

110 

GND8 

124 

143 

GND9 

3PI N_FERRITE 

GND10 

144 

GND11 

uPD98 404 

FR10 

3PI N_FERRITE 

** 

0.1uF 

C97 

53 

GND-RPE2 

56 

GND-RPE1 

50 

VDD-SP 35 

GND-SP 38 

VDD-CR 58 

GND-CR 

VDD-CS2 

33 

VDD-CS1 

32 

GND-CS3 

34 

GND-CS2 

30 

GND-CS1 

29 

57 

GND 

LL4004 

0.0 1uF 

FR12 

C156 

3PI N_FERRITE 

D5 

LL4004 

0.1uF 

C84 

+ C18 

1uF 

0.1uF 

C77 

C189 + 

10uF 

F6 

GND 

H10 

H11 

GND 

GND 

H12 

GND 

H13 

H14 

GND 

GND 

J6 

J7 

GND 

GND 

J8 

GND 

J9 

J10 

GND 

GND 

J11 

J12 

GND 

GND 

J13 

GND 

J14 

K6 

GND 

GND 

K7 

K8 

GND 

GND 

K9 

GND 

K10 

GND 

K11 

GND 

K12 

K13 

GND 

GND 

K14 

GND 

L6 

GND 

L7 

GND 

L8 

L9 

GND VDDH 

GND 

L10 

GND 

L11 

GND 

L12 

GND 

L13 

GND 

L14 

GND 

M6 

GND 

M7 

M8 

GND 

GND 

M9 

GND 

M10 

GND 

M11 

GND 

M12 

GND 

M13 

GND 

M14 

N6 

GND 

GND 

N7 

GND 

N8 

GND 

N9 

GND 

N10 

GND 

N11 

GND 

N12 

GND 

N13 

N14 

GND 

GND 

P6 

GND 

P7 

GND 

P8 

GND 

P9 

P10 

GND 

GND 

P11 

E5 

VDDH E6 

VDDH E7 

VDDH E8 

VDDH E9 

VDDH E10 

VDDH E11 

VDDH E12 

VDDH E13 

VDDH E14 

VDDH E15 

VDDH G15 

VDDH H15 

VDDH J15 

VDDH K15 

VDDH L15 

VDDH M15 

VDDH N15 

VDDH L5 

VDDH K5 

VDDH J5 

VDDH H5 

VDDH G5 

VDDH R15 

VDDH R14 

VDDH R13 

VDDH R12 

VDDH R11 

VDDH R10 

VDDH R9 

VDDH F5 

VDDL A8 

VDDL H19 

VDDL M1 

VDDL W8 

VDDH P15 

VDDH T14 

VDDH P5 

VDDH N5 

VDDH M5 

VDDH R8 

VDDH R7 

VDDH R6 

VDDH R5 

VDDL P16 

VDDL F16 

VDDL F4 

VDDL P4 

0.1uF 

C155 

C1 31 + 

3PI N_FERRITE 

10uF 

10uF 

C79 C1 12 C1 30 + 

C98 

0.0 1uF 

10uF 

+ C1 22 

0.0 1uF 

C149 

C122 

0.0 1uF 

C136 

0.0 1uF 

C90 

0.0 1uF 

C78 

C63 

10uF 

C63 



D4 

A C 

LL4004 

FR16 

R95 

143 

C178 

C216 

0.0 1uF 0.01uF 

C177 

C214 

0.1uF 0.1uF 

C176 C199 

0.0 1uF 0.01uF 

C225 

0.1uF 

C195 

0.1uF 

2 

+ 

C187 

0.01uF 

C188 

0.1uF 

1 

C206 

0.0 1uF 

C200 

0.1uF 

C207 

0.0 1uF 

C213 

0.1uF 

3 

C184 

0.0 1uF 

C183 

0.1uF 

R101 

51.1 

C179 

0.0 1uF 

0.1uF 


C180 

1 

0.01uF 

C118 

0.1uF 

C120 

0.01uF 

C119 

C121 

0.1uF 

C192 

0.0 1uF 

C226 

0.1uF 

2 

R102 

243 

1 

510_1% 

R117 

0.0 1uF 

0.1uF 

A C 

0.0 1uF C182 

0.1uF C181 

0.0 1uF C186 

0.1uF C185 

0.0 1uF C222 

0.1uF C223 

0.0 1uF C198 

0.1uF C194 

1 

R120 

143 

ADJ 

0.0 1uF 

C80 

0.1uF 

C113 

73 

VDD5 GND-TPE2 

42 

A C 

D 108 

VDD6 

D 

95 

PWRA1552 

GND F7 

GND F8 

0.0 1uF 

H7 

C15 

FR13 

GND 

H8 

H9 

GND 

0.1uF C14 

1 

27 

36 

60 

VDD1 

VDD2 

VDD3 

VDD4 

VDD-TPE1 

VDD-TPE2 

VDD-TPE3 

GND-TPE1 

39 

49 

45 

46 

0.1uF C83 

0.0 1uF C82 

0.1uF C81 

0.0 1uF C1 16 

0.1uF C1 15 

0.0 1uF C1 14 

+ 

PWRA1551 

10uF 

C1 32 

3PI N_FERRITE 

FR19 

VCC 

0.0 1uF 

C100 

U10B 

FR14 

VDD155 

G8 

G9 

G10 

G11 

G12 

G13 

G14 

H6 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND F9 

GND F10 

GND F11 

GND F12 

GND F13 

GND F14 

GND G6 

3 

2 

1 

3 

2 

1 

CONN PLUG 3 

D6 

0.1uF C85 

J3 

V3 U3 

VDD155 

U20A 

5 


4 

3 

2 

V3P 

1

5 

4 

3 

2 


A3 

12-POWER A 


1 

MPC86 6ADS 

MMDF3N03HD 

Title 

nnet2 60 3 

6 

V3 U3 

A A 

2 

7 


+ C304 


1uF 

1 

8 


Israel 

2 

1 

nnet2 59 

Q3 

4 5 

DRMPWR 

MMDF3N03HD 

124K( *) 

1 

8 

R2 16 

V12 

3 

nnet1 40 

2 

7 

6 

V3 U3 

Q2 

nnet2 614 

5 

124K( *) 

LTC1315 

R2 11 

2 

1uF 

C302 

0.1uF 

VCC 

DRMPWR 3 

6 

24 

AVCCIN 

18 

10K 

BVCCIN 

4 5 

R189 

PCVCC0 

PCVCC0 ASHDN 

5 

nnet1 37 

PCCVCC1 PCCVCC1 6 

AVCC0 

MMDF3N03HD 

PCCVPP0 PCCVPP0 

AVCC1 

3 

PCCVPP 

PCCVPP1 PCCVPP1 

AEN0 

U27-1 

4 

AEN1 

nnet1 38 

11 10 

DRM3U5b 

DRM3Vb 

B B 

PCCVCC 

74AC14D 

nnet1 39 

DRM3Vb 

V12 

+ C289 

2 

BSHDN 8 

BVPPOUT 17 

AVPPOUT 

11 

BVCC0 

12 

BVCC1 

9 

BEN0 BDRV5 

13 

10 

BEN1 BDRV3 

14 

23 

ADRV5 

19 

ADRV3 

20 

+ 



R1 90 

0 (*) 

22 

16 

GND 

GND 

C293 

10uF 

1 

U32 

AVPPIN 1 

BVPPIN 7 

VCC 21 

VCC 15 

nnet1 36 

2 

7 

124K(*) 

124K(*) 


1 

8 

Q1 

VCC 

R1 99 

R2 02 

VCC 

V12 

PWR2 

SMD1 50/33-2 

MBRD620CT 

4 

1 

1SMC12AT3 

+ 

2 

C20 

P12 

D8 

68UF_20V 

3 

- 

1 

D7 

C C 

F1 

VPPIN 

VPP 

VPP 

Chassis 

Chassis 

VCC 

V3U3 

nnet1 41 

+Vin 

VIN FLT 

C23 

MIC29 500 

+ 

1 

PA13 

1SMC5.0AT3 1000pF 

C278 

IN 

OUT 

nnet1 35 

1 

100UF 

MIC29 500 

D 2 

- 

D 

1 

Chassis 

Chassis 

3 

RAP C722 

D9 

2 

GND 

3 

-Vin 

GND 

2 

TAB IS GROUNDED 

C25 

0.0 1uF 

3 

ACM1110-1 02-2P 

"0" 

"I" 

C2 74 

L7 

0.0 1uF 

+ 

C265 

1000pF 

SW2 

3 

F2 

2 

1 

SMD2 60 

E101MD1 ABE 

PWR3 

4 

+ 

3 1 

D10 

P13 

2 

2 

3 

2 

C271 

C287 

10uF 

C286 

10uF 

1uF 

1 

MBRD620CT 

1 

4 

1 

"PWR" 

5 


4 

3 

2 

1

5 

4 

3 

2 


A3 

13-RES ET & INDICATORS A 


1 

MPC86 6ADS 



Israel 

Title 

A A 


B B 



C269 

100pF 

C272 

0.1uF 

74AC14D 

C36 

10nF 

LL4004 


U31 DS1 818-10 

U27-3 

U27-2 

D LED_GREEN LD23 

2 

5 6 

RPORI 

D 

RUN 

nnet1 18 nnet1 17 R179 

VDD RESET 

1 2 

C 

A 

V3U3 

150 

RUN 

+ 74AC14D 

74AC14D 

C35 

nnet1 16 

5V PO WER 

100UF 

- 

1K R182 

U33D 

V3 U3 

U27-4 

74LCX 125D 

U35-2 

U35-6 

LED _YELLOW 

V3 U3 

SDRAMEN 

nnet1 19 

nnet1 15 R175 

9 8 

12 11 

C LD14 A 

nnet3 07 

1 2 

3 4 

51.1 

LED_GREEN 

1K 

74AC05D 

nnet1 14 R176 

74AC14D 

C LD15 A 

74A C05D R20 

SIGNAL LAMP 

nnet3 19 

150 

DRAM ON 

V3 U3 

nnet1 13 

DRMPWR 

U35-1 

11 10 

nnet1 12 R178 

FLA SH ENABLED 

U35-5 

CHINSb 

150 

LED _YELLOW 

74A C05D 

C LD18 A nnet1 11 

PCMCI A ENABLED PCCVCC 

13 12 

U35-3 

U30 

LED _YELLOW 

5 6 

SGLAMPb 

2 

nnet1 06 

R181 nnet1 10 

LD19 RS232 PO RT 1 ENABLED 

74AC05D 

DRAMENb 

1A1 1Y1 

18 

C 

A 

4 

C FENb 

nnet1 05 

150 

6 

1A2 1Y2 

16 

LED _YELLOW 

74A C05D 

C 

PCCENb 

1A3 1Y3 

14 

8 

nnet1 04 

R183 nnet1 09C 

A LD20 

1A4 1Y4 

12 

1 

INFRA-RED ENABLED 

RSEN1b 

nnet1 03 

150 

11 

1G 

IRDENb 

2A1 2Y1 

9 

13 

nnet1 02 

ETHENb 

15 

2A2 2Y2 

7 

nnet1 01 

nnet1 08 

ETHERNE T ENABLED 

RSEN2b 

2A3 2Y3 

5 

17 

nnet1 00 

CHINSb 

2A4 2Y4 

3 

19 

2G 

R186 nnet1 07 LED_ YELLOW C LD22 A 

RS232 PO RT 2 ENABLED 

VCC 

150 

74LS244DW 

nnet1 20 

V12 

nnet1 21 

D12 

nnet1 22 

A C 

1 

LED_GREENLD13 

C 

A 

R172 

150 

TM24 

1K 

U35-4 

R1 91 

LED _YELLOW 

9 8 

C LD16 A 

R177 

150 

LED _YELLOW 

74AC05D 

C LD17 A 

R180 

150 

R185 

LED_ YELLOW 

C 

A LD21 

150 

R19 

D13 

A C 

5.1K 

LL4004 

U27-5 

13 12 

13 

3 

GND 

VCC 

V3 U3 

C277 

0.1uF 

LL4004 

A C 

R184 

47.5K 

D11 

V3U3 

V3 U3 

VCC 

RPORIb 

5 


4 

3 

2 

1

5 

4 

3 

2 


14-ADI CONTROL 

Da te: She et of 

1 

A 

A3 

Tuesday , December 17, 2002 

14 20 

MPC8 66ADS 


Herz elia 

Isarel 46120 

Title 

1 

CHINSb 2 

ADSADR0 3 

A 4 

RN20 

A 

FRZ 6 

10K. 


7 

ADSADR2 8 

ADSADR1 9 

5 

10 

VCC 

D1 

1K 

R1 15 

SW1 SW DIP-4/ SM 

4148D 

R88 

nnet71 

J1 

10K 4.3V 

1 

1 

2 

ADSADDR & MODCK 

B 2 

B 

3 

3 

M4A3-1 28/64-55VC 

CONN PLUG 3 



5 

6 

7 

8 

C 

C133 

1 

GND_0 

13 

25 

GND_1 

GND_2 

26 

GND_3 

27 

38 

GND_4 

GND_5 

39 

49 

GND_6 

GND_7 

50 

GND_8 

51 

63 

GND_9 

GND_10 

75 

76 

GND_11 

GND_12 

77 

GND_13 

88 

89 

GND_14 

GND_15 

99 

100 

GND_16 

GND_17 

0.1uF 

4 

3 

2 

1 

A 

nnet2 58 

nnet63 

nnet2 35 

nnet68 

SRESETb 

BDCb 

nnet16 

nnet72 

nnet3 11 

DSCK 

BHSTA CK 

nnet17 

nnet73 

BADSSR ST 

nnet18 

nnet74 

DSDI 

BADS HRST 

nnet19 

nnet75 

nnet76 

ISP INTDI V3U3 

BAD IA2 

nnet23 

nnet77 

BAD IA1 

nnet24 

nnet78 

BAD IA0 

nnet79 

BHSTR EQ 

nnet2 34 

nnet80 

DSDO 

nnet25 

nnet81 

nnet70 

nnet82 

nnet83 

ISPTCK 

nnet84 

ISPTCK 

RBHSTVCC 

BHS TVCC 

nnet85 

ISP TMS 

nnet86 

ISP TMS 

BA DSREQ 

nnet87 

ISP INTDI 

RBADSREQ 

BA DSACK 

nnet88 

ISP INTDI V3 U3 

nnet89 

RBADSACK 

nnet90 

HSTE Nb 

nnet91 

ISPTCK 

nnet64 

nnet92 

ISP TMS nnet65 

C VCC 

BAP D0 

nnet93 

ISPTDI 

nnet66 

nnet3 18 C 

BAP D1 

nnet94 

BAP D2 

nnet95 

nnet96 

nnet97 

RN6 22 

BAP D3 

nnet98 

RBAPD0 1 

BAP D0 

BAP D4 

nnet99 

VCC 

RBAPD1 2 

BAP D1 

BAP D5 

RBAPD2 

BAP D2 

BAP D6 

AP D0 

ISPTDO 

3 6 

RBAPD3 4 5 BAP D3 

BAP D7 

AP D1 

RBAPD4 

BAP D4 

AP D2 

RBAPD5 

BAP D5 

AP D3 

FRZ 

RBAPD6 

BAP D6 

AP D4 

CHINSb 

RBAPD7 

BAP D7 

AP D5 

VFL S0 

AP D6 

VFL S1 

AP D7 

RUN 

VCC 

MODIN 

nnet67 

ADSADR0 

ADSADR1 

ICL K/2 

VFLSFR Zb 

ADSADR2 

V3U3 

7 

P9 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

TM10 

TM6 

10K 

R87 

TM17 

8 

1 

2 

3 

4 5 

RN5 22 

6 

TM9 

RN19 

P15 

1 

1 TCK NC 2 

2 

3 TMS GND 4 

TM5 

3 6 5 TDI VCC 6 

TM15 

4 5 

7 TDO GND 8 

9 NC NC 10 

22 

TM18 

HEADER_2x5 

8 

7 

7 

P6 

TM13 

8 

TM19 

19 

CON DB 37 

37 

36 

18 

17 

35 

16 

15 

34 

33 

14 

32 

31 

13 

12 

30 

11 

10 

29 

28 

9 27 

26 

8 

7 

25 

6 

5 

24 

23 

4 22 

21 

3 

2 

20 

1 

R96 0 

1 

2 

3 

4 5 

RN9 22 

TM8 

6 

7 8 

U11 

U47 

BEA 

2 

1A1 1Y1 

18 

4 

1A2 1Y2 

16 

6 

1A3 1Y3 

14 

8 

1A4 1Y4 

12 

1 

1G 

11 

2A1 2Y1 

9 

13 

2A2 2Y2 

7 

15 

2A3 2Y3 

5 

17 

19 

2A4 2Y4 

3 

2G 

TM12 

TM7 

2 

1K 

R97 

TM14 

0 

TM16 

IDTQS32X384 U47 

TM4 

1 

2 

B0 A0 

3 

5 

B1 A1 

4 

6 

B2 A2 

7 

9 

A3 

8 

10 

B3 

B4 A4 

11 

BEB 37 

14 

B5 A5 

15 

17 

A6 

16 

18 

B6 

B7 A7 

19 

21 

B8 A8 

20 

22 

B9 A9 

23 

BEC 13 

A10 

26 

A11 

29 

A12 

30 

A13 

33 

A14 

35 

27 

B10 

28 

31 

B11 BED 

B12 

32 

B13 

34 

B14 

25 

A15 

38 

A16 

41 

A17 

42 

A18 

45 

A19 

46 

VCC 48 

VCC 36 

22 

AdsSel0 

39 

B15 

40 

B16 

43 

44 

B17 

B18 

47 

B19 

12 

GND 

24 

GND 

AdsAddr0 

18 

AdsAddr1 

17 

AdsAddr2 

16 

AdsSel1 

21 AdsSel2 

72 

DbgClkOut 

DSDI 

28 

29 

D_C_B 

DSCK 

31 

HstAck 

36 

AdsSoftReset 

64 

19 

AdsHardReset 

32 

HstReq 

61 

Host_Vcc 

7 

Hst_En_B 

Run 

57 

54 

Clk2 

30 

VflsP1 

59 

VflsP0 

70 

20 

AdsAck 

AdsReq 

PdaSoftReset_B 

96 

55 

PD0 

53 

84 

PD1 

PD2 

80 

PD3 

78 

PD4 

3 

PD5 

46 

9 

PD6 

PD7 

5 

PdaHardReset_B 48 

11 

IClk 

Freeze 

4 

ChinS_B 

VFLS0 

6 

VFLS1 

15 

8 

DSDO 10 

VflsFrz_B 86 

14 

DbgClk 

TMS 

TDI 

2 

VCC_0 

23 

TCK 24 

TRST 73 

TDO 74 

ENABLE 52 

SPARE_15 

68 

SPARE_16 

69 

33 

34 

SPARE_0 

SPARE_17 

71 

SPARE_1 

SPARE_18 

79 

TM11 

35 

41 

SPARE_2 

SPARE_19 

81 

SPARE_3 

SPARE_20 

82 

42 

SPARE_4 

SPARE_21 

83 

43 

44 

SPARE_5 

SPARE_22 

85 

SPARE_6 

SPARE_23 

91 

R98 

45 

47 

SPARE_7 

SPARE_24 

92 

SPARE_8 

SPARE_25 

93 

1K 

56 

SPARE_9 

SPARE_26 

94 

58 

60 

SPARE_10 

SPARE_27 

95 

SPARE_11 

SPARE_28 

97 

65 

66 

SPARE_12 

SPARE_29 

98 

SPARE_13 

67 

SPARE_14 

C164 

0.01uF (*) 

C166 

0.01uF (*) 

C173 

0.01uF (*) 


3 

1 

RJ4 

R99 

1K 

R123 

1K 

R116 

1K 

74L S244DW 

12 

VCC_1 

37 

VCC_2 

40 

VCC_3 

62 

VCC_4 

87 

VCC_5 

90 

R1 05 

0 

nnet3 05 

V3 U3 

20Mhz 

vdd e 

C1 70 

nnet2 87 

DBGCLK 

V3 U3 

CLK OUT 3 

R14 

C1 71 

0 

R1 22 

0.1uF 0.0 1uF gnd 

U17 

100 

D 1K 

D 

R13 

U16 

nnet69 

2 

4 

1 

C168 

0.1uF 

C169 

0.1uF 

C163 

0.1uF 

C16 

0.1uF 

C174 

0.1uF 

C17 

0.1uF 

V3 U3 

HRESE Tb 

V3 U3 

VCC 

VCC 

5 


4 

3 

2 

1

5 

4 

3 

2 

1 



A3 

15-T1_E1 A 

MPC8 66ADS 


Herz elia 

Isarel 46120 

Title 


A 

U6 

B B 



4 

8 

1.544_2. 048 

vdd 

CLK OUT 5 

gnd 

0 

R79 

MD[ 0:7] 

IRQ3b 

RSTFRMRb 

RDb 

WRb 

CSFRM Rb 

AD[0:7] 

MD0 

MD1 

MD2 

MD3 

MD4 

MD5 

MD6 

MD7 

0.0 1uF 

C1 25 

0.1uF 

C1 26 

VDDT1 

VDD T1 

AD0 

AD1 

AD2 

AD3 

AD4 

AD5 

AD6 

AD7 

V3 U3 

PEB2256 

Chassis 

1:2.4 

T11 44 

XDON_1 

P- S- 

C 2.7 

5.6 

TRANSM IT 

RJ4 5_Eth 

C 

54 

CS 

43 

44 

45 

46 

47 

48 

49 

50 

A0 

A1 

A2 

A3 

A4 

A5 

A6 

A7 

40 

39 

38 

37 

36 

33 

32 

31 

30 

29 

28 

27 

26 

23 

22 

21 

D0 

D1 

D2 

D3 

D4 

D5 

D6 

D7 

D8 

D9 

D10 

D11 

D12 

D13 

D14 

D15 

WRITE 

53 RD 

57 

13 

52 

INT 

RES 

73 

MCLK 

55 

11 

12 

51 

BLE~ 

IM 

DBW 

ALE 

SYNC 

79 SEC/FSC 

78 

15 

TDI 

TMS 

16 TCK 

17 TRS~ 

14 TDO 

76 

77 

CLK1 

CLK2 

18 


5 

R45 

3 

14 

U25 14 

R44 

TM2 

M 

U24 P65 

2 

M+ 

15 

1 

P+ 

S+ 

5.6 

16 

R39 

TM3 

U24 P60 

60 

61 

62 

63 

64 

XPA_1_SYPX~ 

XPB_1_XSIG 

XPC_1_TCLK_XCLK 

XPD_1_TFS 

SCLKX_1 

XDOP_1 

2.7 

7 

R43 

PA11 

56 

XDI_1 

RDIN_1 

5.6 

2 

6 

U25 11 

U24 P64 

PC6 

U2 59 

PA2 

22.1 

PA10 

U2 

RECEI VE 

1:1 

S+ P+ 

M M+ 

S- P- 

11 

TM1 

7 

10 

5.6 

RDIP_1 

8 

9 

3 

R56 

R70 

75 

66 

67 

68 

69 

70 

65 

RCLK_1 

RDO_1 

RPA_1_RTIMS 

RPB_1_RSIGD 

RPC_1_RSFP~/RFM 

RPD_1_RMFB 

SCLKR_1 

100 

R48 

8 

BLUE 

ORANGE 

7 BLACK 

6 RED 

5 GREEN 

4 YELLOW 

3 BROWN 

2 GRAY 

1 

13 

CHASSI 

14 

CHASSI 

P3 

R73 

R1 11 

510 

U7 

VDDR 4 

VSSR 1 

NC1 

19 

NC2 

20 

NC3 

74 

NC4 

80 

VSS 10 

VSS 25 

VSS 35 

VSS 42 

VSS 59 

VSS 72 

VDD 9 

VDD 24 

VDD 34 

VDD 41 

VDD 58 

VDD 71 

VDDX 6 

VSSX 8 

3PI N_FERRITE 

+ C1 27 

10uF 

3PI N_FERRITE 

V3 U3 

VDDT1 

VDD T1 

D FR15 

D 

10uF 

0.0 1uF 

0.01uF 

3PI N_FERRITE 

0.1uF 

VDDT1 

FR8 

C159 

+ 

C88 

C1 40 

VDD T1 

FR7 

0.1uF 

0.1uF 

0.1uF 

0.1uF 

C1 06 

BRIDGE 

0.1uF 

0.1uF 

0.1uF 

0.0 1uF 

73 

10uF 

0.0 1uF 

+ C 

JP3 

C1 07 

C1 34 

C1 44 

C1 41 

C1 42 

C1 43 

C91 

C87 

C1 05 

5 


4 

3 

JP5 

BRIDGE 

2 

1

5 

4 

3 

2 


A3 

16-EXP_CONN A 


1 

MPC8 66ADS 



Israel 

Title 

A A 


CONN-96 

CONN-96 

CONN-96 

P21A 

V3U3 P21B 

EXATMRSC 

A1 

P21C 

EXATMRD0 

A2 

B1 

BD0 

EXATMRD1 

A3 

B2 

BD[0..7] 

C1 

BD1 

EXATMRD2 

A4 

B3 

C2 

BD2 

EXATMRD3 

A5 

B4 

C3 

BD3 

EXATMRD4 

A6 

B5 

C4 

BD4 

EXATMRD5 

A7 

B6 

C5 

BD5 

EXATMRD6 

A8 

B7 

C6 

BD6 

EXATMRD7 

A9 

B8 

C7 

A10 

BD7 

EXM ITXD3 

B9 

C8 

B A16 

EXATMRCK 

A11 

EXM ITXD2 

B10 

C9 

A12 

B A17 

EXM ITXD1 

B11 

C10 

A13 

B A18 

EXPC OL 

B12 

C11 

B A19 

B BWE0b 

A14 

EXP TXEN 

B13 

C12 

B A20 

B 

BDRMWb 

A15 

EXPMD IO 

B14 

C13 

B A21 

BEDO OEb 

A16 

EXPCRS 

B15 

C14 

B A22 

BGPL2b 

A17 

B16 

C15 

B A23 

BGPL3b 

A18 

B17 

C16 

B A24 

GPL4Ab 

A19 

B18 

C17 

B A25 

GPL4Bb 

A20 

B19 

C18 

B A26 

GPL5Ab 

A21 

B20 

C19 

B A27 

GPL5Bb 

A22 

B21 

A23 

B22 

B A28 

B A29 

BSYSCL K3 

A24 

B23 

A25 

B24 

B A30 

B A31 

BS0Ab 

A26 

B25 

A27 

B26 

BA[16 ..31] 

MIISELb 

BRW2b 

A28 

B27 

B TSb 

A29 

B28 

TAb 

A30 

B29 

CS7b 

A31 

B30 

CS6b 

A32 

B31 

B32 



C20 

C21 

C22 

C23 

C24 

C25 

C26 

C27 

C28 

C29 

C30 

C31 

C32 


CONN-96 

CONN-96 

CONN-96 

P7C 

P7B 

P7A 

C1 

PB31 

B1 

ETHRX 

A1 

C2 

PB30 

B2 

E THTX 

A2 

C3 

PB29 

B3 

IRDRXD 

A3 

D C4 

PB28 

B4 

IRDTXD 

A4 

D 

C5 

RSEN2b 

RSEN2b 

PB27 

B5 

MPD 11 

A5 

C6 

PB26 

B6 

MPD 10 

A6 

C7 

RSTXD1 

B7 

MPD9 

A7 

C8 

RSRXD1 

B8 

MPD8 

A8 

C9 

RSD TR1b 

B9 

ET HTCK 

A9 

C10 

RSD TR2b 

B10 

ETHRCK 

A10 

C11 

RSTXD2 

B11 

PA5 

A11 

C12 

RSRXD2 

B12 

PA4 

A12 

C13 

ETENA 

B13 

PA3 

A13 

C14 

PB18 

B14 

PA2 

A14 

MPD15 

C15 

PB17 

B15 

PA1 

A15 

MPD14 

C16 

PB16 

B16 

PA0 

A16 

MPD13 

C17 

PB15 

B17 

A17 

MPD12 

C18 

PB14 

B18 

PA11 

A18 

MPD7 

C19 

B19 

PA10 

A19 

MPD6 

C20 

RXCLAV 

B20 

PA9 

A20 

C21 

HRESE Tb 

HRESE Tb 

PC14 

B21 

PA8 

A21 

C22 

SRESETb 

S RESETb 

PC13 

B22 

A22 

C23 

PC12 

B23 

A23 

C24 

ECLSN 

B24 

MIRQ 7b 

A24 

C25 

FRZ 

ERENA 

B25 

A25 

MPD3 

C26 

PC9 

B26 

ETHENb 

A26 

C27 

IRQ3b 

VPPIN 

VP PIN 

PC8 

B27 

A27 

C28 

IRQ2b 

PC7 

B28 

A28 

C29 

IRQ1b 

PC6 

B29 

A29 

NMIb 

MPD4 

C30 

PC5 

B30 

A30 

C31 

PC4 

B31 

RSEN1b 

A31 

C MPD5 

C32 

B32 

A32 

C 

VCC 

VCC 

5 


4 

3 

2 

1

(*) NOT ASSEMBLED 

0 R2 25 DBREV1 

0 R24 BRE V0 


V3 U3 

V3 U3 

V3 U3 

A A 

0 R25 BRE V1 

V3 U3 

0 (*) R2 15 DBID0 


0 R26 BRE V2 

0 R2 17 DBID1 


DBID0 1 

DRMPD1 1 

DBREV0 1 

BCSR2R4 1 


0 (*) R22 BCSR3R13 

0 R2 21 DBID2 

DBID1 2 

DRMPD2 2 

DBREV1 2 

FPD1 2 

Israel 

DBID2 3 

DRMPD3 3 

RN29 DBREV2 3 

FPD2 3 

0 (*) R23 BCSR3R1 

DBID3 

DBID3 

RN2 

DRMPD4 

10K. 

0 R2 23 

4 

4 

BRE V0 4 

RN3 FPD3 4 

RN4 Title 

DBID4 6 

10K. 

EXTO LI0 6 

BRE V1 6 

10K. FPD4 6 

10K. 

MPC8 66ADS 

0 (*) R21 BCSR3R0 

0 (*) R2 26 DBID4 

DBID5 7 

EXTO LI1 7 

BRE V2 7 

FPD5 7 

BCSR3R0 8 

EXTO LI2 8 

BRE V3 8 

FPD6 8 


0 (*) R2 36 BCSR2R4 

0 R2 18 DBID5 

BCSR3R1 9 

EXTO LI3 9 

BCSR3R13 9 

FPD7 9 

A3 

17-BC SR A 


5 

4 

3 

2 

1 

5 

10 

5 

10 

5 

10 

5 

10 

(*) NOT ASSEMBLED 


M4A3-1 92/96 

1 

GND_0 

14 

108 

GND_1 

24 

GND_2 

36 

GND_3 

37 

GND_4 

50 

GND_5 

GND_6 

64 

73 

GND_7 

GND_8 

84 

95 

GND_9 

GND_10 

136 

GND_11 

109 

123 

GND_12 

GND_13 

4 

GND0 

GND1 

10 GND2 

15 GND3 

21 GND4 

28 GND5 

34 GND6 

39 GND7 

45 

FPD[1..4] 

D D 

BD0 

FPD4 

U36 

BD1 

FPD3 

BD[ 0..15] 

BD2 

FPD2 

BD0 

26 

FPD4 

BD3 

FPD1 

BD1 

BD0 

110 

FPD3 

BD4 

BD2 

BD1 

FPD2 

BD5 

DRMPD4 

BCSR2R4 

30 

BD3 

BD2 

100 

FPD1 

BD6 

DRMPD3 

V3 U3 

BD4 

BD3 

116 

BD7 

DRMPD2 

BD5 

BD4 

RN25 

112 

PCRWb 

BD6 

BD5 

32 

FCS1b 

DRMPD[1..4] 

BD7 

BD6 

10K. 

16 

FCS2b 

BD8 

BD7 

10 

5 

FCS3b 

5 

BD9 

104 

BD8 

FCS4b 

BD8 

DRMPD1 

BD10 

BD9 

18 

FENb 

BD9 

EXT OLI0 

BD11 

BD10 

98 

IRDENb 

BD10 

EXT OLI1 

BD12 

BD11 

28 

FOEb 

BD11 

EXT OLI2 

BD13 

BD12 

102 

LBUFENb 

BD12 

EXT OLI3 

BD14 

BD13 

nnet10 

RAS 1b 

BD13 

DBREV0 EXTOLI[0. .3] 

MODIN2 

22 

22.1 

BD15 

BD14 

nnet11 

R192 

RAS 2b 

BD14 

DBREV1 

MODIN1 

RS T0 

nnet12 

22.1 

RAS1DDb 

BD15 

DBREV2 

RS T1 

4 nnet13 R198 

RAS2DDb 

ABR0 

Rst1 

DRVCNFb 

TM33 

DBREV[0..2] 

ABR1 

PCCVCC1 

A30 

RSEN1b 

A20 

RSEN2b 

A19 

nnet14 

22.1 

DRMA9 

B A29 

nnet15 R195 

DRMA10 

C B A28 

C 

B A27 

BA10 

BA9 

UBUFENb 

V3 U3 

SRESETb 

TPFLD Lb 

HRESE Tb 

NMIb 

SGLAMPb 

HARD-RE SET 

RPORI 

PCCENb 

CLK1 

ETHENb 

BRW2b 

BCE1 Ab 

TPS QELb 

BA[27 ..29] 

BCE2 Ab 

V3 U3 

FCSb 

TAb 

DRMPD1 

DRMCS1b 

DRMPD2 

DRMCS2b 

BCSR2CSb 

BTEAb 

U56 

BCSRCSb 

DRAMENb 

BD0 2 

MODIN 

ETHLOOP 

BD1 Q0 

D0 

47 

BCSR3R0 

3 

BCSR3R1 

nnet2 99 R2 08 

MODCK1 

BD2 

D1 

46 

5 

Q1 

DBID0 

ISPI NTDI 

nnet3 00 0 

MODCK2 

BD3 

D2 

44 

R2 12 

Q2 

6 

DBID1 

ISPT MS 

D3 

43 

0 

Q3 

ISPTCK 

PCVCC0 

OE1 

1 

ISPTDO 

SDRAMEN 

BD4 8 

DBID2 

PCEENb 

BD5 

D4 

41 

9 

Q4 

DBID3 DBID[0..5] 

BD6 Q5 

D5 

40 

11 

DBID4 

PCCVPP0 

BD7 Q6 

D6 

38 

12 

DBID5 

nnet1 

PCCVPP1 

Q7 

D7 

37 

B B 

PCOENb 

OE2 

48 

CS7b 

nnet3 

BD8 13 

BRE V0 

nnet4 

RSTCNFb 

BD9 Q8 

D8 

36 

14 

FPD7 

BD10 Q9 

D9 

35 

16 

FPD6 

CS6b 

nnet6 

BD11 Q10 

D10 

33 

TM37 

SW4 

17 

FPD5 

nnet7 

MODIN2 

Q11 

D11 

32 

TM39 

1 

4 

TM31 

MODIN1 

OE3 

25 

2 

3 

CS5b 

nnet9 

BD12 19 

BRE V1 BRE V[0..3] 

BD13 Q12 

D12 

30 

90HBW02PR 

20 

BCSR3R13 

BD14 Q13 

D13 

29 

22 

BRE V2 

MODCK1-2 

BD15 Q14 

D14 

27 

23 

BRE V3 

Q15 

D15 

26 

OE4 

24 

MODIN2 

MODIN1 

Rst0 

PCR_W 

6 

8 

A30 

9 

10 

A20 

A19 

11 

BA29 

19 

BA10 

17 

12 

NMI~ 

R_PORI 

DRMPD1 

15 

DRMPD2 

7 

20 

F_PD4 

29 

Ras2DD~ 

21 

BA9 

23 

SReset~ 

Modck2 

27 

56 

F_PD1 

57 

Ras2~ 58 

LBUFEn~ 60 

Ras1DD~ 61 

DRVCNF~ 

62 

PccVcc1 

66 

RS_En2~ 

DRMA10 

65 

68 

DramEn~ 70 

DRMA9 

71 

ModemEn~ 

72 

HReset~ 

75 

USBSPD 76 

F_Cs2~ 

F_OE~ 

31 

DRMH_W~ 

77 

PccVpp1 

78 

RSTCNF~ 

33 

UUFEN~ 

38 

39 

F_PD3 

41 

F_Cs1~ 

F_EN~ 

40 

42 

F_Cs3~ 43 

IRD_En~ 44 

F_Cs4~ 45 

F_PD2 

55 

VDOEN~ 

79 

TPFLDL~ 

54 

BR_W2 

47 

CE1A~ 

46 

F_Cs~ 

53 

TA~ 

48 

BCSRCs~ 

80 

VDORST~ 

81 

SGLAMP~ 

82 

PccEn~ 85 

EthEn~ 86 

Ras1~ 

BCSREn~ 

87 

TPSQEL~ 

89 

UsbVcc1 

91 

92 

94 

DRMCs2~ 

93 

ModIn 

DRMCs1~ 

97 

Bcsr3Cs~ 99 

Bcsr2Cs~ 105 

119 

Abr1 

118 

CE2A~ 

Abr0 

120 

125 

BA27 

124 

CLK1 

BA28 

126 

UBUFEn~ 

EthLoop 

128 

PCEEn~ 

127 

129 

PccVpp0 

130 

FCfgEn~ 132 

PCOEn~ 133 

Modck1 

137 

SdramEn~ 

MDM_AUD~ 

134 

138 

VDOEXTCK 

PcVcc0 

140 

142 

RS_En1~ 143 

U40A 

1A1 


3 

22.1 

BD15 

R201 

22.1 

R203 

SW6 

SW5 

3 

3 

22.1 

1 

1 

R197 

2 

2 

SRESET-RED ABORT-BLACK 

UsbVcc0 

144 

111 

BTEA~ 

TM38 

2 

TDI 

34 

TM125 

TMS 

35 

TCK 

107 

TDO 

49 

SPARE_CLK0 

52 

TM32 

SPARE_CLK1 

121 

TM22 

SPARE_CLK2 

103 

SPARE_6 

113 

SPARE_7 

114 

TM29 

SPARE_8 

115 

139 

SPARE_9 

SPARE_10 

141 

SPARE_11 

SPARE_0 

59 

117 

SPARE_12 

SPARE_1 

67 

TM35 

131 

SPARE_13 

SPARE_2 

69 

SPARE_3 

88 

74 

NC 

SPARE_4 

90 

106 

NC0 

SPARE_5 

101 

A5 

1A2 A6 

1A3 B5 

1A4 B6 

2A1 C5 

2A2 C6 

2A3 D5 

2A4 D6 

1OE A3 

2OE A4 

A2 

1Y1 

A1 

B2 

1Y2 

1Y3 

B1 

1Y4 

C2 

2Y1 

C1 

2Y2 

D2 

2Y3 

D1 

2Y4 

3A1 E5 

3A2 E6 

3A3 F5 

3A4 F6 

4A1 G5 

4A2 G6 

4A3 H6 

4A4 H5 

3OE H4 

4OE H3 

E2 

3Y1 

E1 

3Y2 

F2 

3Y3 

F1 

3Y4 

G2 

4Y1 

G1 

4Y2 

H1 

4Y3 

H2 

4Y4 

TM25 

TM26 




VDD3 

42 

VDD2 

31 

VDD1 

18 

VDD0 

7 

C39 

0.1uF 

C40 

0.1uF 

0.1uF 


C38 

C37 

0.1uF 

TM27 

1 

2 

3 

4 

6 

7 

8 

9 

VCC_0 

13 

VCC_1 

25 

VCC_2 

51 

VCC_3 

63 

VCC_4 

83 

VCC_5 

96 

VCC_6 

122 

VCC_7 

135 

V3.3 7, 18,31,42 

GND 4,10, 15,21,28,34,39,45 

V3U3 

C290 

0.1uF 

C298 

0.1uF 

C301 

0.1uF 

C297 

0.1uF 

C283 

0.1uF 

C314 

0.1uF 

C315 

0.1uF 

C312 

0.1uF 

C326 

0.1uF 

V3 U3 

V3 U3 

5 


4 

3 

2 

1

5 

4 

3 

2 


A3 

18-RS232 & CLK A 


1 

MPC86 6ADS 


Herz elia 

Isarel 46120 

Title 

GND 

A A 


INFRA-RED PORT 

R1 

2K 

IRDENb 

IRDRXD 

IRDTXD 

IR DTXD 

IRDRXD 

IRDENb 

0 

R29 

nnet1 91 

IR1 

7 

TxD 

2 

RxD 

6 

SD/MODE 

5 

NC 

1 

NC 

4 

GND 

TFDS60 00 

VCCIN 

3 

A 8 

GND 

nnet1 76 28 

nnet1 69 

C1+ 

V+ 

27 

nnet1 71 

DCD 

nnet1 77 24 

DTROUTb 

C1- 

nnet1 72 

TXDOUTb 

nnet1 78 1 

nnet1 70 

C2+ 

V- 

3 

RXDI Nb 

nnet1 73 

RTSOU Tb 

nnet1 79 2 

DSR INb 

C2- 

RI 

14 

RSTXD2 

T1IN 

T1OUT 

13 

RSTXD2 

12 

T2IN 

T3IN 

nnet1 74 

nnet1 75 

RS RXD2 

Chassis 

VCC 

B RSRXD2 

RSD TR2b 

B 

RSD TR2b 

VCC 

nnet1 92 

V3 U3 

RSEN2b 

Chassis Chassis Chassis Chassis Chassis 

RSEN2b 

25 

C5 

DGND 

MAX3241EC AI 

0.1uF 

nnet1 93 

9 

T2OUT 10 

T3OUT 11 

21 

R1OUTB 

20 

R2OUTB 

19 

R1OUT 

R1IN 

18 

R2OUT 

17 

R3OUT 

16 

R4OUT 

15 

R5OUT 

23 

EN 

4 

R2IN 5 

R3IN 6 

R4IN 7 

R5IN 8 

P2B 

C6 

C69 

BLM18AG121 SN1 

0.1uF 

0.1uF 

L9 

C62 

C2 

0.1uF 

0.1uF 

B9 

B5 

RS232- PORT2 


L5 

4.7uF 

+ C43 0.1uF 

C44 

R2 

10 

B4 

B8 

B3 

B2 

B7 

B6 


L8 

B1 


L11 


L10 

R30 

100 

DECOU PLING 

R27 

2K 

TTL Levels 

RS-232 Levels 

1000pF C56 

1000pF C50 

1000pF C45 

1000pF C46 

"RS-232" 

nnet2 63 

22 

VCC 

RS-232 PHY 

26 

SHDN 

U43 

10K 

R3 

RS232 PORTS 

C C 

V3 U3 V3 U3 



1000pF C55 


nnet1 87 

nnet1 85 

D nnet1 80 

nnet2 80 

D 

DCD 

V3 U3 

nnet1 88 

DT ROUTa 

U53 

nnet1 81 

TXDOUTa 

PLL CLK-DR IVER 

nnet1 89 

nnet1 86 

RXDINa 

nnet2 81 

nnet1 82 

RTSOUTa 

CLKA1 

2 

BSYSC LK1 

nnet2 82 

nnet1 90 

DSRI Na 

CLKA2 

3 

CL K1 

nnet2 83 

BSYSC LK2 

RI 

CLKA3 

14 

nnet2 84 

CLKA4 

15 

BSYSC LK3 

0 R1 66 

RSTXD1 

nnet2 85 

RSTXD1 

BSYSC LK4 

nnet1 83 

SYSC LK 

BLM18AG12 1SN1 

nnet1 84 

RS RXD1 

L12 

Chassis 

CLKOUT 

RSRXD1 

RSD TR1b 

RSD TR1b 

CY2309ZC- 1H 

V3U3 

RSEN1b 

Chassis Chassis 

Chassis Chassis Chassis 

RSEN1b 

CLOCK GENERATOR 

R173 

16 

4 

VCC1 

13 

VCC2 

9 

S1 

1 

REF 

5 

GND1 

12 

GND2 

S2 

28 


10uF 

C1+ 

V+ 

27 

C8 

L1 

24 


C1- 

0.1uF 

1 

L2 

C2+ 

V- 

3 


R1 63 

C3 

C4 

0 R1 46 

2 

L4 

R1 67 0 

0.1uF C2- 

0.1uF 

0 

14 

T1IN 

T1OUT 

8 

13 

T2IN 

CLKB1 

6 

12 


CLKB2 

7 

0 R145 

T3IN 

CLKB3 

10 

L3 

CLKB4 

11 

25 

C9 

DGND 

MAX3241E CAI 

0.1uF 

9 

T2OUT 10 

T3OUT 11 

21 

R1OUTB 

20 

R2OUTB 

19 

18 

R1OUT 

R1IN 

R2OUT 

17 

R3OUT 

16 

R4OUT 

15 

R5OUT 

23 

EN 

4 

R2IN 5 

R3IN 6 

R4IN 7 

R5IN 8 

P2A 

C7 

0.1uF 

A5 

RS232 -PORT2 

A9 

A4 

A8 

A7 

A3 

A2 

A6 

A1 

S1 

S2 

DECOU PLING 

1000pF C57 

1000pF C1 

1000pF C47 

1000pF C48 

1000pF C49 

120pF C21 nnet3 14 

120pF C251 

120pF C249 

120pF C234 

TTL Levels 

RS-232 Levels 

nnet3 15 

nnet3 16 

nnet3 17 

120 pF C255 nnet2 88 100 R168 

120 pF C311 nnet2 89 100 R227 

120 pF C260 nnet2 90 100 

120 pF C294 nnet2 91 100 R200 

120 pF C299 nnet2 92 100 R204 

"RS-232" 

nnet2 62 

22 

VCC 

RS-232 PHY 

26 

SHDN 

2 

+ 

1 

U44 

C22 

C227 0.1 uF 

10K 

R4 

V3 U3 

V3 U3 

V3 U3FR20 

3PI N_FERRITE 

C248 0.0 1uF 

For output signals keep t race lengths 

equal 

5 


4 

3 

2 

1

5 

4 

3 

2 

1 



A3 A 

REF 

GND1 

5 

CLKOUT 

CY2309ZC-1H 

1 

CLKB1 S1 

9 

CLKB2 

CLKB3 

CLKB4 

GND2 

12 

 

16 

16 

6 

7 

10 

11 

MIITXCLK 

6 

7 

10 

11 

REF 

GND1 

5 

CLKOUT 

CY2309ZC-1H 

1 

CLKB1 S1 

9 

CLKB2 

CLKB3 

CLKB4 

GND2 

12 

MII RXCLK 


Herz elia 

Isarel 46120 

Title 

15 

0 R2 41 

A CLKA4 

15 

MIIR XCLK2 


A 

S2 

8 

CLKA4 

S2 

8 

MIITXCLK1 

V3 U3 

MIIR XCLK1 

V3 U3 

0 

R2 42 

2 

3 

14 

CLKA1 

CLKA2 

CLKA3 

VCC1 

VCC2 

4 

13 

0 R240 

2 

3 

14 

CLKA1 

CLKA2 

CLKA3 

VCC1 

VCC2 

4 

13 

MIISE Lb 

MUXSELb 

1K R1 14 


U59 

10uF 


U58 

10uF 

C344 

1 2 

+ 

C342 

1 2 

+ 

C92 

0.1uF 

V3 U3 

V3 U3 

FR22 

C341 0.0 1uF 

V3 U3 

FR23 

R81 

10K 

1K 

R1 64 

C343 0.0 1uF 

VCC 

GND VCC 

IDTQS32X384 

U8 

48 

nnet2 95 

MI ITXD1 

nnet2 94 

31 

PD3 

I3F 

QS33X253 

29 

EF 

MPD3 

ATMTXS OC 

CE1Ab 

25 

YF 

I0F 26 

I1F 27 

I2F 28 

MIITXD2 

EXM ITXD2 

BCE 1Ab 

0.1uF 

39 

40 

43 

44 

47 

12 

24 

B15 

B16 

B17 

B18 

B19 

GND 

EXPCOL 

EXP TXEN 

EXPMD IO 

EXPCRS 

C235 

VCC 

MI ITXD2 

32 

24 

IPASE L0 

IPASE L1 

VCC 

17 

PD4 

MPD4 

ATMTXD7 

CE2Ab 

23 

MI ITXD3 

EXM ITXD3 

MPCCRS 

MPC MDIO 

MPCTXEN 

MPCCOL 

28 

31 

32 

34 

B10 

B11 

B12 

B13 

B14 

BEB 37 

A10 

A11 

29 

A12 

30 

A13 

33 

A14 

35 

A15 

38 

A16 

41 

A17 

42 

A18 

45 

A19 

46 

VCC 36 

MIICRS 

MII MDIO 

MIITXEN 

MIICOL 

3 4 

74AC14D U27-6 

MI ITXD3 

nnet3 12 

B BCE2 Ab 

BED 

27 

26 

B 

25 

39 

10uF 

ED 

ED I3D 37 



31 

I3F 

QS33X253 

29 

EF 

25 

YF 

I0F 26 

I1F 27 

I2F 28 

0.1uF 

C1 72 

32 

24 

17 

23 

I0E 22 

I1E 21 

I2E 20 

I3E 19 

S0EF 30 

S1EF 18 

YE 

EE 

VCC 

GND 

39 

PD5 

33 

YD 

I0D 34 

I1D 35 

I2D 36 

MPD5 

ATMTXD6 

C334 

2 

IPA0 

33 

0.1uF 

BVS1 

ATMRXD0 

MII RXD3 

EXATMRD0 

ATMRXD5 

ATMRXD6 

ATMRXD7 

ATMRXSOC 

14 

17 

18 

21 

22 

B5 

B6 

B7 

B8 

B9 

ATMTXD5 

ATMTXD6 

ATMTXD7 

ATMTXS OC 

V3 U3 

VCC 

MIIRXDV 

PD6 

VCC 

C2 36 

40 

16 

S1CD 10 

GND 

I0D 

YD 

34 

I1D 35 

I2D 36 

I3D 37 

I0E 22 

I1E 21 

I2E 20 

I3E 19 

S0EF 30 

S1EF 18 

YE 

EE 

VCC 

GND 

+ 

1 

C333 0.1 uF 

9 

MPD6 

ATMTXD5 

IPA1 

15 

ATMTXD3 

ATMTXD4 

Near U 42 

C332 0.0 1uF 

MIIRXERR 

ATMRXD0 

ATMRXD1 

ATMRXD2 

ATMRXD3 

ATMRXD4 

2 

5 

6 

9 

10 

B0 

B1 

B2 

B3 

B4 

ATMTXD0 

ATMTXD1 

ATMTXD2 

47 

PD7 

BEA 1 

A0 

3 

A1 

4 

A2 

7 

A3 

8 

A4 

11 

BEC 

A5 

15 

A6 

16 

A7 

19 

A8 

20 

A9 

23 

13 

R76 

10K 

C1 67 

0.1uF 

9 

40 

16 

I0C 14 

I1C 13 

I2C 12 

I3C 11 

S0CD 38 

S1CD 10 

YC 

EC 

VCC 

GND 

47 

EB 

41 

YB 

MPD7 

ATMTXD4 

V3 U3 

IPA2 

41 

U8 

0.1uF 

I3B 45 

I2B 44 

I1B 43 

I0B 42 

10pF 

C338 

0.1uF 

C1 65 

C237 

PD9 0 

VCC 

MI ITXD0 

48 

8 

VCC 

1 

R1 04 

nnet2 55 

7 

1 

48 

8 

I0A 

YA 

EA 

VCC 

GND 

6 

I1A 5 

I2A 4 

I3A 3 

S0AB 46 

S1AB 2 

AT MCKSEL 

MPD9 

nnet2 56 

CLKA2 

CLKA3 

14 

CLKA4 

15 

CLKOUT 

CY2309ZC- 1H 

16 

VCC2 

9 

S1 

1 

REF 

5 

GND1 

12 

GND2 

S2 

8 

CLKB1 

6 

CLKB2 

7 

CLKB3 

10 

CLKB4 

11 

IPA3 

U15 

U25 

7 

BCD2b 

I0A 

ATMRXD3 

YA 

MIIRXD0 

EA 

EXATMRD3 

VCC 

GND 

BWP 

ATMRXD2 

YB 

MII RXD1 

EB 

EXATMRD2 

BVS2 

ATMRXD1 

MII RXD2 

EXATMRD1 

6 

I1A 5 

I2A 4 

I3A 3 

S0AB 46 

S1AB 2 

I3B 45 

I2B 44 

I1B 43 

I0B 42 

I0C 14 

I1C 13 

I2C 12 

I3C 11 

S0CD 38 

YC 

EC 

VCC 

1K 

nnet2 97 

EXATMRD4 

MIIR XCLK2 

C 4 

R91 

VCC1 CLKA1 

2 

I3F 

13 

3 

QS33X253 

C 

29 

31 

EF 

R2 39 

0 

ATMTXC LK 

IPA4 

nnet2 96 

31 

I3F 

QS33X253 

29 

EF 

MII RXD0 

U49 


25 

YF 

0.1uF 

I0F 26 

I1F 27 

I2F 28 


15 

1K 

R1 48 

BCD1b 

ATMRXD4 

31 

EF 

PD10 

25 

YF 

I0F 26 

I1F 27 

I2F 28 

C340 1 2 

10uF 

25 

YF 

+ 

C2 17 

VCC 

GND 

MPD10 

ATMTXE NB 

V3 U3 

32 

24 

0.1uF 

I0F 

QS33X253 

26 

I1F 27 

I2F 28 

I3F 29 

0.1uF 

VCC 

17 

EE 

C1 60 

32 

24 

PDS EL0 

PDS EL1 

IPA5 

MIIRXERR 

EXATMRD5 

BBV D2 

ATMRXD5 

VCC 

VCC 

17 

MIITXE RR 

MIITXE RR 

EXATMRD6 

PD11 

23 

MPD11 

ATMRXENB 

IPA6 

BBV D1 

ATMRXD6 

39 

MIIMDC 

PD12 

33 

I0D 

YD 

ED 

34 

I1D 35 

I2D 36 

I3D 37 

I0E 22 

I1E 21 

I2E 20 

I3E 19 

S0EF 30 

S1EF 18 

YE 

EE 

VCC 

GND 

FR17 

23 

YE 

I0E 22 

I1E 21 

I2E 20 

I3E 19 

S0EF 30 

S1EF 18 

C2 01 

C339 0.0 1uF 

32 

24 

17 

39 

ED 

I0D 34 

I1D 35 

I2D 36 

I3D 37 

23 

10pF 

C3 37 

33 

YD 

39 

C2 18 

0.1uF 

MPD12 

ATMTXD3 

VCC 

C1 61 

0.1uF 

VCC 

40 

16 

MII RXDV 

EXATMRD7 

IPA7 

VCC 

C2 02 

EXATMRSC 

9 

MII RXD1 

BRDY 

ATMRXD7 

MIITXCLK1 

WAIT Ab 

BWAI TAb 

ATMRXSOC 

PD13 

15 

ATMTXD2 

44_to_ pin _45 

47 

MII RXD2 

ALEA 

EB I3B 

D MIR Q7b 

MIITXD1 

D 

MPD13 

IRQ7b 

CHANGED: From_pin 

nnet2 93 

EX MITXD1 

45 

4 

2 

41 

I0B 42 

41 

YB 

0 

47 

I2B 44 

I1B 43 

I0C 14 

I1C 13 

I2C 12 

I3C 11 

S0CD 38 

S1CD 10 

YC 

EC 

VCC 

GND 

CLKA1 

CLKA2 

3 

CLKA3 

14 

CLKA4 

15 

CLKOUT 

CY2309ZC- 1H 

16 

VCC1 

13 

VCC2 

9 

S1 

1 

REF 

5 

12 

GND1 

GND2 

S2 

8 

CLKB1 

6 

CLKB2 

7 

CLKB3 

10 

CLKB4 

11 

33 

40 

16 

9 

1K 

R1 21 

15 

47 

YB 

EB I3B 45 

I2B 44 

I1B 43 

I0C 14 

I1C 13 

I2C 12 

I3C 11 

S0CD 38 

S1CD 10 

YC 

EC 

VCC 

GND 

0.1uF 

I0D 

YD 

ED 

34 

I1D 35 

I2D 36 

I3D 37 

I0E 22 

I1E 21 

I2E 20 

I3E 19 

S0EF 30 

S1EF 18 

YE 

EE 

VCC 

GND 

9 

40 

16 

15 

I0C 14 

I1C 13 

I2C 12 

I3C 11 

S0CD 38 

S1CD 10 

YC 

EC 

VCC 

GND 

EB 

I3B 45 

U48 


R2 38 

C2 19 

0.1uF 

VCC 

MIIR XCLK1 

PDS EL0 

PDS EL1 

R94 

10K 

0.1uF 

BBALEA 

C2 03 

0.1uF 

V3 U3 

MIIMDC 

PD8 

MPD8 

RESETA 

0 

VCC 

nnet2 57 

VCC 

U14 

MPD15 

PD15 

I0A 

7 

ATMTXD0 

YA 

1 

MII RXD3 

EA 

48 

VCC 

8 

GND 

MPD14 

PD14 41 

ATMTXD1 

YB 

6 

I1A 5 

I2A 4 

I3A 3 

S0AB 46 

S1AB 2 

I2B 44 

I1B 43 

I0B 42 

48 

8 

C336 1 2 

10uF 

1 

+ 

C1 62 

7 

I0A 

YA 

EA 

VCC 

GND 

6 

I1A 5 

I2A 4 

I3A 3 

S0AB 46 

S1AB 2 

I0B 42 

FR1 

C335 0.0 1uF 

U22 

R144 

7 

1 

48 

8 

I0A 

YA 

EA 

VCC 

GND 

6 

I1A 5 

I2A 4 

I3A 3 

S0AB 46 

S1AB 2 

BRESETA 

ATMRXCLK 

MI ITXD0 

EXATMRCK 

V3 U3 

R2 43 

0(*) 

U19 

5 


4 

3 

2 

1

5 

4 

3 

2 


A3 

20-ETH ERNET A 


1 

MPC86 6ADS 



Israel 

Title 


A A 

C 

LED_RED 

LD6 

68PF 

A 

nnet56 

VCC 

0.039UF 

C86 

C123 

A C 

R68 

243 

EEST 

nnet59 

nnet60 

nnet57 nnet58 nnet61 

LD1 

LD2 

LD3 

LD4 

LD5 

LED_RED LED _YELLOW LED_RED LED_GREEN LED_GREEN 

A C 

A C 

A C 

10K 

R69 

VCC-7,1 0,11,15,18,30,35,38 

7 

ET HTX 

ET HTX 

U1 

ET ENA 

ET ENA 

nnet51 

1 

LPF 

ET HTCK 

ET HTCK 

nnet3 08 

P1 

8 TP TX 

nnet30 

nnet52 

5 

6 TPTXb 

ETHRX 

E THRX 

nnet29 

TPRX 

ERENA 

ERENA 

nnet28 

nnet53 

3 

LPF 

ETHRCK 

ETHRCK 

nnet27 

R78 0 nnet3 09 

nnet39 

8 

BLUE 

ECLSN 

ECLSN 

nnet26 

R53 

nnet54 

nnet2 98 

R54 

16 LPF 

VCC 

39.1 

39.1 

9 

nnet55 

C 12 

11 TPR Xb 

C 

nnet49 

RJ45_Eth 

ETHE Nb 

ETHE Nb 

nnet48 

14 

LPF 

Chassis 

PE680 26 

nnet33 

nnet47 

10 

nnet35 

nnet46 

nnet34 

TPS QELb 

TPS QELb 

TPFLD Lb 

TPFLD Lb 

nnet45 

ETHLOOP 

E THLOOP 

nnet44 

nnet43 

nnet36 

nnet42 

nnet37 

nnet41 

nnet38 

nnet40 

10K 

B 

R89 

B 

GND-8,13 ,14,19,20,33,34,39,47 

ORANGE 

7 BLACK 

6 RED 

5 GREEN 

4 YELLOW 

3 BROWN 

2 GRAY 

U5 

52 

TX 

ACXb 

21 

49 

TENA 

ACX 

20 

R75 0 

48 

U13 

TCLK 

1 

2 

4 

1A1 1Y1 

18 

R55 

VCC 

1A2 1Y2 

16 

6 

1A3 1Y3 

14 

2 

0 (*) 

RX 

8 

1A4 1Y4 

12 

1 

1G 

1 

RENA 

11 

13 

2A1 2Y1 

9 

2A2 2Y2 

7 

50 

RCLK 

15 

17 

2A3 2Y3 

5 

2A4 2Y4 

3 

51 

CLSN 

13 

CHASSI 

19 

2G 

14 

CHASSI 

GND 

10K 

QS32 44D 

3 

R74 10 

CS0 

4 

CS1 

5 

CS2 

C61 

46 

TPEN 

9 

R38 

APORT 

100 

29 

TPAPCE 

27 

TPSQEL 

28 

TPFULDL 

6 

LOOP 

12 

MFILT 

16 

X1 

17 

R83 

X2 

C138 

294 

R37 

R52 

3900PF 

150 

150 

22 

ATXb 

25 

TPTX 37 

ARX 24 

TPRXb 

31 

RXLED 41 

TXLED 40 

ARXb 

23 

TPRX 32 

ATX 26 

TPTXb 

36 

CLLED 42 

TPLIL 

43 

TPPLR 44 

TPJABB 45 

R90 

1K 

R28 

R42 

R65 

20MHz 

150 

150 

150 



68PF 

C124 

Y1 

A C 

10K 

R9 

0.01uF (*) 


D D2 

D 

4148D 

(*): op tional 

nnet32 

R84 

nnet62 

nnet31 

10K 4. 3V 

MC681 60 

C157 

C 

0.1uF 

1 

2 

3 

4 

6 

7 

8 

9 

A 

R85 

VCC 

10 

5 

R80 

RN7 

10K. 

C137 

C102 

VCC 

10K 

10K 

0.1uF 

0.1uF 

C103 

0.1uF 

C104 

0.1uF 

V3U3 

VCC 

5 


4 

3 

2 

1


Freescale 




Inc. 


APPENDIX B - Programmable Logic Equations 

The MPC86xADS has 3 programmable logic devices on it. Use is done with Lattice - M4A3 - 128/64, Lattice 

- M4 - A3 - 192/96, Altera EPM3128ATC144-10 These devices support the following function on the ADS: 

1) U16 - Debug Port Controller 

2) U36 -The BCSR1-4, auxiliary board control functions, e.g,. buffers control, local interrupter, reset 

logic, etc’. 

3) U37 - BCSR5. Control the ATM & fast ethernet devices and functionality. 





Freescale 




Inc. 

2•0•1 U2 - Debug Port Controller 


"****************************************************************************** 

"* Pda ADS Debug Port Controller. * 

"* Mach controller for an interface between Sun ADI port at one side, to * 

"* debug port at the other. * 

"****************************************************************************** 

"* In this file (9): 

"* - The pinout are changed to the new device M4A3-128/64-55VC 

"****************************************************************************** 


"* - Added support for VFLS / FRZ switching, for both normal operation and 

"* external debug station connected to the FADS. 

"* Support includes: 

"* - separating vfls between MPC and debug port. 

"* - Selection between frz / vfls (default) is done by VflsFrz_B input pin. 

"* - Selection between on-board / off-board vfls/frz is done by ChinS_B coming 

"* from the expansion connectors. 

"* - VFLS(0:1) are driven towards the debug-port connector when board is not 

"* selected, i.e., either ADI is disconnected or addresses don't match. 

"****************************************************************************** 


"* - BundleDelay field in the control register is changed to debug port 

"* clock frquency select according to the following values: 

"* 0 - divide by 8 (1.25 Mhz) 

"* 1 - divide by 4 (2.5 Mhz) 

"* 2 - divide by 2 (5 Mhz) 

"* 3 - divide by 1 (10 Mhz) default. 

"* - Added clock divider for 2 , 4, 8 output of which is routed externaly 

"* to the i/f clock input. 

"****************************************************************************** 


"* - RUN siganl polarity was changed to active-high, this, to support 

"* other changes for revision PILOT of the ads. 

"****************************************************************************** 

"* In this file (5) added: 

"* - protection against spikes on the reset lines, so that the interface 

"* will not be reset by an accidental spike. 

"* - D_C_B signal was synchronized to avoid accidental write to control 

"* during data write. 

"* - DSDI is given value (H) prior to negation of SRESET* to comply with 5XX 

"* family 

"****************************************************************************** 

"* In this file (4) the polarity of address selection lines is reversed so 

"* that ON the switch represent address line at high and vice-versa 

"****************************************************************************** 

"* In this file (3) the IClk is not reseted at all so it can be used to 

"* sync pda reset signals inside. 

"* Added consideration for reset generated by the pda: 

"* - when pda is reset (i.e., its hard | soft reset signals are asserted, 

"* it is not allowed for the host to initiate data trnasfer towards the pda. 

"* It can however, access the control / status register to either change 

"* parameters and / or check for status. 

"* - The status of reset signals is added to the status register, so it can 





Freescale 




Inc. 

"* be polled by the host. 

"****************************************************************************** 


module dbg_prt7 

title 'MPC821ADS Debug Port Controller. 

Originated for Ptec ADS, Shlomo Reches (MSIL) - October 26, 1993 

Modified for Pda ADS, Yair Liebman - (MSIL) - April 04, 1995' 

"****************************************************************************** 

"* Device declaration. * 

"****************************************************************************** 

"U02 device 'mach220a'; 

"****************************************************************************** 

"****************************************************************************** 

"* Pins declaration. * 

"****************************************************************************** 

"ADI Port pins. 

HstReq PIN 32 ; "Host to ADS, write pulse. (IN) 

AdsAck PIN 20 ISTYPE 'reg, buffer'; "ADS to host, write ack. 

"(OUT,3s) 

AdsReq PIN 96 ISTYPE 'reg, buffer'; "ADS to host, write 

"signal. (OUT,3s) 

HstAck PIN 31; "Host to ADS, write ack. (IN) 

AdsHardReset PIN 64; "Host to ADS, Hard reset. (IN) 

AdsSoftReset PIN 36; "Host to ADS, Soft reset. (IN) 

HstEn_B PIN 7; "Host connected to ADS. (IN) 

HostVcc PIN 61; "Host to ADS, host is on. (IN) 

D_C_B PIN 29; "Host to ADS, select data 

"or control access. (IN) 

AdsSel0 PIN 22; 

AdsSel1 PIN 21; 

AdsSel2 PIN 19; "Host to ADS, card addr. (IN) 

AdsAddr0 PIN 18; 

AdsAddr1 PIN 17; 

AdsAddr2 PIN 16; "ADS board address switch. (IN) 

AdsSelect_B NODE ISTYPE 'com, buffer'; "ADS selection indicator. (OUT) 





Freescale 




Inc. 


"****************************************************************************** 

"* MPC pins. Including debug port. * 

"****************************************************************************** 

PdaHardReset_B PIN 48; "Pda's hard reset input. (I/O. o.d.) 

PdaSoftReset_B PIN 5; "Pda's soft reset output. (I/O. o.d.) 

VFLS0 PIN 6 ; 

VFLS1 PIN 15 ; "Debug/Trap mode, report. (IN) 

Freeze PIN 4; "Alternative debug mode report (IN) 

DSCK PIN 30 istype 'com'; "Pda's debug port clock. (Out) 

DSDI PIN 28 istype 'com'; "Pda's debug serial data in (Out) 

DSDO PIN 10; " Pda's debug serial data output (In) 

"****************************************************************************** 

"* Dedicated Debug Port pins. 

"****************************************************************************** 

VflsP0 PIN 70 istype 'com'; 

VflsP1 PIN 59 istype 'com'; 

VflsFrz_B PIN 86; " selectes between VFLS/FRZ from MPC 

"****************************************************************************** 

"* Mach to ADI data bus. * 

"****************************************************************************** 

PD7, 

PD6, 

PD5, 

PD4, 

PD3, 

PD2, 

PD1, 

PD0 PIN 9,46,3,78,80,84,53,55; "ADI data bus.(I/O) 

"****************************************************************************** 

"* Clock gen pins. * 

"****************************************************************************** 

DbgClk PIN 14; "Debug Clock input source. (IN) 

DbgClkOut PIN 72 istype 'com' ; " to be connected to IClk. (out) 

Clk2 PIN 54 istype 'reg, buffer'; "IClk divided by 2 (Out) 

" (Out for testing, may be node) 

IClk PIN 11; " Connected to Clkout externally (In) 

"****************************************************************************** 

"* Misc. 

"****************************************************************************** 

Run PIN 57 istype 'com'; "external indication 

ChinS_B PIN 8; " active (L) when chips is In socket 

"****************************************************************************** 

"****************************************************************************** 

"* Clock genrator Internals: 

"****************************************************************************** 

DbgClkDivBy2 NODE istype 'reg, buffer'; 

DbgClkDivBy4 NODE istype 'reg, buffer'; 

DbgClkDivBy8 NODE istype 'reg, buffer'; " counter (divider) signals. 

Cstr0 NODE istype 'reg, buffer'; 

Cstr1 NODE istype 'reg, buffer'; " Clock Safe Transition Register 





Freescale 




Inc. 


"****************************************************************************** 

"* Reset active. (Active when at least one of the reset sources is active) * 

"****************************************************************************** 

PrimReset NODE istype 'com'; " Primary Reset. Host initiated 

D_PrimReset NODE istype 'com'; " delayed Reset 

DD_PrimReset NODE istype 'com'; " double delayed primary reset. 

Reset NODE istype 'com'; " Interface reset. 

PdaRst NODE istype 'reg, buffer'; " pda continued / initiated. 

" part of the status register. 

"****************************************************************************** 

"* ADS_ACK, ADS_REQ auxiliary internal control signals * 

"****************************************************************************** 

S_HstReqNODE istype 'reg'; "sync. host req. 

DS_HstReqNODE istype 'reg'; " double sync. host req. 

S_D_C_BNODE istype 'reg, buffer'; " synchronized data/ control selection 

S_HstAckNODE istype 'reg, buffer'; " sync host ack 

DS_HstAckNODE istype 'reg, buffer'; " double sync host ack 

BundleDelay1, 

BundleDelay0NODE istype 'reg, buffer'; "delay counter for bundle 

" delay compensation 

BndTmrExpNODE istype 'com';" terminal count for bundle 

" delay timer. 

PDOeNODE istype 'com'; "Mach to ADI data OE. 

PdaHardResetEnNODE istype 'com'; " enables hard reset buffer. 

PdaSoftResetEnNODE istype 'com'; " enables soft reset buffer. 

"****************************************************************************** 

"* Tx Shift Register * 

"****************************************************************************** 

TxReg7, 

TxReg6, 

TxReg5, 

TxReg4, 

TxReg3, 

TxReg2, 

TxReg1, 

TxReg0NODE istype 'reg, buffer'; " Transmit latch and 

" shift register 

"****************************************************************************** 

"* Tx Control Logic * 

"****************************************************************************** 

TxWordLen3, 

TxWordLen2, 

TxWordLen1, 

TxWordLen0NODE istype 'reg, buffer'; " Counter, counts (on fast clock, 

" to gain 1/2 clock resolution) 





" transmission length 

Freescale 




Inc. 

TxWordEndNODE istype 'com'; " Terminal count, sets transmission 

" length. 

TxEnNODE istype 'reg, buffer'; " Transmit Enable. 

TxClkSnsNODE istype 'reg, buffer'; " transmit clock polarity 

"****************************************************************************** 

"* Rx Shift Register * 

"****************************************************************************** 

RxReg0NODE istype 'reg, buffer'; " receive shift register 

" and latch 

"****************************************************************************** 

"* Rx Control Logic * 

"****************************************************************************** 

DsdiEnNODE istype 'reg'; " enables dsdi towards 


"****************************************************************************** 

"* ADI control & status register bits. * 

"****************************************************************************** 

StatusRequest_B NODE istype 'reg, buffer'; "Status request 

DebugEntry_B NODE istype 'reg, buffer'; "Debug enable after reset (L) 

DiagLoopBack_B NODE istype 'reg, buffer'; "diagnostic loopback mode (L) 

DbgClkDivSel0 NODE istype 'reg, buffer'; 

DbgClkDivSel1 NODE istype 'reg, buffer'; " DbgClk division select 

InDebugMode NODE istype 'reg, buffer'; " sync. VFLSs, became pin 

TxError NODE istype 'reg, buffer'; " tx interrupted by pda 

" internal reset. 

"****************************************************************************** 

H, L, X, Z = 1, 0, .X., .Z.; 

C, D, U = .C., .D., .U.; 

"****************************************************************************** 

"* Since all state machines operate at interface clock (IClk) there is no 

"* need to have DbgClk driven during simulation (it will double the number 

"* of vectors required). Therefore, an alternative clock generator was built 

"* with which the 1/2 clock is the 1'st in the chain. 

"* This alternative clock is compiled in if the SIMULATION variable is defined. 

"* If not the original clock generator design is compiled, however simulation 

"* will not pass then. 

"****************************************************************************** 

"* SIMULATION = 1; 

"****************************************************************************** 

"****************************************************************************** 

"* Signal groups 

"****************************************************************************** 

AdsSel = [AdsSel2,AdsSel1,AdsSel0]; 

AdsAddr = [!AdsAddr2,!AdsAddr1,!AdsAddr0]; 

AdsRst = [AdsHardReset, AdsSoftReset]; 

Rst = [PdaHardReset_B, PdaSoftReset_B]; 





ClkOut = [Clk2]; 

DbgClkDiv = [DbgClkDivBy8, DbgClkDivBy4, DbgClkDivBy2]; 

DbgClkDivSel = [DbgClkDivSel1, DbgClkDivSel0]; 

Cstr = [Cstr1, Cstr0]; 

Freescale 




Inc. 


PD = [PD7,PD6,PD5,PD4,PD3,PD2,PD1,PD0]; 

VFLS = [VFLS0, VFLS1]; 

VflsP = [VflsP0,VflsP1]; 

BndDly = [BundleDelay1, BundleDelay0]; "bundle delay 

"compensation timer 

TxReg = [TxReg7..TxReg0]; 

RxReg = [TxReg6,TxReg5,TxReg4,TxReg3,TxReg2,TxReg1,TxReg0,RxReg0]; 

AdiCtrlReg = [DbgClkDivSel1, DbgClkDivSel0, StatusRequest_B, 

DiagLoopBack_B,DebugEntry_B]; 

AdiStatReg = [PdaRst, TxError, InDebugMode, DbgClkDivSel1, DbgClkDivSel0, 

StatusRequest_B, DiagLoopBack_B, DebugEntry_B]; 

TxWordLen = [TxWordLen3, TxWordLen2, TxWordLen1, TxWordLen0]; 

PortEn = [AdsSel2,AdsSel1,AdsSel0,!AdsAddr2,!AdsAddr1,!AdsAddr0, 

HostVcc,HstEn_B]; 

"****************************************************************************** 

"* Select Logic definitions 

"****************************************************************************** 

HOST_VCC_ACTIVE = 1; 

HOST_EN_B_ACTIVE = 0; 

HOST_IS_ON = ((HstEn_B==HOST_EN_B_ACTIVE) & (HostVcc==HOST_VCC_ACTIVE)); 

HOST_IS_OFF = !HOST_IS_ON; 

BOARD_IS_SELECTED = 0; 

ADS_IS_SELECTED = (AdsSelect_B.fb==BOARD_IS_SELECTED) ; 

"Data_Cntrl_B line levels. 

DATA = 1; 

CONTROL = !DATA; 

"****************************************************************************** 

"* Reset Logic definitions 

"****************************************************************************** 

ADS_HARD_RESET_ACTIVE = 1; 

ADS_SOFT_RESET_ACTIVE = 1; 

"****************************************************************************** 

"* Clock Logic definitions 

"****************************************************************************** 

SELECT_CHANGE_ALLOWED = (DbgClkDiv.fb == 0); 

DEBUG_CLOCK_DIV_BY_1 = (Cstr.fb == 0); 




"****************************************************************************** 

"* AdsAck Logic definitions 





Freescale 




Inc. 

"****************************************************************************** 

BUNDLE_DELAY = 2; 


HOST_REQ_ACTIVE = 1; 

ADS_ACK_ACTIVE = 1; "The other state is - !ADS_ACK_ACTIVE 

HOST_ACK_ACTIVE = 1; 

HOST_WRITE_ADI = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 

(DS_HstReq.fb ==HOST_REQ_ACTIVE) & 

(AdsAck==!ADS_ACK_ACTIVE) & 

(HstAck==!HOST_ACK_ACTIVE) ); 

HOST_WRITE_ADI_CONTROL = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 

(DS_HstReq.fb ==HOST_REQ_ACTIVE) & 


(D_C_B==CONTROL) & 

(S_D_C_B.fb == CONTROL) & 


HOST_WRITE_ADI_DATA = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 

(DS_HstReq.fb==HOST_REQ_ACTIVE) & 


(D_C_B==DATA) & 

(S_D_C_B.fb ==DATA) & 


HOST_WRITE_COMPLETE = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 

(DS_HstReq.fb==!HOST_REQ_ACTIVE) & 

(AdsAck==!ADS_ACK_ACTIVE) ); 

"****************************************************************************** 

"* Control & Status register definitions 

"****************************************************************************** 

STATUS_REQUEST= 0; 

DEBUG_ENTRY= 0; 

DIAG_LOOP_BACK= 0; 

IN_DEBUG_MODE = 1; 

TX_DONE_OK= 0; 

TX_INTERRUPTED = !TX_DONE_OK; 

FRZ_SELECTED = 0; 

IS_STATUS_REQUEST = (StatusRequest_B.fb == STATUS_REQUEST); 

DEBUG_MODE_ENTRY = (DebugEntry_B.fb == DEBUG_ENTRY); 

IN_DIAG_LOOP_BACK = (DiagLoopBack_B.fb == DIAG_LOOP_BACK); 

IS_IN_DEBUG_MODE = (InDebugMode.fb == IN_DEBUG_MODE); 

FRZ_IS_SELECTED = (VflsFrz_B == FRZ_SELECTED); 

"****************************************************************************** 





Freescale 




Inc. 

"* DSDI_ENABLE Logic definitions 

"****************************************************************************** 

DSDI_ENABLED = 1; 

DSDI_DISABLED = 0; 

STATE_DSDI_ENABLED = (DsdiEn.fb == DSDI_ENABLED); 

"****************************************************************************** 

"* Tx enable state machine 

"****************************************************************************** 

TX_ENABLED = 1; 

TX_DISABLED = 0; 

STATE_TX_ENABLED = (TxEn.fb == TX_ENABLED); 

STATE_TX_DISABLED = (TxEn.fb == TX_DISABLED); 

TX_WORD_LENGTH = 14; " In 1/2 IClk clocks 

"****************************************************************************** 

"* TxClkSns state machine 

"****************************************************************************** 

TX_ON_RISING = 0; 

TX_ON_FALLING = 1; 

STATE_TX_ON_RISING = (TxClkSns.fb == TX_ON_RISING); 

STATE_TX_ON_FALLING = (TxClkSns.fb == TX_ON_FALLING); 

"****************************************************************************** 

"* AdsReq machine definitions. 

"****************************************************************************** 

ADS_REQ_ACTIVE = 1; "The other state is - !ADS_REQ_ACTIVE 


HOST_READ_ADI = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 

(DS_HstAck.fb==HOST_ACK_ACTIVE) & 

(AdsReq==ADS_REQ_ACTIVE) & 

(HstReq==!HOST_REQ_ACTIVE) ); 

HOST_READ_ADI_DATA = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 


(HstReq==!HOST_REQ_ACTIVE) & 


(D_C_B==DATA) ); 

HOST_READ_ADI_CONTROL = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 




(D_C_B==CONTROL) ); 

ADS_SEND_STATUS = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 

(DS_HstReq.fb == !HOST_REQ_ACTIVE) & 

(D_C_B==CONTROL) & 





Freescale 




Inc. 

(AdsAck==ADS_ACK_ACTIVE) & 

IS_STATUS_REQUEST ); 


"****************************************************************************** 

"* ADI Data Bus definitions 

"****************************************************************************** 

DATA_BUFFERS_ENABLE = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 

(HstAck==HOST_ACK_ACTIVE) & 

(HstReq==!HOST_REQ_ACTIVE) ); 

STATUS_WORD_ON_ADI_BUS = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 



(D_C_B==CONTROL) ); 

READ_DATA_WORD_ON_ADI_BUS = ( (AdsSelect_B.fb==BOARD_IS_SELECTED) & 



(D_C_B== DATA) ); 

"****************************************************************************** 

"* Vfls / Frz select definitions 

"****************************************************************************** 

CHIP_IN_SOCKET = 0; 

CHIP_IS_IN_SOCKET = (ChinS_B == CHIP_IN_SOCKET); 

"****************************************************************************** 

"* Equations, state diagrams. * 

"****************************************************************************** 

"* * 

"* ####### * 

"* # #### # # ## ##### # #### # # #### * 

"* # # # # # # # # # # # ## # # * 

"* ##### # # # # # # # # # # # # # #### * 

"* # # # # # # ###### # # # # # # # # * 

"* # # # # # # # # # # # # ## # # * 

"* ####### ### # #### # # # # #### # # #### * 

"* * 

"****************************************************************************** 

"****************************************************************************** 

"* AdsSelect. * 

"* ADS selection indicator. At low state, when host accesses the ADS. * 

"****************************************************************************** 

equations 

!AdsSelect_B = HOST_IS_ON & (AdsSel==AdsAddr); "AdsAddr is already inverted 

"****************************************************************************** 

"* Internal Logic Reset. 





Freescale 




Inc. 

"****************************************************************************** 

equations 

PrimReset = HOST_IS_OFF # "internal logic reset 

( (AdsHardReset == ADS_HARD_RESET_ACTIVE) & 

(AdsSoftReset ==ADS_SOFT_RESET_ACTIVE) & 

ADS_IS_SELECTED ); 

D_PrimReset = PrimReset.fb; 

DD_PrimReset = D_PrimReset.fb; 


Reset = PrimReset.fb & D_PrimReset.fb & DD_PrimReset.fb;" spike filter 

"****************************************************************************** 

"* Reset PDA. (Connected to PDA hard and reset inputs) Asynchronous. * 

"****************************************************************************** 

equations 

!PdaHardReset_B = H; 

PdaHardReset_B.oe = PdaHardResetEn; "open-drain 

PdaHardResetEn = ADS_IS_SELECTED & 

(AdsHardReset==ADS_HARD_RESET_ACTIVE); 

!PdaSoftReset_B = H; 

PdaSoftReset_B.oe = PdaSoftResetEn; "needs to be open-drain 

PdaSoftResetEn = ADS_IS_SELECTED & 

(AdsSoftReset==ADS_SOFT_RESET_ACTIVE ); 

"****************************************************************************** 

"****************************************************************************** 

"* Clock generator. 

"* All i/f logic works on IClk, which is driven externally by the output 

"* of DbgClk divider. 

"* The debug clock divider is a 3 bit free-running counter, outputs of which 

"* control a 4:1 mux, output of which drives IClk (externally). 

"* Since mux control may change on the fly, a protection logic by means of 

"* 2 bit register is provided, so that mux control is allowed to change 

"* only when all divider outputs are high which assures a falling edge prior 

"* to a rising edge. 

"* Clk2 is infact the source for DSCK and is available outside for debug 

"* purpose. 

"****************************************************************************** 

equations 

DbgClkDiv.clk = DbgClk; 

DbgClkDiv := DbgClkDiv.fb + 1; " free running counter. 





Freescale 




Inc. 


"****************************************************************************** 

"* Clock Safe Transition Register. (CSTR) 

"* The goal of this register is to provide safe clock transitions, i.e., that 

"* a trasition will not cause races over the clockout. E.g., in a transition 

"* between divide by 1 and divide by any bigger order, a possible race may 

"* occur since the divided outputs are delayed with respect to DbgClk. 

"* Therefore, a safe transition may be performed only when all clocks are LOW. 

"****************************************************************************** 

equations 

Cstr.clk = DbgClk; 

"* Cstr.ar = Reset; 

when (SELECT_CHANGE_ALLOWED) then 

Cstr := DbgClkDivSel.fb; 

else 

Cstr := Cstr.fb; 

"****************************************************************************** 

"* Clock selector. 

"* Controlled by the CSTR. 

"****************************************************************************** 

equations 

DbgClkOut.oe = 1; 

when (DEBUG_CLOCK_DIV_BY_1) then 

DbgClkOut = DbgClk; 

else when (DEBUG_CLOCK_DIV_BY_2) then 

DbgClkOut = DbgClkDivBy2.fb; 





"****************************************************************************** 

"* Clk2. 

"* IClk divided by 2 . 

"****************************************************************************** 

equations 

Clk2.clk = IClk; 

ClkOut.oe = 3; 

ClkOut.ar = Reset; 

Clk2 := !Clk2 & HOST_IS_ON; "divide by 2 

"****************************************************************************** 

"* Bundle delay timer. This timer ensures data validity in the following casses: 

"* 1) Host write to adi. In that case AdsAck is ASSERTED only after that timer 

"* expired. 





Freescale 




Inc. 


"* 2) Host read from adi. In that case AdsReq is NEGATED after that timer 

"* expired, ensuring enough time for data propgation over the bundle. 

"* The timer is async reset when both soft and hard reset is applied to the i/f. 

"* The timer is sync. reset a clock after it expires. 

"* Count starts when either HstReq or HstAck are detected asserted 

"* (after proper synchronization) 

"* The value upon which the terminal count is assereted, is in the control 

"* register. When the interface is reset by the host, this value defaults 

"* to its upper bound. Using the diagnostic loop-back mode this value 

"* may be re-established for optimal performance. (by means of test & error) 

"****************************************************************************** 

equations 

BndDly.ar = Reset; 

BndDly.clk = IClk; 

when ( ( (HOST_WRITE_ADI_CONTROL # HOST_READ_ADI_CONTROL ) # 

(HOST_WRITE_ADI_DATA # HOST_READ_ADI_DATA) & !PdaRst.fb) 

& !BndTmrExp.fb) then 

BndDly := BndDly.fb +1; 

else 

BndDly := 0; 

BndTmrExp = (BndDly.fb == BUNDLE_DELAY) & !AdsAck ; "delay field 

"active low. 

"****************************************************************************** 

"* AdsAck. 

"* Host write to ads ack. This state machine generates an automatic ADS_ACK, 

"* during a host to ADS write. 

"* When the host access the ADS data / control register, an automatic 

"* acknowledge is generated, after data has been latched into either the 

"* tx shift register or the control register. 

"* Acknowledge is released when the host removes its write control line. 

"* (HstReq) 

"* 

"* The machine steps through these states : 

"* 0 - !ADS_ACK_ACTIVE 

"* 1 - ADS_ACK_ACTIVE 

"****************************************************************************** 

equations 

AdsAck.clk = IClk; 

AdsAck.ar = Reset; 

AdsAck.oe = ADS_IS_SELECTED; 

S_HstReq.clk = IClk; 

DS_HstReq.clk = IClk; 

S_HstReq := HstReq; 

DS_HstReq := S_HstReq.fb & HstReq;"double synced 





S_D_C_B.clk = IClk;" synchronizing D_C_B selector 

S_D_C_B := D_C_B; 

Freescale 




Inc. 


state_diagram AdsAck 

state !ADS_ACK_ACTIVE: 

if ( (HOST_WRITE_ADI_CONTROL # 

(HOST_WRITE_ADI_DATA & !PdaRst.fb) ) & BndTmrExp.fb) then 

ADS_ACK_ACTIVE 

else 

!ADS_ACK_ACTIVE; 

state ADS_ACK_ACTIVE: 

if ( DS_HstReq.fb==!HOST_REQ_ACTIVE ) then 

!ADS_ACK_ACTIVE 

else 

ADS_ACK_ACTIVE; 

"****************************************************************************** 

"* Transmit Enable logic. 

"* Enables transmit of serial data over DSDI and generation of serial 

"* clock over DSCK. 

"* Transmission begins immediately after data written by the host is latched 

"* into the transmit shift register and ends after 7 shifts were made to the 

"* tx shift register. 

"* Termination is done using a 4 bit counter TxWordLength which has a terminal 

"* count (and reset) TxWordEnd. 

"****************************************************************************** 

equations 

TxEn.ar = Reset; 

TxEn.clk = IClk;" to provide 1/2 clock resolution 

state_diagram TxEn 

state TX_DISABLED: 

if(HOST_WRITE_ADI_DATA & BndTmrExp.fb & !PdaRst.fb) then 

TX_ENABLED 

else 

TX_DISABLED; 

state TX_ENABLED: 

if(TxWordEnd # PdaRst.fb) then 

TX_DISABLED 

else 

TX_ENABLED; 

"****************************************************************************** 

"* Transmit Length Counter. This counter determines the length of transmission 

"* towards the MPC. The fast clock is used here to allow 1/2 clock resolution 

"* with the negation of TxEn, which enables DSCK outside. 

"****************************************************************************** 

equations 

TxWordLen.ar = Reset; 

TxWordLen.clk = IClk; 

TxWordEnd = (TxWordLen.fb == TX_WORD_LENGTH); 





when ( STATE_TX_ENABLED & !TxWordEnd & !PdaRst.fb) then 

TxWordLen.d = TxWordLen.fb + 1; 

else 

TxWordLen.d = 0; 

Freescale 




Inc. 


"****************************************************************************** 

"* TxClkSns - Transmit Clock Sense. 

"* Since Host req is synced acc to IClk and may be detected active when Clk2 is 

"* either '1' or '0', DSCK and the clock according to which DSDI is sent and 

"* DSDO is sampled should be changed. 

"* When TxClkSns is '0' - DSCK will be !Clk2 while transmit will be done 

"* according to Clk2 and recieve by !Clk2. 

"* When TxClkSns is '1' - DSCK will be Clk2 while transmit will be done 

"* according to !Clk2_B and recieve by Clk2. 

"****************************************************************************** 

equations 

TxClkSns.clk = IClk; 

TxClkSns.ar = Reset; 

state_diagram TxClkSns 

state TX_ON_RISING: 

if (HOST_WRITE_ADI_DATA & BndTmrExp.fb & Clk2) then 

TX_ON_FALLING 

else 

TX_ON_RISING; 

state TX_ON_FALLING: 

if (HOST_WRITE_ADI_DATA & BndTmrExp.fb & !Clk2) then 

TX_ON_RISING 

else 

TX_ON_FALLING; 

"****************************************************************************** 

"* Tx shift Register. 

"* 8 bits shift register which either shifts data out (MSB first) or holds 

"* its data. The edge (in Clk2 terms) upon which the above actions are taken, 

"* is determined by TxClkSns. The Tx shift register operates according to IClk. 

"* The Tx shift register is 1'st written by the host (data cycle) and along 

"* with write being acknowledged to the host data is shifted out via DSDI. 

"* 

"* In order of saving logic, the Tx shift register is shared with the Receive 

"* shift register, this, due to the fact that when a bit is shifted out a FF 

"* becomes available. Since the Tx shift register is shifted MSB first, its 

"* LSB FFs are grdualy becoming available for received data. 

"* To provide a 1/2 DSCK hold time for DSDI, a single FF receive SR is used 

"* which is the source for the Tx shift register. (if 0 hold is required 

"* for DSDI this FF may be ommited) 

"****************************************************************************** 

equations 

TxReg.clk = IClk; 





TxReg.ar = Reset; 

Freescale 




Inc. 


when ( HOST_WRITE_ADI_DATA & BndTmrExp.fb & !STATE_TX_ENABLED) then 

[TxReg7..TxReg1] := [PD7..PD1].pin; " latching ADI data 

else when (STATE_TX_ENABLED & STATE_TX_ON_RISING & !Clk2 # 

STATE_TX_ENABLED & STATE_TX_ON_FALLING & Clk2) then 

[TxReg7..TxReg1] := [TxReg6..TxReg0].fb; " shifting out MSB 1'st. 

else 

[TxReg7..TxReg1] := [TxReg7..TxReg1].fb; " Holding value. 

when ( HOST_WRITE_ADI_DATA & BndTmrExp.fb & !STATE_TX_ENABLED) then 

TxReg0 := PD0.pin; 

else when (STATE_TX_ENABLED & STATE_TX_ON_RISING & !Clk2 # 

STATE_TX_ENABLED & STATE_TX_ON_FALLING & Clk2) then 

TxReg0 := RxReg0.fb; 

else 

TxReg0 := TxReg0.fb; 

"****************************************************************************** 

"* Receive Shift Register. 

"* A single stage shift register used as a source for the Tx shift register. 

"* In normal mode the input for the Rx shift register is the pda's DSDO, while 

"* in diagnostic loopback mode, data is taken directly from the Tx shift 

"* serial output. 

"* 

"* The output of the Rx shift register is fed to the input of the Tx shift 

"* register. When transmission (and reception) is done the received data 

"* word is compossed of the Rx shift register (LSB) concatenated with the 

"* 7 LSBs of the Tx shift register. 

"* 

"* The edge (in Clk2 terms) upon which data is shifted in is determined by 

"* TxClkSns as with the Tx shift register but on opposite edges, i.e., 

"* data is shifted Out from the Tx shift register on the Falling edge of 

"* DSCK while is shifted In to the Rx shift register on the Rising edge 

"* DSCK. (DSCK terms are constant in that regard). 

"****************************************************************************** 

equations 

RxReg0.clk = IClk; 

RxReg0.ar = Reset; 

when ( STATE_TX_ENABLED & STATE_TX_ON_RISING & Clk2 # 

STATE_TX_ENABLED & STATE_TX_ON_FALLING & !Clk2) & (!IN_DIAG_LOOP_BACK) then 

RxReg0.d = DSDO; "shift in ext data 

else when ( STATE_TX_ENABLED & STATE_TX_ON_RISING & Clk2 # 

STATE_TX_ENABLED & STATE_TX_ON_FALLING & !Clk2) & IN_DIAG_LOOP_BACK then 

RxReg0.d = TxReg7.fb;" shift in from transmit reg 

else 

RxReg0.d = RxReg0.fb;" hold value 

"****************************************************************************** 





Freescale 




Inc. 


"* AdsReq. 

"* Host from ads, read acknowledge. This state machine generates an automatic 

"* ADS read request from the host when either a byte of data is received in the 

"* Rx shift register or the status request bit in the control register is 

"* active during a previous host write to the control register. 

"* When the host detectes AdsReq asserted, it assertes HstAck in return. HstAck 

"* double synchronized from the ADI port and delayed using the bundle delay 

"* compensation timer to negate AdsReq. When the host detects AdsReq negated 

"* it knows that data is valid to be read. After the host reads the data it 

"* negates HstAck. 

"* The machine steps through these states : 

"* 0 - !ADS_REQ_ACTIVE 

"* 1 - ADS_REQ_ACTIVE 

"****************************************************************************** 

equations 

AdsReq.clk = IClk; 

AdsReq.ar = Reset; 

AdsReq.oe = ADS_IS_SELECTED; 

S_HstAck.clk = IClk; 

DS_HstAck.clk = IClk; 

S_HstAck := HstAck; 

DS_HstAck := HstAck & S_HstAck;"double synced 

state_diagram AdsReq 

state !ADS_REQ_ACTIVE: 

if ( TxEn.fb & TxWordEnd #" end of data shift to PDA 

ADS_SEND_STATUS) then" end of control write and status required 

ADS_REQ_ACTIVE 

else 

!ADS_REQ_ACTIVE; 

state ADS_REQ_ACTIVE: 

if ( HOST_READ_ADI & BndTmrExp.fb ) then 

!ADS_REQ_ACTIVE 

else 

ADS_REQ_ACTIVE; 

"****************************************************************************** 

"* ADI control register. 

"* The ADI control register is written upon host to ADI write with a 

"* D_C_B line is in control mode. It also may be read when StatusRequest_B bit 

"* is active. 

"* 

"* Control register bits description: 

"* 

"* DebugEntry_B: (Bit 0). When this bit is active (L), the pda will enter debug 

"* mode immediately after reset, i.e., DSCK will be held high 

"* after the rising edge of SRESET*. When negated, DSCK will be 

"* held low after the rising edge of SRESET so the pda will start 

"* running instantly. 

"* DiagLoopBack_B: (Bit 1). When active (L), the interface is in Diagnostic 

"*Loopback mode. I.e., the source for the Rx shift register is 





Freescale 




Inc. 


"* the output of the Tx shift register. During that mode, DSCK 

"*and DSDI are tri-stated, so no arbitrary data is sent to the 

"*debug port. When inactive, the interface is in normal mode, 

"*i.e., DSCK and DSDI are driven and the source of the Rx shift 

"*register is DSDO. 

"* StatusRequest_B: (Bit 2). When active (L) any write to the control register 

"*will be followed by a status read cycle initiated by the 

"*debug port controller, i.e., AdsReq will be asserted after 

"*the write cycle ends. When inactive, a write to the control 

"* register will not be followed by a read from status register. 

"* DbgClkDivSel(1:0) : (Bits 4,3). This field selects the division of the 

"* DbgClk input. Division factors are set as follows: 

"* 0 - by 1 

"* 1 - by 2 

"* 2 - by 4 

"*3 - by 8 

"* 

"* Important!!! All bits wake up active (L) after reset. 

"* 

"****************************************************************************** 

equations 

AdiCtrlReg.clk = IClk; 

AdiCtrlReg.ar = Reset;"All active low. 

when ( HOST_WRITE_ADI_CONTROL & BndTmrExp.fb) then 

AdiCtrlReg.d = [PD4.pin, PD3.pin, PD2.pin, PD1.pin, PD0.pin]; 

else 

AdiCtrlReg.d = AdiCtrlReg.fb; 

"****************************************************************************** 

"* ADI Data Bus. 

"* The Adi data bus is driven towards the host when the host reads the i/f. 

"* When D_C_B line is high (data) the Rx shift register contents is driven. If 

"* D_C_B is low (control) the status register contents is driven. 

"* The status register contains all control register's bits (4:0) with the 

"* addition of the following: 

"* 

"* InDebugMode: (Bit 5). When this bit is active (H), the mpc is in debug mode, 

"* i.e., either Freeze or VFLS(0:1) lines are driven high. 

"* When mpc is not in socket, VflsP(0:1) coming from the debug port 

"* are selected. 

"* TxError: (Bit 6). When this bit is active (H), it signals that the pda was 

"* reset (internally) during data transmission. (i.e., data received 

"* during that trnasmission is corrupted). This bit is reset (L) when 

"* either happens: (1) - The interface is reset by the host (both 

"*AdsHardReset and AdsSoftReset are asserted (H) by the host 

"* while the board is selected). (2) - The host writes the interface with 

"* D_C_B signal low (control) and with data bit 6 high. (3) - a new data 

"* word is written to the Tx shift register. (I.e., error is not kept 

"*indefinitely). 

"* PdaRst: (Bit 7). When this bit is active (H), it means that either SRESET* 

"*or HRESET* or both are driven by the pda. The host have to wait until 

"* this bit negates so that data may be wrriten to the debug port. 





Freescale 




Inc. 

"****************************************************************************** 

equations 

PDOe = DATA_BUFFERS_ENABLE ; 

PD.oe = PDOe; 


when ( READ_DATA_WORD_ON_ADI_BUS) then 

PD = RxReg.fb; 

elsewhen ( STATUS_WORD_ON_ADI_BUS ) then 

PD = [PdaRst.fb, TxError.fb, InDebugMode.fb, DbgClkDivSel1.fb, DbgClkDivSel0.fb, 

StatusRequest_B.fb, DiagLoopBack_B.fb, DebugEntry_B.fb ]; 

"****************************************************************************** 

"* Reset Status 

"****************************************************************************** 

PdaRst.clk = IClk; 

PdaRst := (!PdaHardReset_B # !PdaSoftReset_B) & 

(AdsSelect_B.fb==BOARD_IS_SELECTED); " synchronized inside. 

"****************************************************************************** 

"* In debug Mode 

"****************************************************************************** 

InDebugMode.clk = IClk; 

when (FRZ_IS_SELECTED & CHIP_IS_IN_SOCKET) then 

InDebugMode := Freeze; 

else when (!FRZ_IS_SELECTED & CHIP_IS_IN_SOCKET) then 

InDebugMode := (VFLS0 & VFLS1); 

else when (!CHIP_IN_SOCKET) then 

InDebugMode := (VflsP0.pin & VflsP1.pin); 

"****************************************************************************** 

"* TxError. 

"* This bit of the status register is set ('1') when the pda internally resets 

"* during data transmission over the debug port. 

"* When this bit is writen '1' by the adi port (control) the status bit is 

"* cleared. Writing '0' has no influence on that bit. 

"****************************************************************************** 

equations 

TxError.clk = IClk; 

TxError.ar = Reset; 

state_diagram TxError 

state TX_DONE_OK: 

if(STATE_TX_ENABLED & PdaRst.fb) then 

TX_INTERRUPTED 

else 

TX_DONE_OK; 

state TX_INTERRUPTED: 





Freescale 




Inc. 

if (HOST_WRITE_ADI_CONTROL & BndTmrExp.fb & PD6.pin 

# HOST_WRITE_ADI_DATA & BndTmrExp.fb & !PdaRst.fb) then 

TX_DONE_OK 

else 

TX_INTERRUPTED; 

"****************************************************************************** 

"* DSCK. 

"* PDA debug port, gated serial clock. 

"****************************************************************************** 

equations 

DSCK.oe = ADS_IS_SELECTED; 


when ( ADS_IS_SELECTED & !PdaSoftReset_B ) then 

DSCK = H;"debug mode enable 

else when ( ADS_IS_SELECTED & !TxEn.fb & PdaSoftReset_B ) then 

DSCK = !DebugEntry_B.fb;"debug mode direct entry 

else when (ADS_IS_SELECTED & TxEn.fb & STATE_TX_ON_RISING) then 

DSCK = !Clk2;"debug port clock 

else when (ADS_IS_SELECTED & TxEn.fb & STATE_TX_ON_FALLING) then 

DSCK = Clk2;"debug port inverted clock 

else when (!ADS_IS_SELECTED) then 

DSCK = H;"default value, infact X 

"****************************************************************************** 

"* DSDI. 

"* Debug Port Serial Data in. (from Pda). 

"* To provide better hold time for DSDI from the last rising edge of DSCK, 

"* a dedicated enable for DSDI is provided - DSDI_ENABLE. 

"****************************************************************************** 

equations 

DsdiEn.ar = Reset; 

DsdiEn.clk = IClk; 

state_diagram DsdiEn 

state DSDI_DISABLED: 

if(HOST_WRITE_ADI_DATA & BndTmrExp.fb & !PdaRst.fb) then 

DSDI_ENABLED 

else 

DSDI_DISABLED; 

state DSDI_ENABLED: 

if(STATE_TX_DISABLED # PdaRst.fb) then 

DSDI_DISABLED 

else 

DSDI_ENABLED; 

equations 

DSDI.oe = ADS_IS_SELECTED & !IN_DIAG_LOOP_BACK; "avoid junk driven on DSDI input 

"during diagnostic loop back mode. 

when (ADS_IS_SELECTED & !PdaSoftReset_B) then 

DSDI = H; 

else when (ADS_IS_SELECTED & !STATE_DSDI_ENABLED & PdaSoftReset_B ) then 

DSDI = L; 

else when (ADS_IS_SELECTED & STATE_DSDI_ENABLED) then 

DSDI = TxReg7.fb; 





else 

DSDI = L; 

Freescale 




Inc. 

"****************************************************************************** 

"* Debug Port VFLS pins. 

"****************************************************************************** 

equations 

VflsP.oe = !ADS_IS_SELECTED; 

when (!FRZ_IS_SELECTED) then 

VflsP = [VFLS0,VFLS1]; 

else when (FRZ_IS_SELECTED) then 

VflsP = [Freeze,Freeze]; 

"****************************************************************************** 

"* Run Led 

"****************************************************************************** 

Run.oe = H; 

!Run = IS_IN_DEBUG_MODE;"when 1 lits a led. 






Freescale 




Inc. 


2•0•2 U36 - Board Control & Status Register 

"***"*************************************************************************************** 

"* In this file (A): 

"* - 2 files were merged together: bcsr11.abl and brd_ctl13.abl 

"* - First all the history of bcsr11 is described and then all the history of brd_ctl13. 

"* BCSR basis file was bcsr11. Then, brd_ctl13 was added. 

"*************************************************************************************** 

"* History of bcsr11 

"****************************************************************************** 


"* - Added board revision # at BCSR3: 0 ENG 

"* 1 - PILOT. 

"* - Flash Presence detect lines - added FlashPD(7:5). 

"* - Changed polarity of Power-On Reset (now active high) 

"* - DramEn becomes active-low to enhance debug-station support changes. 

"****************************************************************************** 


"* - Board revisiob code @ BCSR3 is changed to 2 - Rev A. 

"****************************************************************************** 


"* - Board revisiob code @ BCSR3 is changed to 3 - Rev B. 

"* - Added RS232En2~ for 2'nd RS232 port. 

"****************************************************************************** 


"* - All status bits (except CntRegEnProtect~) are removed for external buffers. 

"* - Added address line A27 

"* - Added BCSR2CS~ and BCSR3CS~ for external status registers. 

"* - Added controls on bcsr1: 

"* - SdramEn~ 

"* - PccVcc1~ 

"* - Added BCSR4 with following controls: 

"* - UsbFethEn~ (bit 4) enables Usb or Fast Ethernet ports 

"* - UsbSpeed (bit 5) Usb speed control ('1'- full speed) 

"* - UsbVcc0(bit 6) enables VCC for Usb channel 

"* - UsbVcc1 (bit 7) reserved for possible 3.3V usb power 

"* - VideoOn~(bit 8) enables video transceiver 

"* - VideoExtClkEn (bit 9) enables ext 27Mhz clock for video encoder 

"* - VideoRst~(bit 10) resets the video encoder. 

"* - SignaLamp(bit 3) used for s/w signaling to user. 

"****************************************************************************** 


"* - Added ethernet transceiver control signals to BCSR4: 

"* - EthLoop (bit 0) sets the transceiver to internal loopback (H) 

"* - TPFFLDL~ (bit 1) sets the trans. to full-duplex mode. (L) 

"* - TPSQEL~ (bit 2) allows for testing the colission ciruitry 

"* of the 68160. 

"* - ModemEn~ (bit 11) enables the modem tool with the MPC823FADSDB 

"* - Modem_Audio~ (bit 12) selects between modem / audio function for 

"* modem tool with MPC823 daughter board. 

"****************************************************************************** 


"* - Corrected bug with UsbVcc0 and UsbVcc1 - they were writen according to 

"* PccVcc0 and PccVcc1 data bits, instead of UsbVcc0 and UsbVcc1 data bits. 

"* For Eng 823DB it has no influence since the USB power is not operational 

"* there, but for rev Pilot and up 823DB it is important. 

"****************************************************************************** 

"* History of brd_ctl13 

"***************************************************************************** 





Freescale 




Inc. 



"* 1) The use of BCLOSE~ is removed. This due to the assignment 

"* BCLOSE~ to GPL4A. In order of using of GPL4A bit in the upm to determine 

"* data sampling edge, GPL4A may not be used as a GPL. Therefore DramBankXCs~ 

"* must envelope the cycle so that data buffers remain open throughout the 

"* cycle. 

"* 2) Removed CS support for flash configuration. I.e., FlashCs1~ will not be 

"* asserted during hard reset. Flash configuration will be supported on 

"* silicon next revisions. 

"* data buffers will still open for flash configuration when hard reset 

"* asserted and flash configuration option bit, asserted. 

"* 3) Since Bclose~ is no longer available, the data buffers will open 

"* asynchronously. I.e., driven directly by the various chip-selects. 

"* to provide data hold (0) on write cycles to flash, CSNT bit in the OR 

"* should be programmed active, while ACS == 00. 

"****************************************************************************** 

"* In This file (6), A12 and A11 are removed from the flash selection equation 

"* since they can select only a 1/2 Mbyte of flash rather then 2Mbyte selection 

"* needed. Therefore, only one bank of 2 Mbyte flash may be used (MCM29F020). 

"* The rest of the CS are driven high constantly. 

"****************************************************************************** 


"* - Pon Reset Out is removed. Pon Reset is driven directly to MPC. 

"* - Modck0 becomes Modck2 

"* - A9 and A10 replace A11 and A12 in flash bank selection 

"* - Optional BufClose~ is removed. 

"* - DramEn becomes active-low to support debug-station support changes. 

"* - Added F_PD(1:3) to support SMART Flash SIMMs. 

"* - Support for 32KHz crystal - renewed. 

"****************************************************************************** 


"* - Added protection against data contention for write cycles after 

"* Flash read cycle. This is achieved using a state-machine which identifies 

"* end of flash read and a chain of internal gates serving as a delay line. 

"* This kind of solution guaranties a fixed delay over the data buffer enable 

"* signal, that is, only after a flash read cycle. 

"****************************************************************************** 


"* - The addressing scheme of the flash is changed so that the bank does 

"* not occupy a space bigger than its real size. I.e. A9 and A10 use 

"* is conditioned with the module type. 

"****************************************************************************** 

" In this file (10): 

"* - A bug is fixed in Smart flash memories presence detect encoding: 

"* for SM732A1000A - F_PD == 5 (was 2) 

"* for SM732A2000 - F_PD == 4 (was 3) 

"****************************************************************************** 


"* - KAPORIn (power-on reset input) line is removed. It was unused previously. 

"* - Instead of the the above, F_PD4 input is added, so excact identification 

"* may be given to any flash memory. 

"* - Number of delay stages for flash turn-off time protection is decreased 

"* This to avoid possible problem in write to 0-w.s. memories. 

"****************************************************************************** 

"* In This file (12): 

"* - Added ATA support for PCMCIA. I.e., PccEvenEn~ and PccOddEn~ become 

"* identical, enabled by logic OR of CE1~ and CE2~ 

"****************************************************************************** 






Freescale 




Inc. 


"* - A bug is fixed in pcmcia data buffers enables, so that 1'st pcmcia 

"* access after flash read, is not defected anymore. 

"****************************************************************************** 

module bcsr11 

title 'MPC8XXFADS Board Control and Status Register. 

Originated for MPC821ADS, Yair Liebman - (MSIL) - April 14, 1995 

Revised for MC8XXFDAS, Yair Liebman - (MSIL) January 21, 1997' 

"****************************************************************************** 

"* Device declaration. * 

"****************************************************************************** 

"U11 device 'mach220a'; 

"****************************************************************************** 

"****************************************************************************** 

"****************************************************************************** 

"* Pins declaration. * 

"****************************************************************************** 

"* System i/f pins 

"****************************************************************************** 

SYSCLKPIN 124; 

cs5 PIN 117 ; 

cs6 PIN 115; 

cs7 PIN 103; "added haim 

RGPORInPIN 12; 

DriveConfig~PIN 62; 

BrdContRegCs~PIN 48; 

TA~ PIN 53; 

R_W~ PIN 54; 

A27 PIN 125; 

A28 PIN 126; 

A29 PIN 11; 

D0 PIN 26; 

D1 PIN 110; 

D2 PIN 30; 

D3 PIN 100; 

D4 PIN 116; 

D5 PIN 112; 

D6 PIN 32; 

D7 PIN 16; 

D8 PIN 5; 

D9 PIN 104; 

D10 PIN 18; 

D11 PIN 98; 

D12 PIN 28; 

D13 PIN 102; 

D14 PIN 22; 

D15 PIN 3; 

"****************************************************************************** 

"* Board Control Pins. Read/Write. 





Freescale 




Inc. 


"****************************************************************************** 

FlashEn~PIN 40 istype 'reg,buffer'; " flash enable. 

DramEn~PIN 70 istype 'reg,buffer'; " dram enable 

EthEn~PIN 86 istype 'reg,buffer'; " ethernet port enable 

InfRedEn~PIN 44 istype 'reg,buffer'; " infra-red port enable 

FlashCfgEn~PIN 132 istype 'reg,buffer'; " flash configuration enable 

CntRegEn~PIN 87 istype 'reg,buffer'; " control register access enable 

RS232En1~PIN 143 istype 'reg,buffer'; " RS232 port 1 enable 

PccEn~PIN 85 istype 'reg,buffer'; " PCMCIA port enable 

PccVcc0PIN 140 istype 'reg,buffer'; " PCMCIA operation voltage select 0 

PccVpp0PIN 130 istype 'reg,buffer'; " PCMCIA programming voltage select 

PccVpp1PIN 78 istype 'reg,buffer'; " PCMCIA programming voltage select 

HalfWord~PIN 77 istype 'reg,buffer'; " 32/16 bit dram operation select 

RS232En2~PIN 68 istype 'reg,buffer'; " RS232 port 2 enable 

SdramEn~PIN 138 istype 'reg,buffer'; " sdram enable 

PccVcc1PIN 66 istype 'reg,buffer'; " PCMCIA operation voltage select 1 

EthLoop PIN 128 istype 'reg,buffer'; " 68160 internal loop back 

TPFLDL~ PIN 80 istype 'reg,buffer'; " 68160 full-duplex 

TPSQEL~ PIN 89 istype 'reg,buffer'; " 68160 colission circuitry test. 

SignaLamp~PIN 82 istype 'reg,buffer'; " status lamp for misc s/w visual signaling 

UsbFethEn~ PIN 38 istype 'reg,buffer'; " Usb or Fast ethernet port enable 

UsbSpeedPIN 76 istype 'reg,buffer'; " Usb speed control 

UsbVcc0PIN 144 istype 'reg,buffer'; " Usb VCC select 0 line 

UsbVcc1PIN 91 istype 'reg,buffer'; " Usb VCC select 1 line 

VideoOn~PIN 79 istype 'reg,buffer'; " Video encoder enable 

VideoExtClkEn PIN 142 istype 'reg,buffer'; " Enable external clock gen for video encoder 

VideoRst~PIN 81 istype 'reg,buffer'; " Video Encoder reset 

ModemEn~ PIN 75 istype 'reg,buffer'; " modem tool enable for MPC823FADSDB 

Modem_Audio~ PIN 134 istype 'reg,buffer'; " Modem / Audio functions select 

" for modem tool with MPC823 d/b. 

"****************************************************************************** 

"* Board Status Pins. Read only. 

"****************************************************************************** 

"* removed to external buffers 

"****************************************************************************** 

"* Board Status Registers Chip-Selects 

"****************************************************************************** 

Bcsr2Cs~PIN 105 istype 'com'; 

Bcsr3Cs~PIN 99 istype 'com'; 

"****************************************************************************** 

"* Auxiliary Pins. 

"****************************************************************************** 

"****************************************************************************** 

"* Addition Pins from brd_ctl13. 

"****************************************************************************** 

"****************************************************************************** 

"* Flash Associated Pins. 

"****************************************************************************** 

F_PD1 PIN 57; 

F_PD2 PIN 55; 

F_PD3 PIN 41; 

F_PD4 PIN 29; 





FlashCs~ PIN 46;" flash bank chip-select 

Freescale 




Inc. 


FlashCs1~PIN 42 istype 'com';" Flash bank1 chip-select 




FlashOe~PIN 31 istype 'com';" Flash output enable. 

"****************************************************************************** 

"* Dram Associated Pins. 

"****************************************************************************** 

A9 PIN 21; 

A10 PIN 19; 

A19 PIN 10; 

A20 PIN 9; 

A30 PIN 8;" pda address lines inputs (IN) 

SizeDetect1PIN 7; 

SizeDetect0PIN 15; " dram simm size detect lines (IN) 

DramBank1Cs~PIN 97;" 1'st bank chip-select(IN, L) 

DramBank2Cs~PIN 94;" 2'nd bank chip-select (IN, L) 

DramAdd10PIN 65 istype 'com'; 

DramAdd9PIN 71 istype 'com';" dram address lines 

Ras1~ PIN 92 istype 'com'; 

Ras1DD~PIN 61 istype 'com'; 

Ras2~ PIN 58 istype 'com'; 

Ras2DD~PIN 56 istype 'com';" dram RAS lines. 

"****************************************************************************** 

"* Reset & Interrupt Logic Pins. 

"****************************************************************************** 

Rst0 PIN 6; " connected to N.C. of Reset P.B. 

Rst1 PIN 4; " connected to N.O. of Reset P.B. 

HardReset~PIN 72 istype 'com'; " Actual hard reset output (O.D.) 

SoftReset~PIN 23 istype 'com'; " Actual soft reset output (O.D.) 

ResetConfig~PIN 33 istype 'com'; " Drives the RSTCONF* signal of the pda. 

Abr0 PIN 120; " connected to N.C. of Abort P.B. 

Abr1 PIN 119; " connected to N.O. of Abort P.B. 

NMIEn NODE istype 'com'; " enables T.S. NMI pin 

NMI~ PIN 17 istype 'com'; " Actual NMI pin (O.D.) 

"****************************************************************************** 

"* Power On Reset Configuration Support 

"****************************************************************************** 

ModIn PIN 93;" MODCK dip-switch 

Modck2PIN 27 istype 'com';" MODCK2 output 

Modck1PIN 137 istype 'com';" MODCK1 output 

ModckOeNODE istype 'com';" enables MODCKs towards PDA during 

" Hard Reset. 





Freescale 




Inc. 


"****************************************************************************** 

"* Data Buffers Enables and Reset configuration support 

"****************************************************************************** 

TEA~ PIN 111; " Transfer Error Acknowledge. 

PccCE1~PIN 47; 

PccCE2~PIN 118; 

UpperHalfEn~PIN 129 istype 'com,invert'; " bits 0:15 data buffer enable 

LowerHalfEn~PIN 60 istype 'com,invert'; " bits 16:31 data buffer enable 

PccEvenEn~PIN 127 istype 'com,invert'; " pcc upper byte data buffer enable 

PccOddEn~PIN 133 istype 'com,invert'; " pcc lower byte data buffer enable 

PccR_W~PIN 20 istype 'com';" pcmcia data buffers direction 

"****************************************************************************** 

"****************************************************************************** 

"* System Hard Reset Configuration. 

"****************************************************************************** 

ERBNODE istype 'reg,buffer'; " External Arbitration 

IP~NODE istype 'reg,buffer'; " Interrupt Prefix in MSR 

BDISNODE istype 'reg,buffer'; " Boot Disable 

RSV2NODE istype 'reg,buffer'; 

BPS0, 

" reserved config bit 2 

BPS1NODE istype 'reg,buffer'; " Boot Port Size 

RSV6NODE istype 'reg,buffer'; 

ISB0, 

" reserved config bit 6 

ISB1NODE istype 'reg,buffer'; 

DBGC0, 

" Internal Space Base 

DBGC1NODE istype 'reg,buffer'; 

DBPC0, 

" Debug pins Config. 

DBPC1NODE istype 'reg,buffer'; " Debug Port pins Config 

RSV13 NODE istype 'reg,buffer'; " reserved config bit 13 



DataOeNODE istype 'com';" data bus output enable on read. 

"****************************************************************************** 

"* Control Register Enable Protection. 

"****************************************************************************** 

CntRegEnProtect~NODE istype 'reg,buffer'; 

"****************************************************************************** 

"* Control Register Write (space saving) Mach 10 required for 52Mhz 

"****************************************************************************** 

Bcsr0Write~ NODE istype 'com'; 



"****************************************************************************** 





Freescale 




Inc. 


"* Addition from brd_ctl13 

"****************************************************************************** 

"****************************************************************************** 

"* Reset & Interrupt Logic Pins. 

"****************************************************************************** 

RstDeb1NODE istype 'com'; " reset push button debouncer 

AbrDeb1NODE istype 'com'; " abort push button debouncer 

HardResetEnNODE istype 'com'; " enables T.S. hard reset pin 

SoftResetEnNODE istype 'com'; " enables T.S. soft reset pin 

ConfigHold2, 

ConfigHold1, 

ConfigHold0node istype 'reg,buffer';" supplies data hold time for 

" hard reset configuration 

ConfigHoldEndnode istype 'com'; 

"****************************************************************************** 

"* data buffers enable. 

"****************************************************************************** 

SyncHardReset~NODE istype 'reg,buffer';" synchronized hard reset 

DSyncHardReset~ NODE istype 'reg,buffer';" double synchronized hard reset 

SyncTEA~NODE istype 'reg,buffer';" needed since TEA~ is O.D. 

HoldOffConsidered NODE istype 'reg,buffer';" data drive hold-off state 

" machine. 

D_FlashOe~NODE istype 'com';" delayed flash output enable 

DD_FlashOe~NODE istype 'com';" double delayed flash output 

" enable 

TD_FlashOe~NODE istype 'com';" triple delayed flash output 

" enable 

" QD_FlashOe~NODE istype 'com'; quad delayed 

" PD_FlashOe~NODE istype 'com'; penta delayed 

KeepPinsConnected node istype 'com'; 

"****************************************************************************** 

"****************************************************************************** 

H, L, X, Z = 1, 0, .X., .Z.; 

C, D, U = .C., .D., .U.; 

"****************************************************************************** 

"* SIMULATION = 1; 

"* SLOW_PLL_LOCK = 1; 

"* DRAM_8_BIT_OPERATION = 1; 

"****************************************************************************** 

"* Signal groups 

"****************************************************************************** 

Add = [A27,A29]; 

Data = [D0..D15]; 

ConfigReg = [ERB,IP~,RSV2,BDIS, 

BPS0,BPS1,RSV6,ISB0, 

ISB1,DBGC0,DBGC1,DBPC0, 

DBPC1,RSV13,RSV14,RSV15]; 

BPS = [BPS0,BPS1];" boot port size 





ISB = [ISB0,ISB1];" Initial Internal Space Base 

DBGC = [DBGC0,DBGC1];" Debug Pins Configuration 

DBPC = [DBPC0,DBPC1];" Debug port location 

Freescale 




Inc. 


ContReg = [FlashEn~, 

DramEn~,EthEn~,InfRedEn~,FlashCfgEn~, 

CntRegEnProtect~,CntRegEn~,RS232En1~,PccEn~, 

PccVcc0,PccVpp0,PccVpp1,HalfWord~, 

RS232En2~,SdramEn~,PccVcc1,EthLoop, 

TPFLDL~,TPSQEL~,SignaLamp~,UsbFethEn~, 

UsbSpeed,UsbVcc0,UsbVcc1,VideoOn~, 

VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~]; 

ReadBcsr1 = [FlashEn~,DramEn~,EthEn~,InfRedEn~, 

FlashCfgEn~,CntRegEnProtect~.fb,CntRegEn~,RS232En1~, 

PccEn~,PccVcc0,PccVpp0,PccVpp1, 

HalfWord~,RS232En2~,SdramEn~,PccVcc1]; 

ReadBcsr4 = [EthLoop, 


UsbSpeed,UsbVcc0, UsbVcc1 ,VideoOn~, 


DrivenContReg = [FlashEn~,DramEn~,EthEn~,InfRedEn~, 

FlashCfgEn~,CntRegEn~,RS232En1~,PccEn~, 






PccVcc = [PccVcc0,PccVcc1]; 

PccVpp = [PccVpp0,PccVpp1]; 

WideContReg = [FlashEn~, 

DramEn~,EthEn~,InfRedEn~,FlashCfgEn~, 

CntRegEnProtect~,CntRegEn~,RS232En1~,PccEn~, 






Bcsr2_3Cs~ = [Bcsr2Cs~,Bcsr3Cs~]; 

"****************************************************************************** 

"* Addition Signal groups from brd_ctl13 

"****************************************************************************** 

F_PD = [F_PD4, F_PD3, F_PD2, F_PD1]; 

FlashCsOut = [FlashCs4~,FlashCs3~,FlashCs2~,FlashCs1~]; 

PdaAdd = [A9,A10,A19,A20,A30]; 

DramAdd = [DramAdd10,DramAdd9]; 

DramCS~ = [DramBank2Cs~,DramBank1Cs~]; 

Cs = [BrdContRegCs~,FlashCs~ ,DramBank1Cs~,DramBank2Cs~]; 

RAS = [Ras1~,Ras1DD~,Ras2~,Ras2DD~]; 

SD = [SizeDetect1,SizeDetect0]; 

Reset = [HardReset~,SoftReset~]; 

ResetEn = [HardResetEn,SoftResetEn]; 

Rst = [Rst1,Rst0]; 





Freescale 




Inc. 

Abr = [Abr1,Abr0]; 

Debounce = [RstDeb1,AbrDeb1]; 

RstCause = [Rst1,Rst0,Abr1,Abr0,!RGPORIn]; 

ConfigHold =[ConfigHold2, ConfigHold1, ConfigHold0]; 

SyncReset = [SyncHardReset~,DSyncHardReset~]; 

Modck = [Modck2, Modck1]; 

PccCs = [PccCE1~,PccCE2~]; 

LocDataBufEn = [UpperHalfEn~,LowerHalfEn~]; 

PccDataBufEn = [PccEvenEn~,PccOddEn~]; 

ModuleEn = [DramEn~,FlashEn~,PccEn~,CntRegEn~]; 

Stp = [TA~]; 


"****************************************************************************** 

"* Power On Reset definitions 

"****************************************************************************** 

FLASH_CFG_ENABLE = 0; 

K_A_PON_RESET_ACTIVE = 1; 

RESET_CONFIG_ACTIVE = 0; 

"**** changed due to long lock delay of the pda *** 17,7,95 ****************** 

@ifndef SLOW_PLL_LOCK { 

KA_PON_RESET = (RGPORIn == K_A_PON_RESET_ACTIVE); 

} 

@ifdef SLOW_PLL_LOCK { 

PON_DEFAULT_ACTIVE = 0; 

KA_PON_RESET = (PonDefault~ == PON_DEFAULT_ACTIVE); 

} 

"*********** end of change *************** 

RESET_CONFIG_DRIVEN = ((DriveConfig~ == RESET_CONFIG_ACTIVE) & 

(FlashCfgEn~ != FLASH_CFG_ENABLE)); 

"****************************************************************************** 

"* Register Access definitions 

"****************************************************************************** 

CONFIG_REG_ADD = 0; 

CONTROL_REG_1_ADD = 1; 

STATUS_REG2_ADD = 2; 

STATUS_REG3_ADD = 3; 

CONTROL_REG_4_ADD = 4; 

" MPC_WRITE_BCSR_0 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & !A29 & !CntRegEn~); 

" MPC_WRITE_BCSR_1 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & A29 & !CntRegEn~); 

MPC_WRITE_BCSR_3 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & A28 & A29 & !CntRegEn~); 

"MPC_WRITE_BCSR_4 = (!BrdContRegCs~ & !TA~ & !R_W~ & A27 & !A28 & !A29 & !CntRegEn~); 

BCSR_WRITE_ACTIVE = 0; 

MPC_WRITE_BCSR_0 = (Bcsr0Write~.fb == BCSR_WRITE_ACTIVE); 






Freescale 




Inc. 



MPC_READ = (!BrdContRegCs~ & R_W~ & !CntRegEn~); 

MPC_READ_BCSR_0 = (!BrdContRegCs~ & R_W~ & !A27 & !A28 & !A29 & !CntRegEn~); 

MPC_READ_BCSR_1 = (!BrdContRegCs~ & R_W~ & !A27 & !A28 & A29 & !CntRegEn~); 

MPC_READ_BCSR_2 = (!BrdContRegCs~ & R_W~ & !A27 & A28 & !A29 & !CntRegEn~); 

MPC_READ_BCSR_3 = (!BrdContRegCs~ & R_W~ & !A27 & A28 & A29 & !CntRegEn~); 

MPC_READ_BCSR_4 = (!BrdContRegCs~ & R_W~ & A27 & !A28 & !A29 & !CntRegEn~); 

"****************************************************************************** 

"****************************************************************************** 

"* BCSR 0 definitions 

"****************************************************************************** 

"****************************************************************************** 

INTERNAL_ARBITRATION = 0; 

EXTERNAL_ARBITRATION = !INTERNAL_ARBITRATION; 

IP_AT_0xFFF00000 = 0;"active low 

IP_AT_0x00000000 = !IP_AT_0xFFF00000; 

RSV2_ACTIVE = 1; 

BOOT_DISABLE = 1; 

BOOT_ENABLE = !BOOT_DISABLE; 

BOOT_PORT_32 = 0; 



BOOT_PORT_RESERVED = 3; 


INT_SPACE_BASE_0x00000000 = 0; 

INT_SPACE_BASE_0x00F00000 = 1; 

INT_SPACE_BASE_0xFF000000 = 2; 

INT_SPACE_BASE_0xFFF00000 = 3; 

DEBUG_PINS_PCMCIA_2 = 0; 

DEBUG_PINS_WATCH_POINTS = 1; 

DEBUG_PINS_RESREVED = 2; 

DEBUG_PINS_FOR_SHOW = 3; 

DEBUG_PORT_ON_JTAG = 0; 

DEBUG_PORT_NON_EXISTANT = 1; 

DEBUG_PORT_RESERVED = 2; 

DEBUG_PORT_ON_DEBUG_PINS = 3; 




"*********************************************** 





"******* Power On Defaults Assignments ********* 

"*********************************************** 

ERB_PON_DEFAULT = INTERNAL_ARBITRATION; 

IP~_PON_DEFAULT = IP_AT_0x00000000; 

RSV2_PON_DEFAULT = !RSV2_ACTIVE; 

BDIS_PON_DEFAULT = BOOT_ENABLE; 

BPS_PON_DEFAULT = BOOT_PORT_32; 


ISB_PON_DEFAULT = INT_SPACE_BASE_0xFF000000; 

DBGC_PON_DEFAULT = DEBUG_PINS_PCMCIA_2; 

DBPC_PON_DEFAULT = DEBUG_PORT_ON_JTAG; 




"******************************************* 

"******* Data Bits Assignments ************* 

"******************************************* 

ERB_DATA_BIT = [D0]; 

IP~_DATA_BIT = [D1]; 

RSV2_DATA_BIT = [D2]; 

BDIS_DATA_BIT = [D3]; 

BPS_DATA_BIT = [D4,D5]; 


ISB_DATA_BIT = [D7,D8]; 

DBGC_DATA_BIT = [D9,D10]; 

DBPC_DATA_BIT = [D11,D12]; 




Freescale 




Inc. 


"****************************************************************************** 

"****************************************************************************** 

"* BCSR 1 definitions. 

"****************************************************************************** 

"****************************************************************************** 

HALF_WORD = 0; 

ETH_ENABLED = 0; 

DRAM_ENABLED = 0; 

CONT_REG_ENABLE = 0; 

RS232_1_ENABLE = 0; 





RS232_2_ENABLE = 0; 

PCC_ENABLE = 0; 

PCC_VCC_CONT_0 = 0; 

PCC_VCC_CONT_1 = 1; 

" PCC_VPP_0 = 0; 

" PCC_VPP_12 = 2; 

" PCC_VPP_5 = 1; 

" PCC_VPP_TS = 3; 

PCC_VPP0 = 1; 

PCC_VPP1 = 1; 

FLASH_ENABLED = 0; 

INF_RED_ENABLE = 0; 

Freescale 




Inc. 

"* FLASH_CFG_ENABLE = 0; needed to be defined ealier 

DRAM_5V = 0; 

DRAM_3V = !DRAM_5V; 

CNT_REG_EN_PROTECT = 0; " inadvertant write protect 

SDRAM_ENABLED = 1; 

"*********************************************** 


"*********************************************** 

FLASH_ENABLE_PON_DEFAULT = FLASH_ENABLED; 

FLASH_CFG_ENABLE_PON_DEFAULT = !FLASH_CFG_ENABLE; 

DRAM_ENABLE_PON_DEFAULT = DRAM_ENABLED; 

ETH_ENABLE_PON_DEFAULT = !ETH_ENABLED; 

CONT_REG_ENABLE_PON_DEFAULT = CONT_REG_ENABLE; 

RS232_1_ENABLE_PON_DEFAULT = !RS232_1_ENABLE; 

RS232_2_ENABLE_PON_DEFAULT = !RS232_2_ENABLE; 

PCC_ENABLE_PON_DEFAULT = !PCC_ENABLE; 

PCC_VCC_0_PON_DEFAULT = PCC_VCC_CONT_0; 

PCC_VCC_1_PON_DEFAULT = PCC_VCC_CONT_0; 


PCC_VPP0_PON_DEFAULT = PCC_VPP0; 

PCC_VPP1_PON_DEFAULT = PCC_VPP1; " T.S. as default 

INF_RED_ENABLE_PON_DEFAULT = !INF_RED_ENABLE; 

HALF_WORD_PON_DEFAULT = !HALF_WORD; 

SDRAM_ENABLE_PON_DEFAULT = SDRAM_ENABLED; 





Freescale 




Inc. 

CNT_REG_EN_PROTECT_PON_DEFAULT = CNT_REG_EN_PROTECT; 

"******************************************* 


"******************************************* 

FLASH_ENABLE_DATA_BIT = [D0]; 

DRAM_ENABLE_DATA_BIT = [D1]; 

ETH_ENABLE_DATA_BIT = [D2]; 

INF_RED_ENABLE_DATA_BIT = [D3]; 

FLASH_CFG_ENABLE_DATA_BIT = [D4]; 

CNT_REG_EN_PROTECT_DATA_BIT = [D5]; 

CONT_REG_ENABLE_DATA_BIT = [D6]; 

RS232_1_ENABLE_DATA_BIT = [D7]; 

PCC_ENABLE_DATA_BIT = [D8]; 

PCC_VCC_0_DATA_BIT = [D9]; 

PCC_VPP0_DATA_BIT = [D10]; 

PCC_VPP1_DATA_BIT = [D11]; 

HALF_WORD_DATA_BIT = [D12]; 

RS232_2_ENABLE_DATA_BIT = [D13]; 

SDRAM_ENABLE_DATA_BIT = [D14]; 

PCC_VCC_1_DATA_BIT = [D15]; 


"****************************************************************************** 

"****************************************************************************** 

"* BCSR 4 definitions. 

"****************************************************************************** 

"****************************************************************************** 

ETH_LOOP = 1; 

ETH_FULL_DUP = 0; 

ETH_CLSN_TEST = 0; 

SIGNAL_LAMP_ON = 0; 

USB_FETH_ENABLED = 0; 

USB_FULL_SPEED = 1; 

USB_VCC_CONT_0 = 0; 

VIDEO_ENABLED = 0; 

VIDEO_EXT_CLK_ENABLED = 1; 

VIDEO_RESET_ACTIVE = 0; 

MODEM_ENABLED_FOR_823 = 0; 

MODEM = 1; 

"*********************************************** 


"*********************************************** 

ETH_LOOP_PON_DEFAULT = !ETH_LOOP; 

ETH_FULL_DUP_PON_DEFAULT = !ETH_FULL_DUP; 

ETH_CLSN_TEST_PON_DEFAULT = !ETH_CLSN_TEST; 

SIGNAL_LAMP_PON_DEFAULT = !SIGNAL_LAMP_ON; 

USB_FETH_EN_PON_DEFAULT = !USB_FETH_ENABLED; 





Freescale 




Inc. 


USB_SPEED_PON_DEFAULT = USB_FULL_SPEED; 

USB_VCC_0_CONT_PON_DEFAULT = !USB_VCC_CONT_0; 

USB_VCC_1_CONT_PON_DEFAULT = !USB_VCC_CONT_0; 

VIDEO_ENABLE_PON_DEFAULT = !VIDEO_ENABLED; 

VIDEO_EXT_CLK_EN_PON_DEFAULT = !VIDEO_EXT_CLK_ENABLED; 

VIDEO_RESET_PON_DEFAULT = !VIDEO_RESET_ACTIVE; 

MODEM_ENABLE_PON_DEFAULT = !MODEM_ENABLED_FOR_823; 

MODEM_FUNC_SEL_PON_DEFAULT = MODEM; 

"******************************************* 


"******************************************* 

ETH_LOOP_DATA_BIT = [D0]; 

ETH_FULL_DUP_DATA_BIT = [D1]; 

ETH_CLSN_TEST_DATA_BIT = [D2]; 

SIGNAL_LAMP_DATA_BIT = [D3]; 

USB_FETH_EN_DATA_BIT = [D4]; 

USB_SPEED_DATA_BIT = [D5]; 

USB_VCC_0_DATA_BIT = [D6]; 

USB_VCC_1_DATA_BIT = [D7]; 

VIDEO_ENABLE_DATA_BIT = [D8]; 

VIDEO_EXT_CLK_EN_DATA_BIT = [D9]; 

VIDEO_RESET_DATA_BIT = [D10]; 

MODEM_ENABLE_DATA_BIT = [D11]; 

MODEM_FUNC_SEL_DATA_BIT = [D12]; 

"********************************************************** 

"******* Addition declarations from brd_ctl13 ************* 

"********************************************************** 

"**************************************** 

"******* Flash declarations ************* 

"**************************************** 

FLASH_ENABLE_ACTIVE = 0; 

FLASH_ACTIVE = (FlashEn~ == FLASH_ENABLE_ACTIVE); 

MCM29020 = (F_PD == 8); 

MCM29040 = (F_PD == 7); 

MCM29080 = (F_PD == 6); 

SM732A1000A = (F_PD == 5); 

SM732A2000 = (F_PD == 4); 

FLASH_BANK1 = ( (MCM29020 # SM732A1000A) # 

(MCM29040 & !A10) # 

(MCM29080 & !A9 & !A10) # 

(SM732A2000 & !A9) ); 

FLASH_BANK2 = ( (MCM29040 & A10) # 

(MCM29080 & !A9 & A10) # 

(SM732A2000 & A9) ); 

FLASH_BANK3 = (A9 & !A10 & MCM29080); 

FLASH_BANK4 = (A9 & A10 & MCM29080); 





"**************************************** 

"******* DRAM declarations ************* 

"**************************************** 

DRAM_ENABLE_ACTIVE = 0; 

DRAM_ACTIVE = (DramEn~ == DRAM_ENABLE_ACTIVE); 

SIMM36100 = (SD == 0); 

SIMM36200 = (SD == 3); 

SIMM36400 = (SD == 2); 

SIMM36800 = (SD == 1); 

IS_HALF_WORD = (HalfWord~ == 0); 

Freescale 




Inc. 


"****************************************************************************** 

"* Reset Declarations. 

"****************************************************************************** 

KEEP_ALIVE_PON_RESET_ACTIVE = 0; 

REGULAR_PON_RESET_ACTIVE = 0; 

HARD_RESET_ACTIVE = 0; 

SOFT_RESET_ACTIVE = 0; 

HARD_CONFIG_HOLD_VALUE = 4; 

DRIVE_MODCK_TO_PDA = (HardReset~ == HARD_RESET_ACTIVE);" have modck stable 

" during hard reset. 

REGULAR_POWER_ON_RESET = (!RGPORIn == REGULAR_PON_RESET_ACTIVE); "add haim 

HARD_RESET_ASSERTED = (SyncHardReset~.fb == HARD_RESET_ACTIVE); 

HARD_RESET_NEGATES = ( (SyncHardReset~.fb != HARD_RESET_ACTIVE ) 

& (DSyncHardReset~.fb == HARD_RESET_ACTIVE)); 

" detecting hard reset negation 

"****************************************************************************** 

"* data buffers enable. 

"****************************************************************************** 

BUFFER_DISABLED = 1; 

BUFFER_ENABLED = !BUFFER_DISABLED; 

CONTROL_REG_ENABLE_ACTIVE = 0; 

FLASH_CONFIG_ENABLED_ACTIVE = 0; 

PCMCIA_ENABLE_ACTIVE = 0; 

GPL_ACTIVE = 0; 

TEA_ASSERTS = (!TEA~ & SyncTEA~.fb);" first clock of TEA~ asserted 

CONTROL_REG_ENABLED = (CntRegEn~ == CONTROL_REG_ENABLE_ACTIVE); 

FLASH_CONFIGURATION_ENABLED = (FlashCfgEn~ == FLASH_CONFIG_ENABLED_ACTIVE); 

PCC_ENABLED = (PccEn~ == PCMCIA_ENABLE_ACTIVE); 

NO_HOLD_OFF = 0; 





HOLD_OFF_CONSIDERED = 1; 

Freescale 




Inc. 


STATE_HOLD_OFF_CONSIDERED = (HoldOffConsidered.fb == HOLD_OFF_CONSIDERED); 

STATE_NO_HOLD_OFF = (HoldOffConsidered.fb == NO_HOLD_OFF); 

END_OF_FLASH_READ = !TA~ & !FlashCs~ & R_W~;" end of flash read cycle. 

END_OF_OTHER_CYCLE = (!TA~ & FlashCs~ # " another access or 

!TA~ & !FlashCs~ & !R_W~); " flash write 

"* HOLD_OFF_PERIOD = (!R_W~ & !PD_FlashOe~.fb); 

HOLD_OFF_PERIOD = (!R_W~ & !TD_FlashOe~.fb); 

"****************************************************************************** 

"* Equations, state diagrams. * 

"****************************************************************************** 

"* * 

"* ####### * 

"* # #### # # ## ##### # #### # # #### * 

"* # # # # # # # # # # # ## # # * 

"* ##### # # # # # # # # # # # # # #### * 

"* # # # # # # ###### # # # # # # # # * 

"* # # # # # # # # # # # # ## # # * 

"* ####### ### # #### # # # # #### # # #### * 

"* * 

"****************************************************************************** 

"* Configuration Register. 

"* Gets its default pon reset values which are driven to the data bus when 

"* during hard reset configuration. 

"* If other values are required, this register may be written with new values 

"* to become active for the next hard reset. 

"* The state machines are built in a way that its power on value is changed in 

"* one place - the declarations area. 

"****************************************************************************** 

equations 

@ifdef SLOW_PLL_LOCK { 

} 

!PonDefault~ = !DriveConfig~ # 

RGPORIn; 

!Bcsr0Write~ = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & !A29 & !CntRegEn~); 

!Bcsr1Write~ = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & A29 & !CntRegEn~); 

!Bcsr4Write~ = (!BrdContRegCs~ & !TA~ & !R_W~ & A27 & !A28 & !A29 & !CntRegEn~); 

ConfigReg.clk = SYSCLK; 

state_diagram ERB 

state INTERNAL_ARBITRATION: 

if (MPC_WRITE_BCSR_0 & 

(ERB_DATA_BIT.pin == EXTERNAL_ARBITRATION) & 

(!KA_PON_RESET # (ERB_PON_DEFAULT != INTERNAL_ARBITRATION)) # 

(KA_PON_RESET & (ERB_PON_DEFAULT == EXTERNAL_ARBITRATION)) ) then 





Freescale 




Inc. 


EXTERNAL_ARBITRATION 

else 

INTERNAL_ARBITRATION; 

state EXTERNAL_ARBITRATION: 


(ERB_DATA_BIT.pin == INTERNAL_ARBITRATION) & 

(!KA_PON_RESET # (ERB_PON_DEFAULT != EXTERNAL_ARBITRATION)) # 

(KA_PON_RESET & (ERB_PON_DEFAULT == INTERNAL_ARBITRATION)) ) then 

INTERNAL_ARBITRATION 

else 

EXTERNAL_ARBITRATION; 

"****************************************************************************** 

state_diagram IP~ 

state IP_AT_0xFFF00000: 


(IP~_DATA_BIT.pin == IP_AT_0x00000000) & 

(!KA_PON_RESET # (IP~_PON_DEFAULT != IP_AT_0xFFF00000)) # 

(KA_PON_RESET & (IP~_PON_DEFAULT == IP_AT_0x00000000)) ) then 

IP_AT_0x00000000 

else 

IP_AT_0xFFF00000; 

state IP_AT_0x00000000: 


(IP~_DATA_BIT.pin == IP_AT_0xFFF00000) & 

(!KA_PON_RESET # (IP~_PON_DEFAULT != IP_AT_0x00000000)) # 

(KA_PON_RESET & (IP~_PON_DEFAULT == IP_AT_0xFFF00000)) ) then 

IP_AT_0xFFF00000 

else 

IP_AT_0x00000000; 

"****************************************************************************** 

state_diagram RSV2 

state !RSV2_ACTIVE: 


(RSV2_DATA_BIT.pin == RSV2_ACTIVE) & 

(!KA_PON_RESET # (RSV2_PON_DEFAULT != !RSV2_ACTIVE)) # 

(KA_PON_RESET & (RSV2_PON_DEFAULT == RSV2_ACTIVE)) ) then 

RSV2_ACTIVE 

else 

!RSV2_ACTIVE; 

state RSV2_ACTIVE: 


(RSV2_DATA_BIT.pin == !RSV2_ACTIVE) & 

(!KA_PON_RESET # (RSV2_PON_DEFAULT != RSV2_ACTIVE)) # 

(KA_PON_RESET & (RSV2_PON_DEFAULT == !RSV2_ACTIVE)) ) then 

!RSV2_ACTIVE 

else 

RSV2_ACTIVE; 

"****************************************************************************** 

state_diagram BDIS 

state BOOT_ENABLE: 


(BDIS_DATA_BIT.pin == BOOT_DISABLE) & 

(!KA_PON_RESET # (BDIS_PON_DEFAULT != BOOT_ENABLE)) # 

(KA_PON_RESET & (BDIS_PON_DEFAULT == BOOT_DISABLE)) ) then 

BOOT_DISABLE 

else 

BOOT_ENABLE; 

state BOOT_DISABLE: 






Freescale 




Inc. 


(BDIS_DATA_BIT.pin == BOOT_ENABLE) & 

(!KA_PON_RESET # (BDIS_PON_DEFAULT != BOOT_DISABLE)) # 

(KA_PON_RESET & (BDIS_PON_DEFAULT == BOOT_ENABLE)) ) then 

BOOT_ENABLE 

else 

BOOT_DISABLE; 

"****************************************************************************** 

state_diagram BPS 

state BOOT_PORT_32: 


(BPS_DATA_BIT.pin == BOOT_PORT_8) & 

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_32)) # 

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_8)) ) then 

BOOT_PORT_8 

else if (MPC_WRITE_BCSR_0 & 




BOOT_PORT_16 


(BPS_DATA_BIT.pin == BOOT_PORT_RESERVED) & 


(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_RESERVED)) ) then 

BOOT_PORT_RESERVED 

else 

BOOT_PORT_32; 






BOOT_PORT_32 





BOOT_PORT_16 






else 

BOOT_PORT_8; 






BOOT_PORT_32 





BOOT_PORT_8 









Freescale 




Inc. 



else 

BOOT_PORT_16; 

state BOOT_PORT_RESERVED: 



(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_RESERVED)) # 


BOOT_PORT_32 





BOOT_PORT_16 





BOOT_PORT_8 

else 

BOOT_PORT_RESERVED; 

"****************************************************************************** 







RSV6_ACTIVE 

else 

!RSV6_ACTIVE; 






!RSV6_ACTIVE 

else 

RSV6_ACTIVE; 

"****************************************************************************** 

state_diagram ISB 

state INT_SPACE_BASE_0x00000000: 


(ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00F00000) & 

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00000000)) # 

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00F00000)) ) then 

INT_SPACE_BASE_0x00F00000 


(ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFF000000) & 


(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFF000000)) ) then 

INT_SPACE_BASE_0xFF000000 


(ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFFF00000) & 


(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFFF00000)) ) then 

INT_SPACE_BASE_0xFFF00000 

else 





INT_SPACE_BASE_0x00000000; 

Freescale 




Inc. 


state INT_SPACE_BASE_0x00F00000: 


(ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00000000) & 

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00F00000)) # 

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00000000)) ) then 

INT_SPACE_BASE_0x00000000 











else 

INT_SPACE_BASE_0x00F00000; 

state INT_SPACE_BASE_0xFF000000: 



(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFF000000)) # 













else 

INT_SPACE_BASE_0xFF000000; 

state INT_SPACE_BASE_0xFFF00000: 



(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFFF00000)) # 













else 

INT_SPACE_BASE_0xFFF00000; 

"****************************************************************************** 





Freescale 




Inc. 


state_diagram DBGC 

state DEBUG_PINS_PCMCIA_2: 


(DBGC_DATA_BIT.pin == DEBUG_PINS_WATCH_POINTS) & 

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_PCMCIA_2)) # 

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_WATCH_POINTS)) ) then 

DEBUG_PINS_WATCH_POINTS 


(DBGC_DATA_BIT.pin == DEBUG_PINS_RESREVED) & 


(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_RESREVED)) ) then 

DEBUG_PINS_RESREVED 


(DBGC_DATA_BIT.pin == DEBUG_PINS_FOR_SHOW) & 


(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_FOR_SHOW)) ) then 

DEBUG_PINS_FOR_SHOW 

else 

DEBUG_PINS_PCMCIA_2; 

state DEBUG_PINS_WATCH_POINTS: 


(DBGC_DATA_BIT.pin == DEBUG_PINS_PCMCIA_2) & 

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_WATCH_POINTS)) # 

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_PCMCIA_2)) ) then 

DEBUG_PINS_PCMCIA_2 











else 

DEBUG_PINS_WATCH_POINTS; 

state DEBUG_PINS_RESREVED: 



(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_RESREVED)) # 













else 

DEBUG_PINS_RESREVED; 

state DEBUG_PINS_FOR_SHOW: 






Freescale 




Inc. 



(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_FOR_SHOW)) # 













else 

DEBUG_PINS_FOR_SHOW; 

"****************************************************************************** 

state_diagram DBPC 

state DEBUG_PORT_ON_JTAG: 


(DBPC_DATA_BIT.pin == DEBUG_PORT_NON_EXISTANT) & 

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_JTAG)) # 

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_NON_EXISTANT)) ) then 

DEBUG_PORT_NON_EXISTANT 


(DBPC_DATA_BIT.pin == DEBUG_PORT_RESERVED) & 


(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_RESERVED)) ) then 

DEBUG_PORT_RESERVED 


(DBPC_DATA_BIT.pin == DEBUG_PORT_ON_DEBUG_PINS) & 


(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_DEBUG_PINS)) ) then 

DEBUG_PORT_ON_DEBUG_PINS 

else 

DEBUG_PORT_ON_JTAG; 

state DEBUG_PORT_NON_EXISTANT: 


(DBPC_DATA_BIT.pin == DEBUG_PORT_ON_JTAG) & 

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_NON_EXISTANT)) # 

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_JTAG)) ) then 

DEBUG_PORT_ON_JTAG 











else 

DEBUG_PORT_NON_EXISTANT; 

state DEBUG_PORT_RESERVED: 







Freescale 




Inc. 


(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_RESERVED)) # 













else 

DEBUG_PORT_RESERVED; 

state DEBUG_PORT_ON_DEBUG_PINS: 



(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_DEBUG_PINS)) # 













else 

DEBUG_PORT_ON_DEBUG_PINS; 

"****************************************************************************** 







RSV13_ACTIVE 

else 

!RSV13_ACTIVE; 






!RSV13_ACTIVE 

else 

RSV13_ACTIVE; 

"****************************************************************************** 










Freescale 




Inc. 



RSV14_ACTIVE 

else 







!RSV14_ACTIVE 

else 

RSV14_ACTIVE; 

"****************************************************************************** 







RSV15_ACTIVE 

else 







!RSV15_ACTIVE 

else 

RSV15_ACTIVE; 

"****************************************************************************** 

"****************************************************************************** 

"* BCSR 1 

"****************************************************************************** 

"****************************************************************************** 

equations 

WideContReg.clk = SYSCLK; 

DrivenContReg.oe = ^hfffffff; 

state_diagram FlashEn~ 

state FLASH_ENABLED: 


(FLASH_ENABLE_DATA_BIT.pin == !FLASH_ENABLED) & 

(!KA_PON_RESET # (FLASH_ENABLE_PON_DEFAULT != FLASH_ENABLED)) # 

(KA_PON_RESET & (FLASH_ENABLE_PON_DEFAULT == !FLASH_ENABLED)) ) then 

!FLASH_ENABLED 

else 

FLASH_ENABLED; 

state !FLASH_ENABLED: 


(FLASH_ENABLE_DATA_BIT.pin == FLASH_ENABLED) & 

(!KA_PON_RESET # (FLASH_ENABLE_PON_DEFAULT != !FLASH_ENABLED)) # 

(KA_PON_RESET & (FLASH_ENABLE_PON_DEFAULT == FLASH_ENABLED)) ) then 

FLASH_ENABLED 

else 

!FLASH_ENABLED; 

"****************************************************************************** 





Freescale 




Inc. 


state_diagram DramEn~ 

state DRAM_ENABLED: 


(DRAM_ENABLE_DATA_BIT.pin == !DRAM_ENABLED) & 

(!KA_PON_RESET # (DRAM_ENABLE_PON_DEFAULT != DRAM_ENABLED)) # 

(KA_PON_RESET & (DRAM_ENABLE_PON_DEFAULT == !DRAM_ENABLED)) ) then 

!DRAM_ENABLED 

else 

DRAM_ENABLED; 

state !DRAM_ENABLED: 


(DRAM_ENABLE_DATA_BIT.pin == DRAM_ENABLED) & 

(!KA_PON_RESET # (DRAM_ENABLE_PON_DEFAULT != !DRAM_ENABLED)) # 

(KA_PON_RESET & (DRAM_ENABLE_PON_DEFAULT == DRAM_ENABLED)) ) then 

DRAM_ENABLED 

else 

!DRAM_ENABLED; 

"****************************************************************************** 

state_diagram EthEn~ 

state ETH_ENABLED: 


(ETH_ENABLE_DATA_BIT.pin == !ETH_ENABLED) & 

(!KA_PON_RESET # (ETH_ENABLE_PON_DEFAULT != ETH_ENABLED)) # 

(KA_PON_RESET & (ETH_ENABLE_PON_DEFAULT == !ETH_ENABLED)) ) then 

!ETH_ENABLED 

else 

ETH_ENABLED; 

state !ETH_ENABLED: 


(ETH_ENABLE_DATA_BIT.pin == ETH_ENABLED) & 

(!KA_PON_RESET # (ETH_ENABLE_PON_DEFAULT != !ETH_ENABLED)) # 

(KA_PON_RESET & (ETH_ENABLE_PON_DEFAULT == ETH_ENABLED)) ) then 

ETH_ENABLED 

else 

!ETH_ENABLED; 

"****************************************************************************** 

state_diagram InfRedEn~ 

state INF_RED_ENABLE: 


(INF_RED_ENABLE_DATA_BIT.pin == !INF_RED_ENABLE) & 

(!KA_PON_RESET # (INF_RED_ENABLE_PON_DEFAULT != INF_RED_ENABLE)) # 

(KA_PON_RESET & (INF_RED_ENABLE_PON_DEFAULT == !INF_RED_ENABLE)) ) then 

!INF_RED_ENABLE 

else 

INF_RED_ENABLE; 

state !INF_RED_ENABLE: 


(INF_RED_ENABLE_DATA_BIT.pin == INF_RED_ENABLE) & 

(!KA_PON_RESET # (INF_RED_ENABLE_PON_DEFAULT != !INF_RED_ENABLE)) # 

(KA_PON_RESET & (INF_RED_ENABLE_PON_DEFAULT == INF_RED_ENABLE)) ) then 

INF_RED_ENABLE 

else 

!INF_RED_ENABLE; 

"****************************************************************************** 

state_diagram FlashCfgEn~ 

state FLASH_CFG_ENABLE: 


(FLASH_CFG_ENABLE_DATA_BIT.pin == !FLASH_CFG_ENABLE) & 





Freescale 




Inc. 


(!KA_PON_RESET # (FLASH_CFG_ENABLE_PON_DEFAULT != FLASH_CFG_ENABLE)) # 

(KA_PON_RESET & (FLASH_CFG_ENABLE_PON_DEFAULT == !FLASH_CFG_ENABLE)) ) then 

!FLASH_CFG_ENABLE 

else 

FLASH_CFG_ENABLE; 

state !FLASH_CFG_ENABLE: 


(FLASH_CFG_ENABLE_DATA_BIT.pin == FLASH_CFG_ENABLE) & 

(!KA_PON_RESET # (FLASH_CFG_ENABLE_PON_DEFAULT != !FLASH_CFG_ENABLE)) # 

(KA_PON_RESET & (FLASH_CFG_ENABLE_PON_DEFAULT == FLASH_CFG_ENABLE)) ) then 

FLASH_CFG_ENABLE 

else 

!FLASH_CFG_ENABLE; 

"****************************************************************************** 

"* To avoid in advertant write to the Control Register Enable bit, which might 

"* result in a need to re-power the board - protection logic is provided. 

"* In order of writing the Control Register Enable this bit in the status register 

"* must be negated. After any write to the control register, this bit asserts 

"* again (to protected mode) 

"****************************************************************************** 

equations 

CntRegEnProtect~.clk = SYSCLK; 

state_diagram CntRegEnProtect~ 

state CNT_REG_EN_PROTECT: 


(CNT_REG_EN_PROTECT_DATA_BIT.pin == !CNT_REG_EN_PROTECT) & 

(!KA_PON_RESET # (CNT_REG_EN_PROTECT_PON_DEFAULT != CNT_REG_EN_PROTECT)) # 

(KA_PON_RESET & (CNT_REG_EN_PROTECT_PON_DEFAULT == !CNT_REG_EN_PROTECT)) ) then 

!CNT_REG_EN_PROTECT 

else 

CNT_REG_EN_PROTECT; 

state !CNT_REG_EN_PROTECT: 


(CNT_REG_EN_PROTECT_DATA_BIT.pin == CNT_REG_EN_PROTECT) & 

(!KA_PON_RESET # (CNT_REG_EN_PROTECT_PON_DEFAULT != !CNT_REG_EN_PROTECT)) # 

(KA_PON_RESET & (CNT_REG_EN_PROTECT_PON_DEFAULT == CNT_REG_EN_PROTECT)) # 

MPC_WRITE_BCSR_1) then " any write to control reg 1 

CNT_REG_EN_PROTECT 

else 

!CNT_REG_EN_PROTECT; 

"****************************************************************************** 

"* protected by CntRegEnProtect~ to prevent from inadvertant write 

"****************************************************************************** 

state_diagram CntRegEn~ 

state CONT_REG_ENABLE: 

if (MPC_WRITE_BCSR_1 & (CntRegEnProtect~.fb != CNT_REG_EN_PROTECT) & 

(CONT_REG_ENABLE_DATA_BIT.pin == !CONT_REG_ENABLE) & 

(!KA_PON_RESET # (CONT_REG_ENABLE_PON_DEFAULT != CONT_REG_ENABLE)) # 

(KA_PON_RESET & (CONT_REG_ENABLE_PON_DEFAULT == !CONT_REG_ENABLE)) ) then 

!CONT_REG_ENABLE 

else 

CONT_REG_ENABLE; 

state !CONT_REG_ENABLE:" in fact not applicable 


(CONT_REG_ENABLE_DATA_BIT.pin == CONT_REG_ENABLE) & 

(!KA_PON_RESET # (CONT_REG_ENABLE_PON_DEFAULT != !CONT_REG_ENABLE)) # 

(KA_PON_RESET & (CONT_REG_ENABLE_PON_DEFAULT == CONT_REG_ENABLE)) ) then 





Freescale 




Inc. 


CONT_REG_ENABLE 

else 

!CONT_REG_ENABLE; 

"****************************************************************************** 

state_diagram RS232En1~ 

state RS232_1_ENABLE: 


(RS232_1_ENABLE_DATA_BIT.pin == !RS232_1_ENABLE) & 

(!KA_PON_RESET # (RS232_1_ENABLE_PON_DEFAULT != RS232_1_ENABLE)) # 

(KA_PON_RESET & (RS232_1_ENABLE_PON_DEFAULT == !RS232_1_ENABLE)) ) then 

!RS232_1_ENABLE 

else 

RS232_1_ENABLE; 

state !RS232_1_ENABLE: 


(RS232_1_ENABLE_DATA_BIT.pin == RS232_1_ENABLE) & 

(!KA_PON_RESET # (RS232_1_ENABLE_PON_DEFAULT != !RS232_1_ENABLE)) # 

(KA_PON_RESET & (RS232_1_ENABLE_PON_DEFAULT == RS232_1_ENABLE)) ) then 

RS232_1_ENABLE 

else 

!RS232_1_ENABLE; 

"****************************************************************************** 

state_diagram PccEn~ 

state PCC_ENABLE: 


(PCC_ENABLE_DATA_BIT.pin == !PCC_ENABLE) & 

(!KA_PON_RESET # (PCC_ENABLE_PON_DEFAULT != PCC_ENABLE)) # 

(KA_PON_RESET & (PCC_ENABLE_PON_DEFAULT == !PCC_ENABLE)) ) then 

!PCC_ENABLE 

else 

PCC_ENABLE; 

state !PCC_ENABLE: 


(PCC_ENABLE_DATA_BIT.pin == PCC_ENABLE) & 

(!KA_PON_RESET # (PCC_ENABLE_PON_DEFAULT != !PCC_ENABLE)) # 

(KA_PON_RESET & (PCC_ENABLE_PON_DEFAULT == PCC_ENABLE)) ) then 

PCC_ENABLE 

else 

!PCC_ENABLE; 

"****************************************************************************** 

state_diagram PccVcc0 

state PCC_VCC_CONT_0: 


(PCC_VCC_0_DATA_BIT.pin == !PCC_VCC_CONT_0) & 

(!KA_PON_RESET # (PCC_VCC_0_PON_DEFAULT != PCC_VCC_CONT_0)) # 

(KA_PON_RESET & (PCC_VCC_0_PON_DEFAULT == !PCC_VCC_CONT_0)) ) then 

!PCC_VCC_CONT_0 

else 

PCC_VCC_CONT_0; 

state !PCC_VCC_CONT_0: 


(PCC_VCC_0_DATA_BIT.pin == PCC_VCC_CONT_0) & 

(!KA_PON_RESET # (PCC_VCC_0_PON_DEFAULT != !PCC_VCC_CONT_0)) # 

(KA_PON_RESET & (PCC_VCC_0_PON_DEFAULT == PCC_VCC_CONT_0)) ) then 

PCC_VCC_CONT_0 

else 

!PCC_VCC_CONT_0; 

"****************************************************************************** 

state_diagram PccVpp0 





Freescale 




Inc. 


state PCC_VPP0: 


(PCC_VPP0_DATA_BIT.pin == !PCC_VPP0) & 

(!KA_PON_RESET # (PCC_VPP0_PON_DEFAULT != PCC_VPP0)) # 

(KA_PON_RESET & (PCC_VPP0_PON_DEFAULT == !PCC_VPP0)) ) then 

!PCC_VPP0 

else 

PCC_VPP0; 

state !PCC_VPP0: 


(PCC_VPP0_DATA_BIT.pin == PCC_VPP0) & 

(!KA_PON_RESET # (PCC_VPP0_PON_DEFAULT != !PCC_VPP0)) # 

(KA_PON_RESET & (PCC_VPP0_PON_DEFAULT == PCC_VPP0)) ) then 

PCC_VPP0 

else 

!PCC_VPP0; 

"****************************************************************************** 

state_diagram PccVpp1 

state PCC_VPP1: 


(PCC_VPP1_DATA_BIT.pin == !PCC_VPP1) & 

(!KA_PON_RESET # (PCC_VPP1_PON_DEFAULT != PCC_VPP1)) # 

(KA_PON_RESET & (PCC_VPP1_PON_DEFAULT == !PCC_VPP1)) ) then 

!PCC_VPP1 

else 

PCC_VPP1; 

state !PCC_VPP1: 


(PCC_VPP1_DATA_BIT.pin == PCC_VPP1) & 

(!KA_PON_RESET # (PCC_VPP1_PON_DEFAULT != !PCC_VPP1)) # 

(KA_PON_RESET & (PCC_VPP1_PON_DEFAULT == PCC_VPP1)) ) then 

PCC_VPP1 

else 

!PCC_VPP1; 

"****************************************************************************** 

state_diagram HalfWord~ 

state HALF_WORD: 


(HALF_WORD_DATA_BIT.pin == !HALF_WORD) & 

(!KA_PON_RESET # (HALF_WORD_PON_DEFAULT != HALF_WORD)) # 

(KA_PON_RESET & (HALF_WORD_PON_DEFAULT == !HALF_WORD)) ) then 

!HALF_WORD 

else 

HALF_WORD; 

state !HALF_WORD: 


(HALF_WORD_DATA_BIT.pin == HALF_WORD) & 

(!KA_PON_RESET # (HALF_WORD_PON_DEFAULT != !HALF_WORD)) # 

(KA_PON_RESET & (HALF_WORD_PON_DEFAULT == HALF_WORD)) ) then 

HALF_WORD 

else 

!HALF_WORD; 

"****************************************************************************** 

state_diagram RS232En2~ 

state RS232_2_ENABLE: 


(RS232_2_ENABLE_DATA_BIT.pin == !RS232_2_ENABLE) & 

(!KA_PON_RESET # (RS232_2_ENABLE_PON_DEFAULT != RS232_2_ENABLE)) # 





Freescale 




Inc. 


(KA_PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == !RS232_2_ENABLE)) ) then 

!RS232_2_ENABLE 

else 

RS232_2_ENABLE; 

state !RS232_2_ENABLE: 


(RS232_2_ENABLE_DATA_BIT.pin == RS232_2_ENABLE) & 

(!KA_PON_RESET # (RS232_2_ENABLE_PON_DEFAULT != !RS232_2_ENABLE)) # 

(KA_PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == RS232_2_ENABLE)) ) then 

RS232_2_ENABLE 

else 

!RS232_2_ENABLE; 

"****************************************************************************** 

state_diagram PccVcc1 

state PCC_VCC_CONT_0: 


(PCC_VCC_1_DATA_BIT.pin == !PCC_VCC_CONT_0) & 

(!KA_PON_RESET # (PCC_VCC_1_PON_DEFAULT != PCC_VCC_CONT_0)) # 

(KA_PON_RESET & (PCC_VCC_1_PON_DEFAULT == !PCC_VCC_CONT_0)) ) then 

!PCC_VCC_CONT_0 

else 

PCC_VCC_CONT_0; 

state !PCC_VCC_CONT_0: 


(PCC_VCC_1_DATA_BIT.pin == PCC_VCC_CONT_0) & 

(!KA_PON_RESET # (PCC_VCC_1_PON_DEFAULT != !PCC_VCC_CONT_0)) # 

(KA_PON_RESET & (PCC_VCC_1_PON_DEFAULT == PCC_VCC_CONT_0)) ) then 

PCC_VCC_CONT_0 

else 

!PCC_VCC_CONT_0; 

"****************************************************************************** 

state_diagram SdramEn~ 

state SDRAM_ENABLED: 


(SDRAM_ENABLE_DATA_BIT.pin == !SDRAM_ENABLED) & 

(!KA_PON_RESET # (SDRAM_ENABLE_PON_DEFAULT != SDRAM_ENABLED)) # 

(KA_PON_RESET & (SDRAM_ENABLE_PON_DEFAULT == !SDRAM_ENABLED)) ) then 

!SDRAM_ENABLED 

else 

SDRAM_ENABLED; 

state !SDRAM_ENABLED: 


(SDRAM_ENABLE_DATA_BIT.pin == SDRAM_ENABLED) & 

(!KA_PON_RESET # (SDRAM_ENABLE_PON_DEFAULT != !SDRAM_ENABLED)) # 

(KA_PON_RESET & (SDRAM_ENABLE_PON_DEFAULT == SDRAM_ENABLED)) ) then 

SDRAM_ENABLED 

else 

!SDRAM_ENABLED; 

"****************************************************************************** 

"****************************************************************************** 

"* BCSR4 State Machines 

"****************************************************************************** 

"****************************************************************************** 

state_diagram UsbFethEn~ 

state USB_FETH_ENABLED: 






Freescale 




Inc. 


(USB_FETH_EN_DATA_BIT.pin == !USB_FETH_ENABLED) & 

(!KA_PON_RESET # (USB_FETH_EN_PON_DEFAULT != USB_FETH_ENABLED)) # 

(KA_PON_RESET & (USB_FETH_EN_PON_DEFAULT == !USB_FETH_ENABLED)) ) then 

!USB_FETH_ENABLED 

else 

USB_FETH_ENABLED; 

state !USB_FETH_ENABLED: 


(USB_FETH_EN_DATA_BIT.pin == USB_FETH_ENABLED) & 

(!KA_PON_RESET # (USB_FETH_EN_PON_DEFAULT != !USB_FETH_ENABLED)) # 

(KA_PON_RESET & (USB_FETH_EN_PON_DEFAULT == USB_FETH_ENABLED)) ) then 

USB_FETH_ENABLED 

else 

!USB_FETH_ENABLED; 

"****************************************************************************** 

state_diagram UsbSpeed 

state USB_FULL_SPEED: 


(USB_SPEED_DATA_BIT.pin == !USB_FULL_SPEED) & 

(!KA_PON_RESET # (USB_SPEED_PON_DEFAULT != USB_FULL_SPEED)) # 

(KA_PON_RESET & (USB_SPEED_PON_DEFAULT == !USB_FULL_SPEED)) ) then 

!USB_FULL_SPEED 

else 

USB_FULL_SPEED; 

state !USB_FULL_SPEED: 


(USB_SPEED_DATA_BIT.pin == USB_FULL_SPEED) & 

(!KA_PON_RESET # (USB_SPEED_PON_DEFAULT != !USB_FULL_SPEED)) # 

(KA_PON_RESET & (USB_SPEED_PON_DEFAULT == USB_FULL_SPEED)) ) then 

USB_FULL_SPEED 

else 

!USB_FULL_SPEED; 

"****************************************************************************** 

state_diagram UsbVcc0 

state USB_VCC_CONT_0: 


(USB_VCC_0_DATA_BIT.pin == !USB_VCC_CONT_0) & 

(!KA_PON_RESET # (USB_VCC_0_CONT_PON_DEFAULT != USB_VCC_CONT_0)) # 

(KA_PON_RESET & (USB_VCC_0_CONT_PON_DEFAULT == !USB_VCC_CONT_0)) ) then 

!USB_VCC_CONT_0 

else 

USB_VCC_CONT_0; 

state !USB_VCC_CONT_0: 


(USB_VCC_0_DATA_BIT.pin == USB_VCC_CONT_0) & 

(!KA_PON_RESET # (USB_VCC_0_CONT_PON_DEFAULT != !USB_VCC_CONT_0)) # 

(KA_PON_RESET & (USB_VCC_0_CONT_PON_DEFAULT == USB_VCC_CONT_0)) ) then 

USB_VCC_CONT_0 

else 

!USB_VCC_CONT_0; 

"****************************************************************************** 

state_diagram UsbVcc1 

state USB_VCC_CONT_0: 






Freescale 




Inc. 


(USB_VCC_1_DATA_BIT.pin == !USB_VCC_CONT_0) & 

(!KA_PON_RESET # (USB_VCC_1_CONT_PON_DEFAULT != USB_VCC_CONT_0)) # 

(KA_PON_RESET & (USB_VCC_1_CONT_PON_DEFAULT == !USB_VCC_CONT_0)) ) then 

!USB_VCC_CONT_0 

else 

USB_VCC_CONT_0; 

state !USB_VCC_CONT_0: 


(USB_VCC_1_DATA_BIT.pin == USB_VCC_CONT_0) & 

(!KA_PON_RESET # (USB_VCC_1_CONT_PON_DEFAULT != !USB_VCC_CONT_0)) # 

(KA_PON_RESET & (USB_VCC_1_CONT_PON_DEFAULT == USB_VCC_CONT_0)) ) then 

USB_VCC_CONT_0 

else 

!USB_VCC_CONT_0; 

"****************************************************************************** 

state_diagram VideoOn~ 

state VIDEO_ENABLED: 


(VIDEO_ENABLE_DATA_BIT.pin == !VIDEO_ENABLED) & 

(!KA_PON_RESET # (VIDEO_ENABLE_PON_DEFAULT != VIDEO_ENABLED)) # 

(KA_PON_RESET & (VIDEO_ENABLE_PON_DEFAULT == !VIDEO_ENABLED)) ) then 

!VIDEO_ENABLED 

else 

VIDEO_ENABLED; 

state !VIDEO_ENABLED: 


(VIDEO_ENABLE_DATA_BIT.pin == VIDEO_ENABLED) & 

(!KA_PON_RESET # (VIDEO_ENABLE_PON_DEFAULT != !VIDEO_ENABLED)) # 

(KA_PON_RESET & (VIDEO_ENABLE_PON_DEFAULT == VIDEO_ENABLED)) ) then 

VIDEO_ENABLED 

else 

!VIDEO_ENABLED; 

"****************************************************************************** 

state_diagram VideoExtClkEn 

state VIDEO_EXT_CLK_ENABLED: 


(VIDEO_EXT_CLK_EN_DATA_BIT.pin == !VIDEO_EXT_CLK_ENABLED) & 

(!KA_PON_RESET # (VIDEO_EXT_CLK_EN_PON_DEFAULT != VIDEO_EXT_CLK_ENABLED)) # 

(KA_PON_RESET & (VIDEO_EXT_CLK_EN_PON_DEFAULT == !VIDEO_EXT_CLK_ENABLED)) ) then 

!VIDEO_EXT_CLK_ENABLED 

else 

VIDEO_EXT_CLK_ENABLED; 

state !VIDEO_EXT_CLK_ENABLED: 


(VIDEO_EXT_CLK_EN_DATA_BIT.pin == VIDEO_EXT_CLK_ENABLED) & 

(!KA_PON_RESET # (VIDEO_EXT_CLK_EN_PON_DEFAULT != !VIDEO_EXT_CLK_ENABLED)) # 

(KA_PON_RESET & (VIDEO_EXT_CLK_EN_PON_DEFAULT == VIDEO_EXT_CLK_ENABLED)) ) then 

VIDEO_EXT_CLK_ENABLED 

else 

!VIDEO_EXT_CLK_ENABLED; 

"****************************************************************************** 

state_diagram VideoRst~ 

state VIDEO_RESET_ACTIVE: 


(VIDEO_RESET_DATA_BIT.pin == !VIDEO_RESET_ACTIVE) & 

(!KA_PON_RESET # (VIDEO_RESET_PON_DEFAULT != VIDEO_RESET_ACTIVE)) # 

(KA_PON_RESET & (VIDEO_RESET_PON_DEFAULT == !VIDEO_RESET_ACTIVE)) ) then 





Freescale 




Inc. 


!VIDEO_RESET_ACTIVE 

else 

VIDEO_RESET_ACTIVE; 

state !VIDEO_RESET_ACTIVE: 


(VIDEO_RESET_DATA_BIT.pin == VIDEO_RESET_ACTIVE) & 

(!KA_PON_RESET # (VIDEO_RESET_PON_DEFAULT != !VIDEO_RESET_ACTIVE)) # 

(KA_PON_RESET & (VIDEO_RESET_PON_DEFAULT == VIDEO_RESET_ACTIVE)) ) then 

VIDEO_RESET_ACTIVE 

else 

!VIDEO_RESET_ACTIVE; 

"****************************************************************************** 

state_diagram SignaLamp~ 

state SIGNAL_LAMP_ON: 


(SIGNAL_LAMP_DATA_BIT.pin == !SIGNAL_LAMP_ON) & 

(!KA_PON_RESET # (SIGNAL_LAMP_PON_DEFAULT != SIGNAL_LAMP_ON)) # 

(KA_PON_RESET & (SIGNAL_LAMP_PON_DEFAULT == !SIGNAL_LAMP_ON)) ) then 

!SIGNAL_LAMP_ON 

else 

SIGNAL_LAMP_ON; 

state !SIGNAL_LAMP_ON: 


(SIGNAL_LAMP_DATA_BIT.pin == SIGNAL_LAMP_ON) & 

(!KA_PON_RESET # (SIGNAL_LAMP_PON_DEFAULT != !SIGNAL_LAMP_ON)) # 

(KA_PON_RESET & (SIGNAL_LAMP_PON_DEFAULT == SIGNAL_LAMP_ON)) ) then 

SIGNAL_LAMP_ON 

else 

!SIGNAL_LAMP_ON; 

"****************************************************************************** 

state_diagram EthLoop 

state ETH_LOOP: 


(ETH_LOOP_DATA_BIT.pin == !ETH_LOOP) & 

(!KA_PON_RESET # (ETH_LOOP_PON_DEFAULT != ETH_LOOP)) # 

(KA_PON_RESET & (ETH_LOOP_PON_DEFAULT == !ETH_LOOP)) ) then 

!ETH_LOOP 

else 

ETH_LOOP; 

state !ETH_LOOP: 


(ETH_LOOP_DATA_BIT.pin == ETH_LOOP) & 

(!KA_PON_RESET # (ETH_LOOP_PON_DEFAULT != !ETH_LOOP)) # 

(KA_PON_RESET & (ETH_LOOP_PON_DEFAULT == ETH_LOOP)) ) then 

ETH_LOOP 

else 

!ETH_LOOP; 

"****************************************************************************** 

state_diagram TPFLDL~ 

state ETH_FULL_DUP: 


(ETH_FULL_DUP_DATA_BIT.pin == !ETH_FULL_DUP) & 

(!KA_PON_RESET # (ETH_FULL_DUP_PON_DEFAULT != ETH_FULL_DUP)) # 

(KA_PON_RESET & (ETH_FULL_DUP_PON_DEFAULT == !ETH_FULL_DUP)) ) then 

!ETH_FULL_DUP 

else 

ETH_FULL_DUP; 

state !ETH_FULL_DUP: 






Freescale 




Inc. 


(ETH_FULL_DUP_DATA_BIT.pin == ETH_FULL_DUP) & 

(!KA_PON_RESET # (ETH_FULL_DUP_PON_DEFAULT != !ETH_FULL_DUP)) # 

(KA_PON_RESET & (ETH_FULL_DUP_PON_DEFAULT == ETH_FULL_DUP)) ) then 

ETH_FULL_DUP 

else 

!ETH_FULL_DUP; 

"****************************************************************************** 

state_diagram TPSQEL~ 

state ETH_CLSN_TEST: 


(ETH_CLSN_TEST_DATA_BIT.pin == !ETH_CLSN_TEST) & 

(!KA_PON_RESET # (ETH_CLSN_TEST_PON_DEFAULT != ETH_CLSN_TEST)) # 

(KA_PON_RESET & (ETH_CLSN_TEST_PON_DEFAULT == !ETH_CLSN_TEST)) ) then 

!ETH_CLSN_TEST 

else 

ETH_CLSN_TEST; 

state !ETH_CLSN_TEST: 


(ETH_CLSN_TEST_DATA_BIT.pin == ETH_CLSN_TEST) & 

(!KA_PON_RESET # (ETH_CLSN_TEST_PON_DEFAULT != !ETH_CLSN_TEST)) # 

(KA_PON_RESET & (ETH_CLSN_TEST_PON_DEFAULT == ETH_CLSN_TEST)) ) then 

ETH_CLSN_TEST 

else 

!ETH_CLSN_TEST; 

"****************************************************************************** 

state_diagram ModemEn~ 

state MODEM_ENABLED_FOR_823: 


(MODEM_ENABLE_DATA_BIT.pin == !MODEM_ENABLED_FOR_823) & 

(!KA_PON_RESET # (MODEM_ENABLE_PON_DEFAULT != MODEM_ENABLED_FOR_823)) # 

(KA_PON_RESET & (MODEM_ENABLE_PON_DEFAULT == !MODEM_ENABLED_FOR_823)) ) then 

!MODEM_ENABLED_FOR_823 

else 

MODEM_ENABLED_FOR_823; 

state !MODEM_ENABLED_FOR_823: 


(MODEM_ENABLE_DATA_BIT.pin == MODEM_ENABLED_FOR_823) & 

(!KA_PON_RESET # (MODEM_ENABLE_PON_DEFAULT != !MODEM_ENABLED_FOR_823)) # 

(KA_PON_RESET & (MODEM_ENABLE_PON_DEFAULT == MODEM_ENABLED_FOR_823)) ) then 

MODEM_ENABLED_FOR_823 

else 

!MODEM_ENABLED_FOR_823; 

"****************************************************************************** 

state_diagram Modem_Audio~ 

state MODEM: 


(MODEM_FUNC_SEL_DATA_BIT.pin == !MODEM) & 

(!KA_PON_RESET # (MODEM_FUNC_SEL_PON_DEFAULT != MODEM)) # 

(KA_PON_RESET & (MODEM_FUNC_SEL_PON_DEFAULT == !MODEM)) ) then 

!MODEM 

else 

MODEM; 

state !MODEM: 


(MODEM_FUNC_SEL_DATA_BIT.pin == MODEM) & 

(!KA_PON_RESET # (MODEM_FUNC_SEL_PON_DEFAULT != !MODEM)) # 

(KA_PON_RESET & (MODEM_FUNC_SEL_PON_DEFAULT == MODEM)) ) then 

MODEM 

else 





Freescale 




Inc. 


!MODEM; 

"****************************************************************************** 

"****************************************************************************** 

" External Read Registers' Chip-Selects 

"****************************************************************************** 

"****************************************************************************** 

equations 

Bcsr2_3Cs~.oe = 3; 

!Bcsr2Cs~ = MPC_READ_BCSR_2; 

!Bcsr3Cs~ = MPC_READ_BCSR_3; 

"****************************************************************************** 

"****************************************************************************** 

"* Read Registers. 

"* All registers have read capabilty. 

"****************************************************************************** 

"****************************************************************************** 

equations 

DataOe = MPC_READ_BCSR_0 # 

MPC_READ_BCSR_1 # 

MPC_READ_BCSR_4 # 

RESET_CONFIG_DRIVEN; 

Data.oe = DataOe; 

"Data.oe = ^hffff; 

when (MPC_READ_BCSR_0 # 

RESET_CONFIG_DRIVEN) then 

Data = [ERB.fb,IP~.fb,RSV2.fb,BDIS.fb,BPS0.fb,BPS1.fb,RSV6.fb, 

ISB0.fb,ISB1.fb,DBGC0.fb,DBGC1.fb,DBPC0.fb,DBPC1.fb, 

RSV13.fb,RSV14.fb,RSV15.fb]; 

else when (MPC_READ_BCSR_1) then 

Data = ReadBcsr1; 

else when (MPC_READ_BCSR_4) then 

"Data = [UsbFethEn~,UsbSpeed,UsbVcc0, UsbVcc1, VideoOn~,VideoExtClkEn, 

" VideoRst~,SignaLamp~,EthLoop,TPFLDL~,TPSQEL~,Modem_Audio~,0,0,0,0]; 

Data = [EthLoop,TPFLDL~,TPSQEL~,SignaLamp~,UsbFethEn~,UsbSpeed,UsbVcc0, 

UsbVcc1, VideoOn~,VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~,0,0,0]; 

"****************************************************************************** 

"****************************************************************************** 

"* Additional Equations from brd_ctl13 

"****************************************************************************** 

"****************************************************************************** 

"******************** 

"* Flash Chip Select 

"******************** 

equations 

FlashCsOut.oe = ^hf; 

!FlashCs1~ = FLASH_ACTIVE & !FlashCs~ & FLASH_BANK1; 

!FlashCs2~ = FLASH_ACTIVE & !FlashCs~ & FLASH_BANK2 ; 



FlashOe~.oe = H; 





!FlashOe~ = FLASH_ACTIVE & R_W~; 

Freescale 




Inc. 


"****************************************************************************** 

"* Dram Address lines. 

"* These lines are conencted to the dram high order address lines A9 and A10 

"* (if available). These lines change value according to the dram size and 

"* port size. 

"* The dram size is encoded from the presence detect lines (see definitions 

"* above) and the port size is determined by the control register. 

"****************************************************************************** 

equations 

DramAdd.oe = 3; 

when (!IS_HALF_WORD # IS_HALF_WORD & (SIMM36400 # SIMM36800)) then 

DramAdd9 = A20; 

else 


when ( (SIMM36400 # SIMM36800) & !IS_HALF_WORD) then 


else when ( (SIMM36400 # SIMM36800) & IS_HALF_WORD) then 


else 

DramAdd10 = 0; 

"****************************************************************************** 

"* RAS generation. 

"* Since the dram simm requires RAS signals to be split due to high capacitive 

"* load and to allow 16 bit operation. When working with 16 bit port size, 

"* the double drive RAS signals are disabled. 

"****************************************************************************** 

equations 

RAS.oe = ^hf; 

!Ras1~ = !DramBank1Cs~ & DramBank2Cs~ & DRAM_ACTIVE; 

!Ras2~ = !DramBank2Cs~ & DramBank1Cs~ & DRAM_ACTIVE & (SIMM36200 # SIMM36800); 

!Ras1DD~ = !DramBank1Cs~ & DramBank2Cs~ & DRAM_ACTIVE; 

!Ras2DD~ = !DramBank2Cs~ & DramBank1Cs~ & DRAM_ACTIVE & (SIMM36200 # SIMM36800); 

"****************************************************************************** 

"* Reset Logic 

"****************************************************************************** 

equations 

Reset.oe = ResetEn; 

Reset = 0;" open drain 

RstDeb1 = !( Rst1 & (!( RstDeb1.fb & Rst0) ) ); " Reset push-button debouncer 

AbrDeb1 = !( Abr1 & (!( AbrDeb1.fb & Abr0) ) ); " Abort push-button debouncer 

HardResetEn = RstDeb1.fb & AbrDeb1.fb " both buttons are depressed; 

# REGULAR_POWER_ON_RESET; 





Freescale 




Inc. 


SoftResetEn = RstDeb1.fb & !AbrDeb1.fb;" only reset button depressed 

"****************************************************************************** 

"* Power On reset configuration 

"****************************************************************************** 

equations 

Modck.oe = ModckOe; 

ModckOe = DRIVE_MODCK_TO_PDA; 

Modck2 = L; 

@ifndef SLOW_32K_LOCK { 

Modck2 = ModIn;" support for 1:513 (32KHz crystal) or 

Modck1 = ModIn;" 1:5 (5MHz clock gen.) via CLK4IN 

} 

@ifdef SLOW_32K_LOCK { 

Modck2 = !ModIn;" support for 1:1 or 1:5 from CLK4IN only 

Modck1 = H;" no support for 32K oscillator. 

} 

"****************************************************************************** 

"* Hard reset configuration 

"****************************************************************************** 

equations 

ResetConfig~.oe = H; 

DriveConfig~.oe = H; 

"* Configuration hold counter. Since the rise time of the HARD RESET signal 

"* is relatively slow, there is a need to provide a hold time for reset 

"* configuration. 

ConfigHold.clk = SYSCLK; 

when (SyncHardReset~.fb & !ConfigHoldEnd.fb) then ConfigHold := ConfigHold.fb +1; 

else when (SyncHardReset~.fb & ConfigHoldEnd.fb) then ConfigHold := ConfigHold.fb; 

else when (!SyncHardReset~.fb) then ConfigHold := 0; 

ConfigHoldEnd = (ConfigHold.fb == HARD_CONFIG_HOLD_VALUE); " terminal count 

!ResetConfig~ = !HardReset~;" drives RSTCONF~ to pda 

!DriveConfig~ = !ConfigHoldEnd.fb; " drives configuration data on the bus. 

"****************************************************************************** 

"* NMI generation 

"****************************************************************************** 

equations 

NMI~.oe = NMIEn; 

NMI~ = 0;" O.D. 

NMIEn = !RstDeb1.fb & AbrDeb1.fb;" only abort button depressed 





Freescale 




Inc. 


"****************************************************************************** 

"* local data buffers enable 

"****************************************************************************** 

equations 

SyncHardReset~.clk = SYSCLK; 

DSyncHardReset~.clk = SYSCLK; 

SyncHardReset~ := HardReset~; 

DSyncHardReset~ := SyncHardReset~.fb; 

SyncTEA~.clk = SYSCLK; 

SyncTEA~ := TEA~; 

LocDataBufEn.oe = 3; 

!UpperHalfEn~ = (!DramBank1Cs~ & DRAM_ACTIVE # 

!DramBank2Cs~ & (SIMM36200 # SIMM36800) & DRAM_ACTIVE # 

!FlashCs~ & FLASH_ACTIVE # 

!BrdContRegCs~ & CONTROL_REG_ENABLED # 

!PccCE1~ & PCC_ENABLED # 

!PccCE2~ & PCC_ENABLED # 

!ConfigHoldEnd.fb) & 

(STATE_HOLD_OFF_CONSIDERED & !(HOLD_OFF_PERIOD) # 

STATE_NO_HOLD_OFF) 

# !cs5 # !cs6 # !cs7; "add haim 

!LowerHalfEn~ = (!DramBank1Cs~ & DRAM_ACTIVE & !IS_HALF_WORD # 

!DramBank2Cs~ & (SIMM36200 # SIMM36800) & 

!IS_HALF_WORD & DRAM_ACTIVE # 

!FlashCs~ & FLASH_ACTIVE # 

!ConfigHoldEnd.fb & FLASH_CONFIGURATION_ENABLED) & 


STATE_NO_HOLD_OFF); 

"****************************************************************************** 

"* local data buffers disable (data contention protection) 

"****************************************************************************** 

equations 

HoldOffConsidered.clk = SYSCLK; 

D_FlashOe~ = FlashOe~; 

DD_FlashOe~ = D_FlashOe~.fb; 

TD_FlashOe~ = DD_FlashOe~.fb; 

"* QD_FlashOe~ = TD_FlashOe~.fb; 

"* PD_FlashOe~ = QD_FlashOe~.fb; 

@ifdef DEBUG { 

equations 

HoldOffConsidered := HOLD_OFF_CONSIDERED; 

} 

@ifndef DEBUG { 

state_diagram HoldOffConsidered 

state NO_HOLD_OFF: 





} 

Freescale 




Inc. 


if (END_OF_FLASH_READ & DSyncHardReset~.fb) then 

HOLD_OFF_CONSIDERED 

else 

NO_HOLD_OFF; 

state HOLD_OFF_CONSIDERED: 

if (END_OF_OTHER_CYCLE # !DSyncHardReset~.fb) then 

NO_HOLD_OFF 

else 

HOLD_OFF_CONSIDERED; 

"****************************************************************************** 

"* pcc data buffers enable 

"****************************************************************************** 

equations 

PccDataBufEn.oe = 3; 

!PccEvenEn~ = (!PccCE1~ # !PccCE2~) & PCC_ENABLED & !HARD_RESET_ASSERTED & 



!PccOddEn~ = (!PccCE1~ # !PccCE2~) & PCC_ENABLED & !HARD_RESET_ASSERTED & 



"****************************************************************************** 

"* pcc data buffers direction 

"****************************************************************************** 

equations 

PccR_W~.oe = H; 

PccR_W~ = R_W~; 

"****************************************************************************** 

"* Auxiliary functions 

"****************************************************************************** 

equations 

KeepPinsConnected = TA~ ; 

"****************************************************************************** 

"* 





Freescale 




Inc. 


2•0•3 BCSR5 & ATM & Fast-Ethernet Control Logic. 

FREQUENCY=50MHZ 

mpc862db@128 

140 nCS 

@53 nTS 

@143 RD_nWR 

134 nOE 

125 nWE 

ADDR_PQ[21..31] 

@127 nPORESET 

136 FUNC_SEL0 

137 FUNC_SEL1 

139 FUNC_SEL2 

@38 CE1 

b@141 nHRESET 

ADDR_PQ[21..23] 

nCS 

GND 

SYSCLK 

nCS_ControlReg1 

RD_nWR 

nHRESET 

BDAT[0..7] 

nWE 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

SYSCLK 

RD_nWR 

nPORESET 


BDAT[0..7] 

nWE 

Spare 

CE1 

FUNC_SEL2 

FUNC_SEL1 

FUNC_SEL0 

CLK 

INPUT 

INPUT 

ADDR[23..21] 

nCS 

Address_Control 

GLOBAL 

INPUT 

nCS_ATM25 

nCS_ATM155 

nCS_T1_E1 



SYSCLK 

SYSCLK 

nCS_ATM25 

nTS 

RD_nWR 

nOE 

nWE 

nHRESET 

SYSCLK 

RD_nWR 

nCS_Framer 

nCS_ATM155 

nWE 

nOE 

nHRESET 

ATM25 

CLK 

ALE 

nCS 

nRD 

nTS 

nWR 

RD_nWR 

ADDR_OE_25 

nOE 

DATA_OE 

nWE 

nMUX_EN_BDAT 

nPORESET 

TP0 

TP1 

nCS_ATM25 

nCS_ATM155 

nCS_Framer 



nRESET_MII 

nMII_RX_EN 

nRESET_ATM25 

nRESET_ATM155 

nRESET_Framer 

BDAT_Comm[7..0] 

BDAT_Comm_En 

BDAT_SW[7..0] 

IPASEL0 

IPASEL1 

PDSEL0 

PDSEL1 

MUXSEL 

SPARE0 

SPARE1 

SPARE2 

BDAT_SW_En 

ATM155_Framer 

CLK 

RD_nWR 

nWR_ATM155 

nCS_Framer 

nRD_ATM155 

nCS_ATM155 

nWR_Framer 

nWE 

nRD_Framer 

nOE 

nPORESET 

ALE_ATM25 

nRD_ATM25 

nWR_ATM25 

ADDR_OE_25 

DATA_OE_25 

nMUX_EN_BDAT 

ATM25_TP0 

ATM25_TP1 

nWR_ATM155 

nRD_ATM155 

nWR_Framer 

nRD_Framer 

SYSCLK 

nHRESET 

BDAT_SW_En 

BDAT_Comm_En 

DATA_OE_25 


BDAT_SW[7..0] 

RD_nWR 

ADDR_PQ[21..31] 

nCS_ATM155 

nCS_Framer 

ADDR_OE_25 

nCS_ATM25 

nWE 

nWR_ATM25 

nWR_Dual 

nMUX_EN_BDAT 

ALE_ATM25 

nRD_ATM25 

AND2 

AND2 

nWR_Dual 

nRD_Dual 

mux_862/6 


muxTP0 

muxTP0 

muxTP1 

WIRE 

WIRE 

WIRE 

WIRE 

OUTPUT 

OUTPUT 

BDAT[0..7] 

AD_ATM[7..0] 

MD[7..0] 

muxTP0 

muxTP1 



OUTPUT 

OUTPUT 

TP3 

TP4 

TP1 

TP2 

mpc862db@91 

mpc862db@101 

mpc862db@111 

mpc862db@87 

GND 

VCC 

OUTPUT 

OUTPUT 

OUTPUT 

BIDIR 

BIDIR 

BIDIR 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

OUTPUT 

ALE_ATM25 

nRD_ATM25 

nWR_ATM25 

MD[7..0] 

BDAT[0..7] 

AD_ATM[7..0] 

nWR_Dual 

nRD_Dual 

nCS_ATM25 

nCS_Framer 

nRESET_MII 

nMII_RX_EN 

nRESET_ATM155 

IPASEL0 

IPASEL1 

PDSEL0 

PDSEL1 

MUXSEL 

ATMADCNT 

MPSEL_155 

mpc862db@72 

mpc862db@116 

mpc862db@88 

mpc862db@102 

mpc862db@113 

mpc862db@55 

nCS_ATM155 mpc862db@71 

mpc862db@117 

mpc862db@60 

mpc862db@68 

nRESET_ATM25 mpc862db@70 

mpc862db@74 

nRESET_Framer mpc862db@119 

mpc862db@45 

mpc862db@61 

mpc862db@56 

mpc862db@84 

mpc862db@86 

mpc862db@110 

mpc862db@109 

TITLE 

MPC862DB - MAIN 

COMPANY 

Motorola Semiconductor 

DESIGNER 

SIZE 

Yehuda Palchan 

NUMBER REV 

D 1.00 

144_0.1 

OF 

DATE SHEET 

2:15p 4-21-2002 

1 2


2•0•4 Block called nux_862/6 

RD_nWR 

ADDR_PQ[21..31] 

nCS_ATM155 

nCS_Framer 

ADDR_OE_25 

nCS_ATM25 

nWE 

nWR_ATM25 

nWR_Dual 

MUX_EN_BDAT 

ALE_ATM25 

nRD_ATM25 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

CLK 

nPORESET 

BDAT_SW_En 

BDAT_Comm_En 

DATA_OE_25 


BDAT_SW[7..0] 

nCS_ATM155 

nCS_Framer 

ADDR_OE_25 

NAND2 

nCS_ATM25 

nMUX_EN_BDAT 

nCS_ATM155 

nCS_Framer 

nWE 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

INPUT 

RD_nWR 

NOR2 

AND2 

AND2 

CS_Dual 

NOR2 

Freescale 




Inc. 

TRI 

BDAT[0..7] MD[7..0] 

NOR2 


WIDTH= 8 

BUSMUX 

nRD_ATM25 

NOT 

OR2 

BDAT_SW[7..0] dataa[] 

0 

BDAT_Comm[7..0] datab[] 1 

result[] 

MUX5[7..0] 

WIDTH= 8 

EN8 

NOT OR2 

EN6 sel 

AND2 

BUSMUX 

dataa[] 

0 

result[] 

datab[] 1 

sel 

TRI 

MUX6[7..0] BDAT[0..7] 

WIDTH= 8 

BUSMUX 

AD_ATM25[7..0] dataa[] 

0 

result[] 

MD[7..0] datab[] 1 

sel 

ADDR_PQ[24..31] 

BDAT[0..7] 

EN5 

ADDR_OE_25 

MUX7[7..0] 

NOT 

NAND3 

OR2 

WIDTH= 8 

BUSMUX 

dataa[] 

0 

result[] 

ADDR_ATM25[7..0] 

datab[] 1 

sel 

EN3 

nCS_ATM25 

nCS_ATM155 

nCS_Framer 

nWR_ATM25 

ADDR_OE_25 


TRI 

AD_ATM25[7..0] 



EN7 

EN_AD 

GND 

WIRE 

WIRE 

TITLE 

COMPANY 

DESIGNER 

BIDIR 

BIDIR 

BIDIR 

OUTPUT 

OUTPUT 

BDAT[0..7] 

AD_ATM25[7..0] 

MD[7..0] 

TP0 

TP1 

MPC862DB - MUX_862 

Motorola Semiconductor 

Yehuda Palchan 

SIZE 

D 

NUMBER 

1.00 

REV 144_0.1 

DATE OF 

SHEET 

11:17a 12-03-2001 

2 2


Freescale 




Inc. 


This module is one of the Altera internal module called: 

module ATM25( 

CLK , 

nCS, 

nTS, 

RD_nWR, 

nOE, 

nWE, 

nPORESET , 

ALE, 

nRD, 

nWR, 

ADDR_OE_25, 

DATA_OE, 

nMUX_EN_BDAT, 

TP0, 

TP1 

); 

/**************************************************/ 

/* Port Declaration */ 

/**************************************************/ 

input CLK; /*system clock*/ 

inputnCS;/*Chip Select */ 

inputnTS;/*PQ Transfer Start*/ 

inputRD_nWR; /*PQ Rd/Wr*/ 

inputnOE;/*PQ Output Enable*/ 

inputnWE;/*PQ Write Enable*/ 

input nPORESET;/*PQ Power On Reset*/ 

outputALE;/*ATM25 Address Latch Enable*/ 

outputnRD;/*ATM25 Read*/ 

outputnWR;/*ATM25 Write*/ 

outputADDR_OE_25;/*Address to ATM25 Output Enable*/ 

output DATA_OE;/*BDAT Output Enable*/ 

output nMUX_EN_BDAT;/*MUX Write BDAT to ATM25*/ 

output TP0; 

output TP1; 

reg DATA_OE_Reg; 

reg ADDR_OE; //ADDR lines to ATM25 Output Enable 

dff D_ALE(.d(!nTS), .clk(CLK), .q(delay_ALE)); 

always 

begin 

//Generate ATM25 controls 

ADDR_OE = !nTS || delay_ALE; 

//Send Address to ATM25 for an EXTENDED nTS signal//Send Data to ATM25 in whole WR cycle 

DATA_OE_Reg = !nOE; 





end 

Freescale 




Inc. 


assign DATA_OE = DATA_OE_Reg; 

assign ADDR_OE_25 = ADDR_OE; //address oe + hold time. 

assignALE = !nTS; 

assign nRD = !(!ADDR_OE && !nCS && !nOE);//Assert nRD only one CLK after ALE is done 

assign nWR = !(!ADDR_OE && !nCS && !nWE);//Assert nWR only after ALE is done; 

assign nMUX_EN_BDAT = delay_ALE;//MUX Enable BDAT Write to ATM25 

assignTP0= delay_ALE; 

assignTP1= delay_ALE; 

endmodule //ATM25 


module ATM155_Framer( 

CLK, 

RD_nWR, 

nCS_Framer, 

nCS_ATM155, 

nWE, 

nOE, 

nWR_ATM155, 

nRD_ATM155, 

nWR_Framer, 

nRD_Framer, 

nPORESET); 

//Port Declaration 

input CLK; //PQ Bus Clock 50MHz 

input RD_nWR; //PQ Bus Signal 

input nCS_Framer; //T1_E1 Framer Chip Select 

input nCS_ATM155; //ATM155 Chip Select 

input nWE;//PQ Bus Signal 

input nOE;//PQ Bus Signal 

input nPORESET;//Power On Reset 

output nWR_ATM155;//Write ATM155 command 

output nRD_ATM155;//Read ATM155 command 

output nWR_Framer;//Write Framer command 

output nRD_Framer;//Read Framer command 

assign nWR_ATM155 = nCS_ATM155 || nWE; 

assign nRD_ATM155 = nCS_ATM155 || nOE; 

assign nWR_Framer = nCS_Framer || nWE; 

assign nRD_Framer = nCS_Framer || nOE; 

endmodule //ATM155_Framer 





Freescale 




Inc. 



module Address_Control ( 

ADDR, 

nCS, 

nCS_ATM25, 

nCS_ATM155, 

nCS_T1_E1, 

nCS_ControlReg1, 

nCS_ControlReg2); 

//Port Declaration 

input [23:21] ADDR; //PQ Address 

input nCS;//PQ nCS5 

output nCS_ATM25; 

output nCS_ATM155; 

output nCS_T1_E1; 

output nCS_ControlReg1; 

output nCS_ControlReg2; 

assign nCS_ATM25 = !((!nCS)&&(ADDR==0)); 

assign nCS_ATM155 = !((!nCS)&&(ADDR==1)); 

assign nCS_T1_E1 = !((!nCS)&&(ADDR==2)); 

assign nCS_ControlReg1 = !((!nCS)&&(ADDR==3)); 

assign nCS_ControlReg2 = !((!nCS)&&(ADDR==4)); 

endmodule //Address_Control 


module COMM_CNTL( 

CLK , 

nCS, 

RD_nWR, 

nPORESET , 

BDAT_IN, 

nWE, 

nRESET_MII, 

nMII_RX_EN, 

nRESET_ATM25, 

nRESET_ATM155, 

nRESET_Framer, 

BDAT_OUT, 

Comm_Cntl_Rd_En 

); 

/**************************************************/ 

/* Port Declaration */ 

/**************************************************/ 

input CLK; /*system clock */ 

inputnCS;/*Chip Select */ 

inputRD_nWR; /*PQ Rd/Wr*/ 





input nPORESET;/*PQ Power On Reset*/ 

input [7:0]BDAT_IN;/*PQ Data Bus*/ 

input nWE;/*PQ Data Bus Write Enable*/ 

output nRESET_MII;//Reset MII 

output nMII_RX_EN;//RX Enable MII 

output nRESET_ATM25;//Reset ATM25 

output nRESET_ATM155;//Reset ATM155 

output nRESET_Framer;//Reset E1_T1 Framer 

output [7:0] BDAT_OUT;/*PQ Data Bus*/ 

output Comm_Cntl_Rd_En; /*Enable BDAT Output TRI*/ 

reg [7:0] Comm_Cntl_Reg;//Communication Control Register 

reg Comm_Cntl_Wr;//Write Comm Reg 

reg Comm_Cntl_Rd;//Read Comm Reg 

always 

begin 

Comm_Cntl_Wr = (!nCS)&&(!nWE); 

Comm_Cntl_Rd = (!nCS)&&(RD_nWR); 

end 

always @(posedge CLK) 

begin 

if (!nPORESET) 

begin 

Comm_Cntl_Reg = 0; 

end 

else if (Comm_Cntl_Wr) 

begin 

Comm_Cntl_Reg = BDAT_IN; 

end 

end 

Freescale 




Inc. 

assign Comm_Cntl_Rd_En = Comm_Cntl_Rd; 

assign BDAT_OUT = Comm_Cntl_Reg; 

assign nRESET_MII = !(Comm_Cntl_Reg[0] || (!nPORESET)); 

assign nMII_RX_EN = !(Comm_Cntl_Reg[1] || (!nPORESET)); 

assign nRESET_ATM25 = !(Comm_Cntl_Reg[2] || (!nPORESET)); 

assign nRESET_ATM155 = !(Comm_Cntl_Reg[3] || (!nPORESET)); 

assign nRESET_Framer = !(Comm_Cntl_Reg[4] || (!nPORESET)); 

endmodule //COMM_CNTL 



module SW_CNTL( 

CLK, 

RD_nWR, 

nPORESET, 

nCS, 

BDAT, 





nWE, 

BDAT_OUT, 

IPASEL0, 

IPASEL1, 

PDSEL0, 

PDSEL1, 

MUXSEL, 

SPARE0, 

SPARE1, 

SPARE2, 

RD_SW_CNTL_En, 

CE2, 

CE1, 

FUNC_SEL2, 

FUNC_SEL1, 

FUNC_SEL0 

); 

// Port Declaration 

inputCLK;//Bus Clock 

inputRD_nWR;//PQ Bus Signal 

inputnPORESET;//Power On Reset 

input nCS;//Chip Select 

input [7:0] BDAT;//PQ Data Bus 

input nWE;//PQ Bus signal Write Enable 

input CE2; 

inputCE1; 

inputFUNC_SEL2; 



output [7:0] BDAT_OUT;//PQ Data Bus 

output IPASEL0; 

outputIPASEL1; 

outputPDSEL0; 

outputPDSEL1; 

outputMUXSEL; 

outputSPARE0; 

outputSPARE1; 

outputSPARE2; 

output RD_SW_CNTL_En;// Control Enable BDAT output 

reg [7:0] SW_Control_Reg;//Switch Control Register 7 bit wide 

reg WR_SW_CNTL;//Write SW_CNTL command 

reg RD_SW_CNTL;//Read SW_CNTL command 

always 

begin 

//WR_SW_CNTL= (!nCS)&&(!RD_nWR); 

RD_SW_CNTL= (!nCS)&&(RD_nWR); 

end 

always @(negedge nWE or negedge nPORESET) 

begin 

Freescale 




Inc. 






if (!nPORESET) 

begin 

SW_Control_Reg =0; 

end 

else if (!RD_SW_CNTL) 

begin 

SW_Control_Reg[0] = CE1; 

SW_Control_Reg[1] = CE2; 

SW_Control_Reg[2] = FUNC_SEL0; 



end 

end 

Freescale 




Inc. 


assign RD_SW_CNTL_En = RD_SW_CNTL; 

assign BDAT_OUT = SW_Control_Reg; 

assign IPASEL0 = (!FUNC_SEL0 && !FUNC_SEL1 && !FUNC_SEL2) || 

(FUNC_SEL0 && !FUNC_SEL1 && !FUNC_SEL2) || 

(FUNC_SEL0 && !FUNC_SEL1 && FUNC_SEL2); 

assign IPASEL1 = (!FUNC_SEL0 && !FUNC_SEL1 && !FUNC_SEL2) || 

(!FUNC_SEL0 && !FUNC_SEL1 && FUNC_SEL2) || 

(!FUNC_SEL0 && FUNC_SEL1 && FUNC_SEL2) || 

(FUNC_SEL0 && !FUNC_SEL1 && FUNC_SEL2); 

assign PDSEL1 = !((!FUNC_SEL0 && !FUNC_SEL1 && !FUNC_SEL2) || 

(!FUNC_SEL0 && !FUNC_SEL1 && FUNC_SEL2)); 

assign PDSEL0 = (FUNC_SEL0 && FUNC_SEL1 && FUNC_SEL2 || 

FUNC_SEL0 && FUNC_SEL1 && !FUNC_SEL2); 

assign MUXSEL = !((!FUNC_SEL0 && FUNC_SEL1 && !FUNC_SEL2) || 

(!FUNC_SEL0 && FUNC_SEL1 && FUNC_SEL2)); //0; //SW_Control_Reg[4]; 

assign SPARE0 = SW_Control_Reg[5]; 



endmodule //SW_CNTL 





Freescale 




Inc. 


APPENDIX C - ADI I/F 

The ADI parallel port supplies parallel link from the MPC86xADS to various host computers. This port is 

connected via a 37 line cable to a special board called ADI (Application Development Interface) installed 

in the host computer. Four versions of the ADI board are available to support connection to IBM-PC/XT/ 

AT, MAC II, VMEbus computers and SUN-4 SPARC stations. It is possible to connect the MPC281ADS 

board to these computers provided that the appropriate software drivers are installed on them. 

Each MPC281ADS can have 8 possible slave addresses set for its ADI port, enabling up to 8 MPC281ADS 

boards to be connected to the same ADI board. 

The ADI port connector is a 37 pin, male, D type connector. The connection between the MPC281ADS and 

the host computer is by a 37 line flat cable, supplied with the ADI board. FIGURE A-1 below shows the pin 

configuration of the connector. 

FIGURE A-1 ADI Port Connector 

NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the MPC281ADS. 

C•1 ADI Port Signal Description 

The ADI port on the MPC281ADS was slightly modified to generate either hard reset or soft reset. This 

feature was added to comply with the MPC’s reset mechanism. 

In the list below, the directions ’I’, ’O’, and ’I/O’ are relative to the MPC86xADS board. (I.E. ’I’ means input 

to the MPC86xADS) 

NOTE: 

Since the ADI was originated for the DSP56001ADS some of 

its signals throughout the boards it was used with, were 

designated with the prefix "ADS". This convention is kept with 

this design also. 

• ADS_SEL(0:2) - ’I’ 

Gnd 20 

1 N.C. 

Gnd 21 

2 D_C~ 

Gnd 22 

3 HST_ACK 

Gnd 23 

4 ADS_SRESET 

Gnd 24 

5 ADS_HRESET 

Gnd 25 

6 ADS_SEL2 

(+ 12 v) N.C. 26 

7 ADS_SEL1 

HOST_VCC 27 

8 ADS_SEL0 

HOST_VCC 28 

9 HOST_REQ 

HOST_VCC 29 

10 ADS_REQ 

ADS_ACK 

HOST_ENABLE~ 30 

11 

Gnd 31 

12 N.C. 

Gnd 32 

13 N.C. 

Gnd 33 

14 N.C. 

PD0 34 

15 N.C. 

PD2 35 

16 PD1 

PD4 36 

17 PD3 

18 PD5 

PD6 37 19 PD7 





Freescale 




Inc. 


These three input lines determine the slave address of the MPC86xADS being accessed by the 

host computer. Up to 8 boards can be addressed by one ADI board. 

• ADS_SRESET - ’I’ 

This input line is used to generate Soft Reset for the MPC. When an ads is selected and this line 

is asserted by the host computer, Soft Reset will be generated to the MPC along with the Soft 

Reset configuration applied during that sequence. 

• HOST_ENABLE~ - ’I’ 

This line is always driven low by the ADI board. When an ADI is connected to the MPC86xADS, 

this signals enabled the operation of the debug port controller. Otherwise the debug port controller 

is disabled and its outputs are tri-stated. 

• ADS_HRESET - ’I’ 

When a host is connected, this line is used in conjunction with the addressing lines to generate 

a Hard Reset to the MPC86xADS board. When this signal is driven in conjunction with the 

ADS_SRESET signal, the ADI I/F state machines and registers are reset. 

• HOST_REQ -’I’ 

This signal initiates a host to MPC86xADS write cycle. 

• ADS_ACK - ’O’ 

This signal is the MPC86xADS response to the HOST_REQ signal, indicating that the board has 

detected the assertion of HOST_REQ. 

• ADS_REQ - ’O’ 

This signal initiates an MPC86xADS to host write cycle. 

• HST_ACK - ’I’ 

This signal serves as the host’s response to the ADS_REQ signal. 

• HOST_VCC - ’I’ (three lines) 

These lines are power lines from the host computer. In the MPC86xADS, these lines are used 

by the hardware to determine if the host computer is powered on. 

• PD(0:7) - ’I/O’ 

These eight I/O lines are the parallel data bus. This bus is used to transmit and receive data from the host 

computer. 





D•1 INTRODUCTION 

Freescale 




Inc. 


APPENDIX D - ADI Installation 

This appendix describes the hardware installation of the ADI board into various host computers. 

The installation instructions cover the following host computers: 

1) IBM-PC/XT/AT 

2) SUN - 4 (SBus interface) 

D•2 IBM-PC/XT/AT to MPC86xADS Interface 

The ADI board should be installed in one of the IBM-PC/XT/AT motherboard system expansion slots. A 

single ADI can control up to eight MPC86xADS boards. The ADI address in the computer is configured to 

be at I/O memory addresses 100-102 (hex), but it may be reconfigured for an alternate address space. 

CAUTION 

BEFORE REMOVING OR INSTALLING ANY 

EQUIPMENT IN THE IBM-PC/XT/AT 

D•2•1 

COMPUTER, TURN THE POWER OFF AND 

REMOVE THE POWER CORD. 

ADI Installation in IBM-PC/XT/AT 

Refer to the appropriate Installation and Setup manual of the IBM-PC/XT/AT computer for instructions on 

removing the computer cover. 

The ADI board address block should be configured at a free I/O address space in the computer. The 

address must be unique and it must not fall within the address range of another card installed in the 

computer. 

The ADI board address block can be configured to start at one of the three following addresses: 

• $100 - This address is unassigned in the IBM-PC 

• $200 - This address is usually used for the game port 

• $300 - This address is defined as a prototype port 

The ADI board is factory configured for address decoding at 100-102 hex in the IBM-PC/XT/AT I/O address 

map. These are undefined peripheral addresses. 





Freescale 




Inc. 


FIGURE B-1 Physical Location of jumper JG1 and JG2 

JG1 JG2 

NOTE: Jumper JG2 should be left unconnected. 

The following figure shows the required jumper connection for each address configuration. Address 0 hex 

is not recommended, and its usage might cause problems. 

FIGURE B-2 JG1 Configuration Options 

0 hex 100 hex 200 hex 300 hex 

To properly install the ADI board, position its front bottom corner in the plastic card guide channel at the 

front of the IBM-PC/XT/AT chassis. Keeping the top of the ADI board level and any ribbon cables out of the 

way, lower the board until its connectors are aligned with the computer expansion slot connectors. Using 

evenly distributed pressure, press the ADI board straight down until it seats in the expansion slot. 

Secure the ADI board to the computer chassis using the bracket retaining screw. Refer to the computer 

Installation and Setup manual for instructions on reinstalling the computer cover. 

D•3 SUN-4 to MPC86xADS Interface 

The ADI board should be installed in one of the SBus expansion slots in the Sun-4 SPARCstation 

computer. A single ADI can control up to eight MPC86xADS boards. 





Freescale 




Inc. 


CAUTION 

BEFORE REMOVING OR INSTALLING ANY 

EQUIPMENT IN THE SUN-4 COMPUTER, TURN 

THE POWER OFF AND REMOVE THE POWER 

CORD. 

D•3•1 ADI Installation in the SUN-4 

There are no jumper options on the ADI board for the Sun-4 computer. The ADI board can be inserted into 

any available SBus expansion slot on the motherboard. 

Refer to the appropriate Installation and Setup manual for the Sun-4 computer for instructions on removing 

the computer cover and installing the board in an expansion slot. 

ADI 

Connector 

FIGURE B-3 ADI board for SBus 

SBus 

Connector 

Following is a summary of the Instructions in the Sun manual: 

1. Turn off power to the system, but keep the power cord plugged in. Be sure to save all open files and 

then the following steps should shut down your system: 

• hostname% /bin/su 

• Password: mypasswd 

• hostname# /usr/etc/halt 

• wait for the following messages. 

Syncing file systems... done 

Halted 

Program Terminated 

Type b(boot), c(continue), n(new command mode) 

• When these messages appear, you can safely turn off the power to the system unit. 

2. Open the system unit. Be sure to attach a grounding strap to your wrist and to the metal casing of the 

power supply. Follow the instructions supplied with your system to gain access to the SBus slots. 

3. Remove the SBus slot filler panel for the desired slot from the inner surface of the back panel of the 

system unit. Note that the ADI board is a slave only board and thus will function in any available SBus 

slot. 

4. Slide the ADI board at an angle into the back panel of the system unit. Make sure that the mounting 

plate on the ADI board hooks into the holes on the back panel of the system unit. 





Freescale 




Inc. 


5. Push the ADI board against the back panel and align the connector with its mate and gently press 

the corners of the board to seat the connector firmly. 

6. Close the system unit. 

7. Connect the 37 pin interface flat cable to the ADI board and secure. 

8. Turn power on to the system unit and check for proper operation.

MPC866 Application Development System Users Manual

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