SI-9147B DUAL-CHANNEL 6U VXS VHF/UHF DIGITAL TUNER

Photo courtesy of the U.S. Air Force, U.S. Navy & U.S. Army 

SI-9147B DUAL-CHANNEL 6U VXS VHF/UHF DIGITAL TUNER 

The DRS SI-9147B is a Dual-Channel Wideband VHF/UHF 

Tuner that provides independent or phase-coherent 

conversion of RF signals from 20 MHz to 3,000 MHz. An 

analog IF output is centered at 76.8 MHz. The SI-9147B 

also includes a digital back end that provides wideband 

16-bit analog-to-digital (A/D) converters, 12 ASIC digital 

downconverter channels, 12 FPGA-based digital 

downconverter channels, 1 GB of DDR3 memory, a user 

programmable field-programmable gate array (FPGA), time 

stamping of digital IF packets, and VRT (VITA 49) compliant 

data formatting. The tuner has a minimum tuning resolution 

of 1 MHz, but for high-speed scanning purposes, 

the tune resolution is in multiples of 5 MHz. 

The tuner features an internal Local Oscillator Distribution 

(LOD) assembly that allows it to accept or provide its 1st 

and 2nd LOs to up to eight phase coherent channels in a 

daisy-chain configuration without an external LOD module. 

Cleared by US DoD/OSR for Public Release under OSR case number 11-S-3157 dated 08.16.2011. 

SI-9147B Dual-Channel 6U VXS VHF/UHF Digital Tuner

Architecture 

A functional block diagram of the tuner is shown in Figure 2. Two 

independent RF tuners and LOD bricks are housed in a singlewidth 

6U form factor. Each brick is comprised of three printed 

circuit cards enclosed in a single machined aluminum chassis. 

The dual tuner/LOD modules are mounted on the main Digital 

Interface and Signal Processing (DISP) board. The DISP board 

provides control to the tuners, the digital downconverters (DDC) 

and the digital signal processing resources within the FPGAs. The 

DISP board also controls and implements the 10 gigabit Ethernet 

high-speed serial protocol by which digital IF data is transferred 

across the P0 connector. 

The SI-9147B also utilizes the VITA 41.6 gigabit Ethernet control 

plane over the P0 connector. Front-panel connectors are available 

for the RF inputs, IF outputs, internal and external 10 MHz 

reference, LO inputs and outputs, gigabit Ethernet interface and 

RS 232 control. 

RF Tuner Module 

Figure 1 provides a detailed block diagram of the SI-9147B tuner 

assembly. RF signals are filtered at the input, either voltage-tuned 

tracking preselectors or sub-octave preselectors. The voltage 

tuned tracking preselectors can be bypassed to enable full 40 

MHz bandwidth below 200 MHz. Following the preselector is a 

low-noise RF preamplifier that provides an excellent noise figure 

and gain to overcome the loss of the 1st IF mixer and IF filter. 

Frequency coverage from 20 to 3,000 MHz is provided by 

converting the signal to a 1st IF of 1,750 MHz or 610 MHz, 

using a 1st LO that tunes from 1,750 to 3,010 MHz in 1 MHz 

steps. The first IF is mixed with the 2nd LO signal producing the 

final IF centered at 76.8 MHz. The 2nd LO is fixed at 1,673.2 

MHz when the 1st IF corresponds to 1,750 MHz. When the 1st IF 

is centered at 610 MHz, the 2nd LO is fixed at either 533.2 MHz 

Cleared for Public Release. 

Figure 2: SI-9147B Architecture 

or 686.8 MHz. The 76.8 MHz IF is always inverted with 

respect to the to the RF input. Two cascaded surface 

acoustic wave (SAW) filters are used to limit the bandwidth 

of the 76.8 MHz final IF to 40 MHz. SAW filters achieve 

an excellent shape factor with minimal phase and 

amplitude distortion. 

The end of the second conversion stage provides a front 

panel sample output for the 76.8 MHz IF and the amplification 

needed to interface to the A/D converter module. 

Fast Tuning (Turbo Mode) 

The tuner module has two software-selectable tuning modes. 

In normal tuning mode, the module has a typical tuning 

speed of 300 microseconds and exceptional close-in phase 

noise performance. In turbo tuning mode, the downconverter 

has a typical tuning speed of 50 microseconds with slightly 

degraded phase noise performance. The phase noise 

performance of these modes is listed in the specification table. 

Attenuation Control 

There is over 60 dB of available attenuation range in the 

SI9147B tuner. The default attenuation implementation 

makes use of the values from 0 to 46 dB. This attenuation is 

distributed across three sections of the signal path (the 32 

dB front-end RF attenuator, 7 dB RF attenuator and 31 dB 

second IF step attenuator). The attenuation is distributed 

across these three attenuators based on an internal 

attenuation table, which is designed to maximize dynamic 

range versus signal level. There are several commands for 

each channel to allow individual channel attenuation control. 

The minimum step size for attenuation is 1 dB.

LO Distribution 

As shown in Figure 1, the LO signals can be produced within the 

tuner module or they can be received externally via circuits on the 

LO distribution board (part of the 9147B module). The LO 

distribution circuitry allows a tuner to act as a master, a slave or 

an independent tuner. The master tuner drives out its 1st and 2nd 

LO signals for use by slave tuners, which use the input LOs for 

RF/IF conversions. An independent tuner, acting in a non-phase 

coherent mode, neither drives out nor accepts external LOs. Up 

to eight tuners channels can be daisy-chained for phase coherent 

operation. Phase coherent systems of more than eight channels 

can be achieved by using an external LO distribution module. 

ADC processing module 

The A/D Converter (Digitizer) module contains two 16-bit ADC 

devices that sample the 76.8 MHz IF at a sampling rate of 102.4 

MSPS. The 40 MHz IF bandwidth is digitally downconverted to an 

IF centered at 25.6 MHz. The ADC operates on with an internal 

102.4 MHz ADC master clock, or from an external clock source 

via its front-panel SSMC connector. This clock source is software 

selectable. Sampled data from the ADC module is output via 

low-voltage differential serial (LVDS) interface to the DISP module 

for processing by the FPGA circuitry. 

Digital Signal Processing Overview 

The main DISP board contains all of the hardware and firmware to 

provide the SI-9147B with its extensive digital signal processing 

(DSP) capabilities. The DSP section is based on FPGA and 

Application Specific Integrated Circuit (ASIC) components that 

offer programming flexibility. 

The SI-9147B DSP section consists of two independent 16-bit 

A/D converters, a 102.4 MHz internal A/D clock source, an 

FPGA for data buffering, processing, and formatting, 12 

ASIC-based DDC channels, 12 FPGA-based DDC channels, 

1-GigaByte of memory and front-panel multi-pin connectors for 

auxiliary control and synchronization signals. The outputs of the 

A/D converters are routed to a Virtex®6 FPGA located on the 

DISP board. The FPGA provides the ability to route the dual 

real-time digital IF packet streams to the memory devices for 

delay or any of the 24 DDC channels. 

The FPGA can be configured to perform a host of DSP 

functions including digital channelization in addition to that 

provided by the 24 DDCs, digital filtering, spectral analysis, 

or demodulation. 

The digital IF streams (real-time, delayed, DDC channelized, or 

otherwise processed digital IF packet streams ) are formatted 

according to the VITA 49 (VRT) data packet protocol. The VRT 

packets are transmitted over the SI-9147B’s P0 connector using 

the multi-gigabit transceiver cores embedded within the FPGA in 

compliance with 10 gigabit Ethernet (VITA 41.8) protocol. 


Digital Downconverters (DDCs) 

The SI-9147B allows programmable DDCs to be implemented 

both in ASICs and in the FPGAs. The architecture provides 12 

ASIC DDCs each with a decimation range from 1 to 32,768 and 

capable of tuning to anywhere within the digitized 40 MHz IF BW 

signal. These DDCs may provide output bandwidths from 1 kHz 

to 5 MHz. The DDCs also provide other features such as digital 

automatic gain control and programmable digital filtering. The 

FPGA also includes a special dedicated wide-band DDCs that 

produce 10 or 20 MHz bandwidth output. 

DSP Data Routing 

Dual wideband A/D converters digitize the full 40 MHz of analog 

bandwidth for both channels. These data streams are time tagged 

at the beginning of the process in the FPGA. The digitized data 

can then be routed to the FFTs, ASIC DDCs, FPGA DDCs or 

memory for digital signal processing purposes. Thus, any of the 

DDC resources can be dynamically driven by any of the A/D input 

signals or by a signal delayed or processed within the FPGA. 

Also, the same signal can be routed through two or more DDC 

resources to provide further signal processing and resolution. 

The serialized digital IF packets driven out the VITA 41 (XVS) P0 

connector can consist of raw digital IF data directly from the A/D 

Converters or of digital IF data processed or delayed by the FPGA 

or the ASIC DDCs or both. All data is time tagged and marked with 

the tuner related context fields (frequency, attenuation, etc.) in 

accordance with the VRT (VITA 49) standard. 

Streaming Digital IF 

The digital data output is fully compatible with industry standard 

hardware interface definitions identified in the VITA 41 (VXS) 

specification. It provides eight high-speed Serializer/Deserializer 

(SERDES) output streams at data rates up to 3.125 Gbps with 

each 8b/10b encoded digital stream providing a maximum data 

throughput of 2.5 Gbps for each SERDES. The SI-9147B is 

compliant with the 10 gigabit Ethernet (draft VITA 41.8) as well 

as the gigabit Ethernet control plane (VITA 41.6) extensions. 

Control Interface 

In addition to signal processing, the other major function of the 

DISP board is to provide control over the operations of the SI- 

9147B digital tuner. The DISP board supports control using its 

VME, gigabit Ethernet, and RS-232 interfaces. User control and 

status of the tuner is provided via the gigabit Ethernet (either P0 

or front panel). The gigabit Ethernet data transfers are handled by 

the PPC. User commands and queries are processed by the 

embedded logic within the FPGA and the appropriate control bits 

are sent to the programmable elements of the tuners and ASIC DDCs. 

In addition to gigabit Ethernet and RS-232, the front-panel 

connector provides hardware tune strobe signals used in the 

digital tuner’s frequency scan modes. In step mode, the user can 

predefine up to 128 tuner frequency and attenuation settings 

(i.e., steps) per channel to provide for the use of very 

sophisticated tuner scanning procedures.

SPECIFICATIONS 

General architecture Two 20 MHz to 3 GHz independent 

or coherent digital tuner channels 

in a single-slot 6U VITA 41 (VXS) 

form factor 

Frequency range 20 to 3,000 MHz 

Preselector filters Voltage-tuned 30 to 459 MHz 

(~30% 3 dB bandwidth) 

Fixed sub-octave 460 to 3,000 MHz 

Bypass ≤ 225 MHz 

Tuning step size 1 MHz (normal mode, MHz 

frequency resolution) 

5 MHz (turbo mode, MHz 

frequency resolution) 

Tuning speed ≤ 300 microseconds typical for 

normal mode tuning 

≤ 1135 microseconds worst-case 

for normal mode tuning (Note 1) 

≤ 50 microseconds typical for turbo 

mode tuning 

≤ 465 microseconds worst-case 

for turbo mode tuning (Note 1) 

SSB phase noise (normal tuning mode) (Note 2) 

1 kHz offset -80 dBc/Hz, typical 



1 MHz offset -130 dBc/Hz, typical 

SSB phase noise (turbo tuning mode)(Note 2) 




1 MHz offset -120 dBc/Hz, typical 

INTERNAL REFERENCE 

Frequency 10 MHz 

Reference stability ±0.3 ppm (0ºC to +70ºC) 

Input/output connector type SSMC female 

Output level 0 dBm ±3 dB into 50 ohms 

External operation method Phase locked loop 

200 Hz loop bandwidth 

External reference frequency 10 MHz ±5 ppm 

External input level 0 dBm ±3 dB 


SPURIOUS PERFORMANCE 

In-band input third-order intercept point 

-5 dBm minimum (Note 3) 

Out-of-band input second-order intercept point 

+50 dBm typical 

+40 dBm minimum (Note 4) 

Image rejection TBR (30 to 1,199 MHz) 

70 dB (1,200 to 3,000 MHz) 

IF rejection 80 dB (30 to 3,000 MHz) 

Internally generated spurious < -100 dBm input equivalent 

Channel-to-channel isolation 60 dB minimum 

RF INPUT 

Connector type SMA female 

Impedance 50 ohms nominal 

VSWR at tuned frequency 2.0:1 typical 

3.0:1 maximum 

Input power without damage +20 dBm maximum 

Conducted LO at input -90 dBm typical 

-80 dBm maximum 

Noise figure at maximum gain 12 dB typical (30 to 3,000 

MHz) 14 dB maximum (30 to 

3,000 MHz) (Note 5) 

GAIN 

Overall gain 30 dB nominal 

(at A/D converter stage) (30 to 3,000 MHz) 

Gain variation ± 2 dB (30 to 3,000 MHz) 

Gain control range (default) 47 dB in 1 dB steps 

IF PASSBAND CHARACTERISTICS 

3 dB bandwidth 40 MHz nominal (two 

cascaded 40 MHz SAW 

filters), from 200 MHz to 

3 GHz 

Shape factor 1.3:1 (80:3 dB) 

Amplitude variation ±2 dB (30 to 3,000 MHz) 

Group delay variation ±90 nanoseconds typical 

over 90% of 3 dB bandwidth 

76.8 MHZ ANALOG IF OUTPUT 

Connector type SMA female 

Center frequency 76.8 MHz 


Gain relative to RF input 30 dB nominal

LO OUTPUTS 

Output level (master mode) 0 to +10 dBm (1st LO) 

+4 to +12 dBm (2nd LO) 

Input level (slave mode) -2 dBm minimum 


LO distribution connector type SSMC 

DSP SPECIFICATIONS 

A/D converter Dual LTC2208 16-bit 

A/D converters @ 102.4 

MSPS rate 

Dithering noise LTC2208 internal dithering 

enabled/disabled via software 

Two-tone spur-free dynamic 80 dB, typical (Note 6) 

range (with tuner) 

Single-tone spur-free dynamic 85 dB, typical (Note 6) 

range (with tuner) 

Sampling clock rate 102.4 MHz 

Clock input/output level +6 dBm ±3 dB into 50 ohms 

Time stamp Referenced to 1 PPS front panel 

input 

P0 digital IF data Rear-panel VXS P0, high-speed 

output protocol serial interface that is compliant 

with VITA 41.8; 

10 gigabit Ethernet 

Digital IF data VITA 49 – VRT compliant data 

packet formatting and time tag formats 

Digital IF output data types Real-time 102.4 MSPS 

ADC samples 

Delayed 102.4 MSPS 

ADC samples 

DDC outputs tuned to real-time 

or delayed ADC data (Note 7) 

Number of DDC channels 2 AD6636 devices provide 12 

independently tunable DDC 

channels each with a decimation 

range from 1 to 32,768 and with 

possible bandwidths from 1 kHz 

to 7 MHz 

Stored default DDC 32 defaults (bandwidths 

bandwidths ranging from 15 kHz to 5 MHz) 

Internal frequency scan 128 per channel frequency/gain 

steps 


FPGA dynamically Processor image can be upgraded 

downloadable from via 1G Ethernet (front panel or 

the processor via back panel) 

Front panel serial control Gigabit Ethernet & RS-232 

Weight 2.6 lbs. (1.18 kg) maximum 

Size Single-slot 6U VXS 

(160 x 230 mm) 

Power consumption 

Temperature 

TBD Watts (Note 8) 

Operational (convection-cooled) 0ºC to +50ºC ambient with 

600 CFM airflow 

Non-operational -40ºC to +70ºC 

Specification-compliant +25ºC ± 5ºC ambient with 

15 CFM airflow 

Altitude Operational at 10,000 feet 

(maximum ambient +20ºC) 

Vibration 

Operational Tested per DO-160D, section 8, 

category S2 

Shock 

Operational DO-160D, section 7, category E 

Notes: 

(1) Measured from receipt of tune command to within 1 kHz of desired frequency at 

76.8 MHz IF analog output. Tuning across second LO band breaks and sub MHz 

steps will require additional settling time. 

(2) Measured from RF through final IF, with 1-MHz tuning resolution only. In Turbo 

Tuning Mode, measured from RF through final IF, with 5 MHz tuning resolution only. 

Plots showing measured close-in phase noise performance data at 1 Hz to 1 kHz 

offsets are available upon request. 

(3) Measured with two tones inside the final IF bandwidth, at -7 dBFS. Attenuation set 

to 0 dB. Tuned frequencies of 30 to 3000 MHz. In-band intercept point 

specifications are referenced to the 76.8 MHz IF output only. 

(4) Measured with two tones outside the RF preselector passband. Attenuation set to 

0 dB. Tuned frequencies of 30 to 3,000 MHz. Input second-order intercept point 

performance will degrade when the preselector-bypass path is selected. 

(5) Noise figure specification assumes non-coherent (independent) tuner operation. In 

an N-channel daisy-chained coherent implementation, expect typical and worstcase 

noise figure specs to increase by a maximum of N/2 dB at the slave channel 

farthest from the master channel. 

(6) Two tones at -7 dBFS or a single-tone at -1 dBFS will not produce spurious signals 

greater than –80 dBFS or –85 dBFS respectively. Measured with tuner attenuation 

set to 0 dB, and dither enabled. 

(7) Initial outputs supported will include real-time and delayed ADC samples that are 

time stamped. Outputs from the ASIC DDC channels will also be supported. Other 

possible formats will follow in later revisions of this product. 

(8) Typical steady-state power consumption of base SI-9147B configuration at +25°C 

ambient in non-phase-coherent (independent) and normal tuning speed mode. 

Expect up to 3.0 Watt higher when in phase-coherent (Master/Slave) and turbo 

tuning speed mode. Requires +3.3V, +5V, and +12V VME supply voltages.

HIGHLIGHTS 

• Two wideband tuner channels in a single-slot 6U 

ANSI/VITA 41.0 (XVS) compliant card 

• 20 MHz to 3 GHz frequency range 

• 40 MHz instantaneous IF bandwidth (20% bandwidth 

below 200 MHz when voltage-tuned tracking preselectors 

are engaged) 

• 76.8 MHz analog IF output 

• 102.4 MHz sampling rate 

• 16-bit A/D converters 

• Data transferred via 10 gigabit Ethernet (draft VITA 41.8) 

over 8 high-speed SERDES channels (each @ 3.125 Gbps) 

on the P0 connector 

• Out of band Gigabit Ethernet control on P0 (VITA 41.6) 

• Front panel GigE I/O 

• VITA 49 (VRT) digital IF formatting 

All trademarks and registered trademarks are the property of their respective owners. 

DRS ICAS, LLC. 

21 Continental Boulevard, Merrimack, NH 03054 Tel: 603.429.0111 Fax 603.429.0155 www.drs-ds.com marketing@drs-ds.com 

(AS 9100, Rev. C, ISO 9001:2008, CMMI Level 3, Registered Company) 

Cleared for Public Release – DS FSO Dated 13 July 2011. 

Figure 1: RF Converter Detailed Block Diagram 

• Software-selectable phase-coherency of up to 8 channels 

without external LO Distribution module 

• Typical 300-microsecond tuning speed in normal mode 

• Typical 50-microsecond tuning speed in turbo mode 

• Field Upgradable with network based booting capability 

• Participate into system wide health and status monitoring 

• VXS based redundancy capable 

• Frequency scan modes 

• 1 GByte DDR3 memory on the FPGA 

• 256 MBytes DDR2 memory on the embedded µP 

• 12 ASIC digital downconverter channels 

- 1-32,768 decimation range 

- DDC bandwidths of 1 kHz to 7 MHz 

- Configurable filtering & gain control 

• User programmable FPGA for DSP functions (call factory) 

• Ethernet, or RS-232 control 

Specifications subject to change without notice. Copyright © DRS ICAS, LLC 2012. All Rights Reserved. 

Export of DRS ICAS, LLC products may be subject to U.S. Export Controls. U.S. Export licenses may be required. 

DRS MER V11 01/09/11

SI-9147B DUAL-CHANNEL 6U VXS VHF/UHF DIGITAL TUNER

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