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COTS Enhanced vector graphics and S-RIO boost Intel in DSP applications By Ian Stalker, Curtiss-Wright Controls Embedded Computing The introduction of the new Intel Core i7-2715QE next-generation quad-core processor with the new AVX processing unit means the design of x86-based embedded military digital signal processing (DSP) systems can take a great leap forward. n The new Intel Core i7-2715QE processor, which is faster and more power efficient than its previous generation, also features the new 256-bit wide Intel Advanced Vector Extensions (AVX) floating-point instructions. DSP algorithms rely heavily on the throughput of vector instructions and so will benefit greatly. Before the introduction of Intel AVX, vectorized signal processing functions were limited to 128-bits. Of equal interest to signal processing system designers is the fact that with this platform, Serial RapidIO (S-RIO), the preferred fabric for the types of processor-to-processor communications required by demanding DSP systems, is now for the first time supported, thanks to the upcoming IDT PCIe Gen2 to S-RIO Gen2 protocol conversion bridging semiconductor products. This brings S-RIO, the fabric of choice, well supported by the OpenVPX/VITA 65 standard, to Intel-based open architecture system designs. Now the latest x86 processor can be used in a RapidIO based network, supporting reliable packet transmission, any architecture, while also delivering low and predictable latencies and providing the benefits of RapidIO messaging which are ideal for large peer-to-peer clusters of processors used in complex signal processing applications. For embedded DSP designers, the most recent Intel micro-architecture (codenamed micro-architecture Sandy Bridge) further establishes the x86 architecture as the leading candidate for the most demanding compute-intensive multiprocessor systems. The Intel quad-core processor boasts numerous micro-architecture enhancements and design features over previous Intel processors. For example, the new processor is faster at the same clock speeds as earlier processors, because of its more sophisticated caching and branch prediction. This platform also delivers quad-core processing with power levels that match the stringent requirements of rugged embedded military environments: 4 cores at 45 watts. But the single greatest improvement for DSP system performance delivered by the latest Intel platform is the new AVX processing unit. In recent years Intel has demonstrated its ongoing commitment to high-performance vectorized processing by investing in continual enhancements to the AVX predecessor, Intel Streaming SIMD Extensions (Intel SSE), a 128bit wide processing unit capable of simultaneously operating on four 32-bit floating-point values. Intel SSE also featured support for double-precision floating point, a feature that was not available in AltiVec. In Intel multicore processors each core was given its own SSE unit, so the raw floating-point performance scaled with the number of cores. In the new platform Intel has upgraded the SSE approach with AVX, doubling the size to 256-bits wide. This doubling of vector processing performance is a significant milestone in DSP system design. March 2011 18 DSP algorithms used in critical military applications such as radar, SIGINT, and image processing, depend on the precision achieved with floating point numbers along with speed of processing. The new Intel Core i7 effectively doubles that performance over previous approaches. For typical size 1D and 2D FFTs the improvement gained by AVX is in the 1.5 to 2X range (approximately) over SSE. The AVX instruction set was designed to support future extensions, which hints at wider implementations in the future. Further helping to establish Intel as the ideal platform for DSP applications is the addition of S-RIO support. For embedded and high performance applications S-RIO as of yet has no peer when it comes to multiprocessor system processor-to-processor communications. But prior to this generation of Core i7, there was no support for S-RIO for Intel platforms, which of course limited the viability of Intel architecture use in DSP multiprocessor systems. Solutions have been available to support Infiniband, which is popular in the cluster computing world but is not embraced in military applications, and for Gigabit Ethernet. For single board computers, where the requirement is typically a single processor communicating with I/O, these fabrics have been sufficient. The lack of support for S-RIO, however, deprived would-be Intel-based DSP system designers of the ability to select the multi-
processor fabric of choice. The upcoming IDT PCI Express (PCIe) Gen2 to S-RIO Gen2 bridge provides the first solution for S-RIO support on Intel-based platforms. The new S- RIO Gen 2 switches provide three times the aggregate bandwidth and are twice as fast as the earlier RapidIO 1.3 based switches per port. The signaling rate increase is from 3.125 Gbps to Gen2 6.25 Gbps for switch ports, resulting in 20 Gbps per second per port in the switch fabric. The IDT bridge will provide a mapping from PCIe Gen2 into this S-RIO Gen2 based switch on board and into the backplane. This bridge will support the two main S-RIO transfer modes, memory-mapped transfers and S-RIO messaging. S-RIO bridges implemented in FPGAs do not support highperformance messaging, a feature which directly maps to higher-level software APIs such as MPI. Another plus offered by the IDT silicon is the inclusion of DMA engines that speed computation while off-loading the host processor. Intel processors typically do not have DMA engines on-chip, but depend instead on the peripheral chip to move data. Without a DMA engine, moving data can require a large amount of the host processor attention, with the result that a multicore processor might have one of its cores (and associated power) largely consumed by moving data, which is all the more burdensome because it has to be done in code. The IDT bridge is physically much smaller and lower power than the 10 Gigabit Ethernet (10 GbE) alternatives today, while being 1.6x faster, which is great for SWaP-constrained systems. For in-the-box processor-to-processor connections, 10 GbE is over-featured, making both the controller and switch chips larger and slower than the equivalent S-RIO devices. Moreover in a 10 GbE network, reliable endto-end packet transmissions with reliable transport could take several milliseconds. Another advantage of S-RIO for space-constrained military systems is the ability to support all topologies,including either distributed switch or centralized switch architectures. Distributed switch systems (an example is the VITA 65 BPK6-CEN05-11.2.5-n backplane profile) make use of the local S-RIO switch and thus avoid the need for a separate switch card. For example, if the system was using a ½ ATR short enclosure (four 1” slots) this capability saves 25% of the space and a considerable amount of power. For large systems, centralized switch architectures are often preferred, and S-RIO is COTS equally adept at this approach. Many leading vendors offer S-RIO switch card solutions. An example of a high-performance DSP engine designed to take full advantage of the latest offering for Intel Core i7 is the new CHAMP-AV8 from Curtiss-Wright Controls Embedded Computing. The CHAMP-AV8 is the first rugged, high-performance OpenVPX DSP (digital signal processing) engine based on the Intel Core i7- 2715QE. It also supports the upcoming IDT Gen2 PCIe-to-S-RIO protocol conversion bridge. The rugged CHAMP-AV8 pair of quad-core processors delivers performance, rated at up to 269 GFLOPS. With the IDT bridge chip, the CHAMP-AV8 supports Gen2 S-RIO and Gen2 PCIe interfaces, which enables it to deliver triple the bandwidth of first-generation VPX products with up to 240 Gbps of fabric performance, thus ensuring that application performance can scale commensurately with the much higher CPU performance. The CHAMP-AV8 is supported with an extensive suite of software including support for Wind River VxWorks and Linux operating environments. Additional software support includes inter-processor communications (IPC) and the Curtiss-Wright Control Continuum Vector AVX-optimized signal processing library. n
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