AMS-02 DAQ SYSTEM JBP Backplane Board HARDWARE ... - Cern

AMS-02 DAQ SYSTEM 

JBP Backplane Board 

HARDWARE DESIGN SPECIFICATION 

Document No. : 

CSIST-AMS-MDC-JBP-R05b 

March 4, 2003 

CSIST 

Electronics Systems Division

DOCUMENT NAME: 

APPROVAL and SIGNATURE 

AMS-02 JBP Backplane Board 

HARDWARE DESIGN SPECIFICATION 

Author: 

Checked: 

Checked: 

Approved: 

Yung-Chyn Chou/CSIST ╴╴╴╴╴╴ ╴╴╴ 

Name and Organization, SIGNATURE DATE 

Jan-Wu Hong /CSIST ╴╴╴╴╴╴ ╴╴╴ 


X. Cai /MIT ╴╴╴╴╴╴ ╴╴╴ 


╴╴╴╴╴╴╴╴╴ ╴╴╴╴╴╴ ╴╴╴ 


2

AMS-02 JBP Backplane Board Specification 

1. Compliant with the AMS-02 DAQ System J-Crate Requirements. 

2. 22-slot hybrid monolithic backplane for the AMS-02 DAQ System. 

3. AMS-02 Specific backplane according to AMS-02 backplane mechanical 

layout drawing (in preparation) 

4. Four CompactPCI segments are routed on P1 connector row. 

P2 connectors are installed only on the system slot positions. 

P3 connector row is not used at all. 

The CompactPCI segments are routed with the AMSWire, HRDL, 1553, 

and RS422 specifications for AMS-02 specific applications on P4 and P5 

Additional links are provided for connecting to the Slow Control System. 

Dallas temperature sensors bus in list of signals to route on P4. 

5. Each of the cPCI segments is: 

compliant with the CompactPCI core specification (PICMG 2.0 

R3.0), including the external +12V and -12V power lines connectors 

for ground test only. 

supporting 32-bit, 33 MHz PCI bus operation 

supplying separately of each other and non-cPCI modules 

3.3V V(I/O) signaling voltage only 

no Hot Swap capability 

no Rear I/O capability 

5-slot wide, one system and four I/O slots 

position of the AMS-02 specific I/O modules is predefined 

6. Slot assignment (front panel view, from left to right): 

1 JSBC-0 (system slot) ⎤ 

2 JIM-CAN-0 ⎮ 

3 JBU-0 ⎮ 

4 JIM-AMSW&1553-0 ⎮ JMDC-0 

5 JIM-HRDL/422-0 ⎦ 

6 JSBC-1 (system slot) ⎤ 


8 JBU-1 ⎮ 

9 JIM-AMSW&1553-1 ⎮ JMDC-1 

10 JIM-HRDL/422-1 ⎦ 

11 JHIF 

12 JLIF 

13 JIM-HRDL/422-2 ⎤ 

14 JIM-AMSW&1553-2 ⎮ 

15 JBU-2 ⎮ JMDC-2 

3


17 JSBC-2 (system slot) ⎦ 

18 JIM-HRDL/422-3 ⎤ 

19 JIM-AMSW&1553-3 ⎮ 

20 JBU-3 ⎮ JMDC-3 

21 JIM-CAN-3 ⎜ 

22 JSBC-3 (system slot) ⎦ 

7. Power Distribution: 

Mnemonic Nominal Value Tolerance Notes 

+3.3V_0 +3.3 VDC ±5 % 

+5V_0 +5.0 VDC ±5 % 1 

-5V_0 -5 VDC ±5 % 2 

GND GND 

+3.3V_1 +3.3 VDC ±5 % 

+5V_1 +5.0 VDC ±5 % 1 

-5V_1 -5 VDC ±5 % 2 

GND GND 

+3.3V_2 +3.3 VDC ±5 % 

+5V_2 +5.0 VDC ±5 % 1 

-5V_2 -5 VDC ±5 % 2 

GND GND 

+3.3V_3 +3.3 VDC ±5 % 

+5V_3 +5.0 VDC ±5 % 1 

-5V_3 -5 VDC ±5 % 2 

GND GND 

+5V_A +5.0 VDC ±5 % 3 

-5.2V_A -5.2 VDC ±5 % 3 

AGND Analog GND 7 

+5V_B +5.0 VDC ±5 % 4 

-5.2V_B -5.2 VDC ±5 % 4 

AGND Analog GND 7 

+5V_4 +5.0 VDC ±5 % 5 

GND GND 

+5V_L +5.0 VDC ±5 % 6 

GND GND 

Note: 

(1) Needed for JIM-CAN and JIM-AMSW & 1553. 

May also be used by standard I/O cards for ground test only 

(2) Needed for JIM-HRDL/422 modules 

4

(3) JFOMA part of the JHIF module only 

(4) JFOMB part of the JHIF module only 

(5) J422 part of the JHIF module only 

(6) J1553 part of the JLIF module only 

(7) JFOMA and JFOMB analog ground (AGND) will be bridge 

in moat with GND 

8. External Power Connections: 

The power tap connectors 10pin version (M3) 

It will be included as part of the backplane mechanical specification. 

9. Each of the CompactPCI segments provides +3.3 VDC signal 

environment only. 

All V(I/O) pins of each cPCI slot are connected to the corresponding 

+3.3V power planes. 

10. Bus termination not required according to the PICMGas this design has 

less then 6 slots. 

11. Power decoupling (according to the PICMG 2.0 R3.0) 

12. Characteristic Impedance: 

Zo 65 Ohms ±10% CompactPCI signal traces 

Zhrdl 100 Ohms ±10% HRDL differential pair traces 

Zdiff 110 Ohms ±10% Recommended for all other 

AMS-02 point-to-point differential 

Interconnections (AMSWire,1553), 

but JBP designer should follow the 

specifications of the JIM interfaces 

These values are for PCB only without connectors or boards installed. 

13. CPCI signal consideration: 

SYSEN# grounded at system slot. 

REQ64#, ACK64#, ENUM#, FAL#, DEG#, PRST#, the JSBC Slot board 

shall terminate signals with 2.7KΩ pullupresistor to 3.3V 

Geographical addressing not used 

IDSEL grounded at system slots (MDC’s logical slot 1) 

connected to A31 signal on MDC’s logical slots 2 




REQx#/GNTx# signal connections: 

REQ0#/GNT0# on system slot connected to REQ#/GNT# on slot 2 



5


CLKx signal connections (a single clock line per peripheral slot): 

CLK1 provided the clock to MDC’s logical slots 2 




Clock distribution scheme designed to accommodate up to 1.2ns 

(max) of skew 

INTA# -INTD# connections according the PICMG 2.0 R3.0) 

INTP, INTS, IPMB_SCL, IPMB_SDA, IPMB_PW, HEALTHY#, TCK, 

BRSVP1A5, BRSVP1B5, signals not Used (should be grounded) 

Any other cPCI signals in all slots within the cPCI segments bussed 

with the PICMG 2.0 R3.0 Specification. 

V(I/O) will be connected to 3.3V 

14. Some special signals for AMS application 

JBP_PWR_ON_RST# (AMS-02 specific) signal used for indicating 

of the POWER_ON_DETECT condition to the JMDC modules. 

JBP_PRST# (AMS-02 specific) signal used by any JIM module for 

resetting a corresponding JSBC upon receiving the BOOT command. 

MDCID[1..0] (AMS-02 specific) signals are to identify a JMDC in a 

DAQ System. 

Physical JMDC address is encoded on the backplane (P4) by 

grounding and pulling up different combinations of pins: 

MDC ID[1] MDC ID[0] 

JMDC-0 GND GND 

JMDC-1 GND +3.3V 

JMDC-2 +3.3V GND 

JMDC-3 +3.3V +3.3V 

15. Dallas temp. sensor busses, signals TEMP0_GND,TEMP0_DQ, ... 

TEMP1_VDD, will be connected via flying wires to connector to be 

mounted 

16. Chasis GND connection between boards and JBP is via P4(CHGND). 

6

I. CompactPCI Backplane I/O Connector Pin Assignments 

1. P1 and P2 comply with CompactPCI Specification PICMG 2.0, Ver.3.0 

1.1 P1 for JSBC System Slot Connector Pin Assignments: 

Pin Z A B C D E F 

25 GND 5V REQ64# ENUM# 3.3V 5V GND 

24 GND AD[1] 5V 3.3V AD[0] ACK64# GND 

23 GND 3.3V AD[4] AD[3] 5V AD[2] GND 

22 GND AD[7] GND 3.3V AD[6] AD[5] GND 

21 GND 3.3V AD[9] AD[8] M66EN C/BE[0]# GND 


19 GND 3.3V AD[15] AD[14] GND AD[13] GND 

P1 18 GND SERR# GND 3.3V PAR C/BE[1]# GND 

C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

3.3V 

DEVSEL# 

3.3V 

GND 

GND 

FRAME# 

GND 

3.3V 

IRDY# 

GND PERR# GND 

STOP# LOCK# GND 

GND TRDY# GND 

N 12-14 GND KEY AREA GND 

E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

AD[18] 

AD[21] 

C/BE[3]# 

AD[17] 

GND 

GND 

AD[16] 

3.3V 

AD[23] 

GND C/BE[2]# GND 

AD[20] AD[19] GND 

GND AD[22] GND 

R 8 GND AD[26] GND 3.3V AD[25] AD[24] GND 

7 GND AD[30] AD[29] AD[28] GND AD[27] GND 

6 GND REQ0# GND 3.3V CLK0 AD[31] GND 

5 GND GND GND RST# GND GNT0# GND 

4 GND GND GND 3.3V GND GND GND 

3 GND INTA# INTB# INTC# 5V INTD# GND 

2 GND GND 5V GND GND GND GND 

1 GND 5V -12V GND +12V 5V GND 


7

1.2 P2 for JSBC System Slot Connector Pin Assignments: 


22 GND GND GND GND GND GND GND 

P2 

C 

O 

N 

N 

E 

C 

T 

O 

R 





17 GND GND GND PRST# GND GND GND 

16 GND GND GND DEG# GND GND GND 

15 GND GND GND FAL# REQ5# GNT5# GND 












3 GND CLK4 GND GNT3# REQ4# GNT4# GND 

2 GND CLK2 CLK3 SYSEN# GNT2# REQ3# GND 

1 GND CLK1 GND REQ1# GNT1# REQ2# GND 


8

1.3 P1 for JIM-CAN Peripheral Slot Connector Pin Assignments: 


25 GND 5V REQ64# GND 3.3V 5V GND 




21 GND 3.3V AD[9] AD[8] GND C/BE[0]# GND 




C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

3.3V 

DEVSEL# 

3.3V 

GND 

GND 

FRAME# 

GND 

3.3V 

IRDY# 

GND PERR# GND 


GND TRDY# GND 


E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

AD[18] 

AD[21] 

C/BE[3]# 

AD[17] 

GND 

AD[31] 

AD[16] 

3.3V 

AD[23] 


AD[20] AD[19] GND 







3 GND INTD# INTA# INTB# 5V INTC# GND 




9

1.4 P1 for JBU Peripheral Slot Connector Pin Assignments: 










C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

3.3V 

DEVSEL# 

3.3V 

GND 

GND 

FRAME# 

GND 

3.3V 

IRDY# 

GND PERR# GND 


GND TRDY# GND 


E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

AD[18] 

AD[21] 

C/BE[3]# 

AD[17] 

GND 

AD[30] 

AD[16] 

3.3V 

AD[23] 


AD[20] AD[19] GND 







3 GND INTC# INTD# INTA# 5V INTB# GND 




10

1.5 P1 for JIM-AMSW&1553 Peripheral Slot Connector Pin Assignments: 










C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

3.3V 

DEVSEL# 

3.3V 

GND 

GND 

FRAME# 

GND 

3.3V 

IRDY# 

GND PERR# GND 


GND TRDY# GND 


E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

AD[18] 

AD[21] 

C/BE[3]# 

AD[17] 

GND 

AD[29] 

AD[16] 

3.3V 

AD[23] 


AD[20] AD[19] GND 







3 GND INTB# INTC# INTD# 5V INTA# GND 




11

1.6 P1 for JIM-HRDL/422 Peripheral Slot Connector Pin Assignments: 










C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

3.3V 

DEVSEL# 

3.3V 

GND 

GND 

FRAME# 

GND 

3.3V 

IRDY# 

GND PERR# GND 


GND TRDY# GND 


E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

AD[18] 

AD[21] 

C/BE[3]# 

AD[17] 

GND 

AD[28] 

AD[16] 

3.3V 

AD[23] 


AD[20] AD[19] GND 







3 GND INTA# INTB# INTC# 5V INTD# GND 




1.7 PCI Interrupt Binding: 

12

1.8 System to peripheral slot signal assignment: 

Signal Connector: Pin Signal Connector: Pin 

System Slot(△),Logical Slot 1 Peripheral Slot(○), Logical Slot 2 

CLK1 P2:A1 CLK P1:D6 

AD31 P1:E6 IDSEL P1:B9 

REQ0# P1:A6 REQ# P1:A6 

GNT0# P1:E5 GNT# P1:E5 



AD30 P1:A7 IDSEL P1:B9 

REQ1# P2:C1 REQ# P1:A6 

GNT1# P2:D1 GNT# P1:E5 


CLK3 P2:B2 CLK P1:D6 

AD29 P1:B7 IDSEL P1:B9 

REQ2# P2:E1 REQ# P1:A6 

GNT2# P2:D2 GNT# P1:E5 



AD28 P1:C7 IDSEL P1:B9 

REQ3# P2:E2 REQ# P1:A6 

GNT3# P2:C3 GNT# P1:E5 

13

2 P3 and P4 Pin Assignments: 

2.1 P3 is not used 

2.2 P4 for JSBC Connector Pin Assignments: 









P4 18 GND GND GND GND GND GND GND 

C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND GND GND GND 



N 12-14 KEY AREA 

E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 




R 8 GND CHGND GND GND GND GND GND 

7 GND CHGND GND GND GND GND GND 

6 GND GND TEMP1_VDD GND GND GND GND 

5 GND GND TEMP1_DQ GND GND GND GND 

4 GND JBP_PRST TEMP1_GND GND GND GND GND 

3 GND JBP_PWR_ON_RST# TEMP0_VDD GND GND GND GND 

2 GND MDCID[1] TEMP0_DQ GND GND GND GND 

1 GND MDCID[0] TEMP0_GND GND GND GND GND 


Note: Z12, Z13, Z14, F12, F13, F14 are GROUND pins 

14

2.3 P4 for JIM-CAN Connector Pin Assignments: 










C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 





E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 













15

2.4 P4 for JBU Connector Pin Assignments: 










C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 





E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 













16

2.5 P4 for JIM-AMSW&1553 Connector Pin Assignments: 










C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 





E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 













17

P4 

C 

O 

N 

N 

E 

C 

T 

O 

R 

2.6 P4 for JIM-HRDL/422 Connector Pin Assignments: 


25 GND +5V AGND -5V AGND SD12 GND 

24 GND +5V AGND -5V AGND RXLB1+ GND 

23 GND +5V AGND -5V AGND RXLB1- GND 

22 GND +5V AGND -5V AGND SD11 GND 

21 GND +5V AGND -5V AGND RXLA1+ GND 

20 GND +5V AGND -5V AGND RXLA1- GND 

19 GND +5V AGND -5V AGND AGND GND 

18 GND +5V AGND -5V AGND TXLB1- GND 

17 GND +5V AGND -5V AGND TXLB1+ GND 

16 GND +5V AGND -5V AGND TXLA1- GND 

15 GND MUX12 AGND MUX11 AGND TXLA1+ GND 

12-14 KEY AREA 








4 GND JBP_PRST TEMP1_GND GND TXD1+ TXC1- GND 

3 GND JBP_PWR_ON_RST# TEMP0_VDD GND TXD1- TXC1+ GND 

2 GND MDCID[1] TEMP0_DQ GND RXC1- RXD1+ GND 

1 GND MDCID[0] TEMP0_GND GND RXC1+ RXD1- GND 


Note: AGND and GND will be bridge in moat. 

18

2.7 P4 for JHIF Connector Pin Assignments: 


25 GND +5V_B RXLB1+ RXLB2+ RXLB3+ RXLB4+ GND 

24 GND +5V_B RXLB1- RXLB2- RXLB3- RXLB4- GND 

P4 

C 

O 

N 

N 

E 

C 

T 

O 

R 

23 GND AGND RXLA1+ RXLA2+ RXLA3+ RXLA4+ GND 

22 GND -5.2V_B RXLA1- RXLA2- RXLA3- RXLA4- GND 

21 GND -5.2V_B TXLB1- TXLB2- TXLB3- TXLB4- GND 

20 GND AGND TXLB1+ TXLB2+ TXLB3+ TXLB4+ GND 

19 GND +5V_A TXLA1- TXLA2- TXLA3- TXLA4- GND 

18 GND +5V_A TXLA1+ TXLA2+ TXLA3+ TXLA4+ GND 

17 GND AGND AGND AGND AGND AGND GND 

16 GND -5.2V_A MUX12 MUX22 MUX32 MUX42 GND 

15 GND -5.2V_A MUX11 MUX21 MUX31 MUX41 GND 

12-14 KEY AREA 

11 GND GND SD12 SD22 SD32 SD42 GND 

10 GND +5V_4 SD11 SD21 SD31 SD41 GND 

9 GND +5V_4 GND GND GND GND GND 

8 GND CHGND TXC1- TXC2- TXC3- TXC4- GND 

7 GND CHGND TXC1+ TXC2+ TXC3+ TXC4+ GND 

6 GND TEMP1_VDD TXD1+ TXD2+ TXD3+ TXD4+ GND 

5 GND TEMP1_DQ TXD1- TXD2- TXD3- TXD4- GND 

4 GND TEMP1_GND RXD1+ RXD2+ RXD3+ RXD4+ GND 

3 GND TEMP0_VDD RXD1- RXD2- RXD3- RXD4- GND 

2 GND TEMP0_DQ RXC1- RXC2- RXC3- RXC4- GND 

1 GND TEMP0_GND RXC1+ RXC2+ RXC3+ RXC4+ GND 


Note: AGND and GND will be bridge in moat. 

19

2.8 P4 for JLIF Connector Pin Assignments: 










C 

O 

N 

17 

16 

15 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 





E 

C 

T 

O 

11 

10 

9 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 

GND 








4 GND GND TEMP1_GND GND GND GND GND 



1 GND GND TEMP0_GND GND GND GND GND 


20

3 P5 Connector Pin Assignments 

3.1 P5 for JIM-AMSW&1553 Connector Pin Assignments: 



P5 

C 

O 

N 

N 

E 

C 

T 

O 

R 


20 GND L7-Sin+ L7- Din+ bRTAP L5-Dout+ L5-Sout+ GND 

19 GND L7-Sin- L7- Din- bRTA4 L5-Dout- L5-Sout- GND 

18 GND GND GND bRTA3 GND GND GND 

17 GND L6-Sin+ L6- Din+ bRTA2 L4-Dout+ L4-Sout+ GND 

16 GND L6-Sin- L6- Din- bRTA1 L4-Dout- L4-Sout- GND 


14 GND L9-Sin+ L9- Din+ GND L9-Dout+ L9-Sout+ GND 

13 GND L9-Sin- L9- Din- bRXA L9-Dout- L9-Sout- GND 

12 GND GND GND bRXA* GND GND GND 

11 GND L8-Sin+ L8- Din+ bTXA L8-Dout+ L8-Sout+ GND 

10 GND L8-Sin- L8- Din- bTXA* L8-Dout- L8-Sout- GND 

9 GND GND GND bTX_INH_A GND GND GND 

8 GND L5-Sin+ L5- Din+ bTXB L7-Dout+ L7-Sout+ GND 

7 GND L5-Sin- L5- Din- bTXB* L7-Dout- L7-Sout- GND 

6 GND GND GND bTX_INH_B GND GND GND 

5 GND L4-Sin+ L4- Din+ bRXB* L6-Dout+ L6-Sout+ GND 

4 GND L4-Sin- L4- Din- bRXB L6-Dout- L6-Sout- GND 





Note: All unused pins should be grounded 

21

P5 

C 

O 

N 

N 

E 

C 

T 

O 

R 

3.2 P5 for JLIF Connector Pin Assignments: 




20 GND GND GND bRTAP GND GND GND 







13 GND b0RXA b1RXA GND b2RXA b3RXA GND 

12 GND b0RXA* b1RXA* GND b2RXA* b3RXA* GND 

11 GND b0TXA b1TXA GND b2TXA b3TXA GND 

10 GND b0TXA* b1TXA* GND b2TXA* b3TXA* GND 

9 GND b0TX_INH_A b1TX_INH_A GND b2TX_INH_A b3TX_INH_A GND 

8 GND b0TXB b1TXB GND b2TXB b3TXB GND 

7 GND b0TXB* b1TXB* GND b2TXB* b3TXB* GND 

6 GND b0TX_INH_B b1TX_INH_B GND b2TX_INH_B b3TX_INH_B GND 

5 GND b0RXB* b1RXB* GND b2RXB* b3RXB* GND 

4 GND b0RXB b1RXB GND b2RXB b3RXB GND 



1 GND +5V_L +5V_L GND +5V_L +5V_L GND 


22

4 Power Connector Pin Assignments: 

4.1 Power Tap Connector Pin Assignments: 

JMDC0 JMDC1 JMDC2 JMDC3 

Power Tap Signal Signal Signal Signal 

1 +3.3V_0 +3.3V_1 +3.3V_2 +3.3V_3 

2 GND GND GND GND 

3 +5V_0 +5V_1 +5V_2 +5V_3 


5 -5V_0 -5V_1 -5V_2 -5V_3 


7 CHGND CHGND CHGND CHGND 

8 +12V 

9 -12V 

+12V & -12V for flight will be ground with a 0 ohm resistor 

4.2 JHIF&JLIF Power Tap Connector Pin Assignments: 

JFOMA JFOMB J422 JLIFY(Z) 

Power Tap Signal Signal Signal Signal 

1 +5V_A +5V _B +5V _4 +5V _L 

2 AGND AGND GND GND 

3 -5.2V_A -5.2V _B 

4 AGND AGND 

4.3 Dallas sensor bus Pin Assignment: 

Pin1 Pin2 Pin3 Pin4 Pin5 

Signal TEMP0_GND TEMP0_DQ TEMP0_VDD TEMP1_GND TEMP1_DQ 

Pin6 Pin7 Pin8 Pin9 

Signal TEMP1_VDD GND GND GND 

5 Power Decoupling 

Mnemonic Part Number Decoupling Capacitance Voltage 

5V 

CWR11HH226KC 

1206B104K101YHT 

22μF ± 10% 

0.1μF ± 10% 

15V 

50V 

3.3V 

CWR11HH226KC 

1206B104K101YHT 

22μF ± 10% 

0.1μF ± 10% 

15V 

50V 

-5V(-5.2V) 

CWR11HH226KC 

1206B104K101YHT 

22μF ± 10% 

0.1μF ± 10% 

15V 

50V 

23

II. CompactPCI Backplane Layer Assignment: 

1. Layer 1 Component Side (Top) : Signal 

2. Layer 2 : GND Plane (Neg) with split area for +3.3V (MDCs) 

3. Layer 3 : MID1 Signal 

4. Layer 4 : GND Plane (Neg) with split area for +5V (MDCs, JFOM) 

5. Layer 5 : MID2 Signal+ Chassis GND Plane 

6. Layer 6 : GND Plane (Neg) with split area for –5V (MDCs) and –5.2V 

(JFOM) 

7. Layer 7 : GND Plane (Neg) 

8. Layer 8 : MID3 Signal and +5V (JLIF) 

9. Layer 9 : GND+ AGND Plane (Neg) with split area for +5V (J422) 

10. Layer 10: MID4 Signal 

11. Layer 11: CLK+ GND Plane (Neg) 

12. Layer 12: Solder Side (Bottom) : Signal 

AMSWire links routed on TOP, MID1, MID4, BOTTOM. 

HRDL links routed on TOP, BOTTOM. 

RS422 links routed on TOP, BOTTOM. 

1553 links routed on MID2, MID3. 

PCI bus segment links and other link routed on MID1, MID2, MID3, MID4. 

AGND and GND will be bridge in moat on Layer 9. 

24

Layer to Layer spacing: 

12-JBP DIAGRAM Lamination Simulation (mil) Result (mil) 

L1 Copper Thickness S 1OZ 1.4 TOP 

L1-2 Dielectric Thickness 6.6 

L2 Copper Thickness P 1OZ 1.4 Negative 

L2-L3 Dielectric Thickness 0.014" 14 

L3 Copper Thickness S 1OZ 1.4 MID1 

L3-4 Dielectric Thickness 15 


L4-5 Dielectric Thickness 0.005" 5 










L9-L10 Dielectric Thickness 15 


L10-L11 Dielectric Thickness 0.014" 14 



L12 Copper Thickness S 1OZ 1.4 BOM 

Differential Impedance Simulation: 

L1-2 (L11-12) L3-4 (L9-10) 

TOP and BOTTOM MID1, MID4 

Trace (mil) 5 4 4 

Space (mil) 6 7 8 

Differential Impedance Simulation (ohms) 99.96 110.87 109.9 

25

III. Revision History 

06/19/2001 R01 Initial version 

08/19/2001 R02 Update to the specification for the prototype 

03/29/2001 R03 Add power tap connector 10pin version (M3) 

Add P4 Dallas sensor bus to USCM 

Update P4 JIM-HRDL/422 pin assignment 

Change 24-slot hybrid monolithic backplane 

04/03/2002 R04 Change P4& P5 connector pin assignment 

04/22/2002 R04a 

Update P5 JIM-HRDL/422 pin assignment 

Update to the specification for the flight 

04/23/2002 R04b Update to the specification for the flight 

Restore P4& P5 connector pin assignment 

04/30/2002 R04c Update P5 JIM-AMSW&1553 pin assignment 

05/16/2002 R04d Add P4 chassis GND pin assignment 

P1 and P2 all unused pins should be grounded 

06/06/2002 R05 

Dallas temperature bus to reserve 9 holes in JBP 

“JBP_COLD_START” is renamed to 

“JBP_PWR_ON_RST#” 

“TCK, IPMB PWR, BRSVP1A5, HEALTHY#, 

BRSVP1B5, IPMB SCL, IPMB SDA, INTP, 

INTS, PRST#, DEG#, FAL#, ENUM#”, 

should be grounded 

Restore JSBC P1& P2 CLK signals 

10/22/2002 R05a “REQ64#, ACK64#, ENUM#, FAL#, DEG#, 

PRST#”, the JSBC Slot board shall terminate 

signals with 2.7KΩ pullupresistor to 3.3V 

“SYSEN#” the JSBC Slot board should be 

grounded 

03/04/2003 R05b “JBP_PWR_ON_RST#”, “JBP_PRST” separate 

for different JMDCs 

“REQ64#, ACK64#, ENUM#, FAL#, DEG#, PRST#, 

BD_SEL#, M66EN, SYSEN#, REQ5#, GNT5#”, for 

FM version no connect 

Modify CLKx signal 

Put 2 more power taps on JBP for JFOM 

26

APPENDIX 

1. CompactPCI Specification PICMG 2.0 R3.0 

2. “AMS Electronic Meeting International 2001” (11/12-11/16) 

3. 0328-13 My view on the JBP design.eml by Andrei Rozhkov’s 

4. 0417-4 My comments to JBP document by A. Rozhkov’s Notes to AMS-02 

BACKPLANE Prototype BOARD 

5. “AMS-J-CRATE-R06d” by P. Dennett 

6. “Flight Design Summary” and “0423 Meeting at CERN on JPD, JTPD, 

JT-Crate, JBP (fwd)” by M. Capell 

7. “0430-2 JBP-P5.pdf” by Lin CH 

8. “meeting-0905.txt” by M. Capel Meeting at CERN 

9. “AMS-02 The 55 th working meeting”(June 4 2002) 

10. “AMS Electronic Meeting International 2002” (July 4 2002) 

11. “AMS Electronic Meeting International 2003” (02/19-02/21) 

27

Bill of Material for JBP 

Used Part Type Designator Footprint 

==== ======== ==================== ========== 

50 .1UF CP4A13-CP4A15 C1206 

CP5A15 CP101-CP120 

CP201-CP220 CP301-CP304 

2 0 R32 R33 R0805 

15 10K R17-R31 R0805 

16 22 R1-R16 R0805 

50 22uF CU4A13- CU4E13 C7343 

CU5A15 CU101-CU120 

CU201-CU220 CU301- CU304 

44 CON154A S1P1- S22P1 CON154A 

S1P4-S22P4 

9 CON154B S1P2 S4P5 S6P2 S9P5 CON154B 

S12P5 S14P5 S17P2 

S19P5 S22P2 

42 POWERTAP PT1-PT42 POWERTAP 

28

AMS-02 DAQ SYSTEM JBP Backplane Board HARDWARE ... - Cern

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