UDR2 - Cern
UDR2 - Cern
UDR2 - Cern
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TRD U-Crate Crate electronics<br />
Status and test procedures for the TRD<br />
Readout Electronics<br />
Wim de Boer, Chan Hoon Chung*, Florian Hauler,<br />
Levin Jungermann, Mike Schmanau, Georg Schwering*<br />
IEKP - Universität Karlsruhe (TH)<br />
*RWTH-Aachen I
Outline<br />
1. QM2 production status of boards:<br />
<strong>UDR2</strong>, UPSFEv2, UBPv2, S9011AUv2, S9011B<br />
2. Preparation for thermo-vacuum-test in spring 2005<br />
TRD front end simulator prototype<br />
3. QM2 UPSFE test preparation<br />
4. Cosmics test stand in Karlsruhe<br />
5. Summary<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 2
TRD(U)-Electronics<br />
TRD(U) Electronics Overview<br />
after weight reduction<br />
Ucrate = TRD electronic crate<br />
UBP = TRD backplane<br />
UPD = TRD power distribution box<br />
UPSFE = TRD power supply for front end<br />
UDR = TRD data reduction board<br />
JINF = data concentrator and link to higher DAQ for TRD<br />
UHVG = TRD high voltage generator<br />
UFE = TRD front end<br />
UTE = TRD tube end<br />
UHVD = TRD high voltage distributor<br />
V2<br />
V2<br />
removed USCM<br />
USCM functionality covered partly by JINFV2<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 3
U-crate crate QM1/QM2 hardware<br />
UHVG USCM<br />
UFE JINF <strong>UDR2</strong>/UPSFE<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 4
Status of <strong>UDR2</strong>/UPSFEv2/UBPv2<br />
<strong>UDR2</strong>/UPSFEv2/UBPv2<br />
• <strong>UDR2</strong> (Data reduction board)<br />
• QM2 production at CSIST in Taiwan<br />
completed.<br />
• UPSFEv2 (Power Supply for Frontends)<br />
• 2 QM2 UPSFEs delivered<br />
• Lecroy communication with new LVDS-chips<br />
tested at CERN with Vladimir Koutsenko.<br />
• Go ahead for the PCA of remaining modules<br />
was given September, 21st.<br />
• Production scheduled to be finished October<br />
18th.<br />
• Mike Schmanau/Levin Jungermann will go to<br />
CSIST for tests on 8th of November.<br />
• UBPv2 (backplane)<br />
• QM2 UBPv2 production finished. Slow control<br />
functionality tested successfully with<br />
UPSFEv2, UHVG and JINFv2.<br />
QM2 <strong>UDR2</strong><br />
1. Powergroup 2. Powergroup<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 5<br />
<strong>UDR2</strong><br />
UPSFE<br />
<strong>UDR2</strong><br />
<strong>UDR2</strong><br />
UPSFE<br />
<strong>UDR2</strong><br />
3. Powergroup<br />
<strong>UDR2</strong><br />
UPSFE<br />
<strong>UDR2</strong><br />
JINF<br />
UHVG<br />
UHVG<br />
F. Hauler, IEKP 18.01.2004<br />
UHVG<br />
UHVG<br />
UHVG<br />
UHVG
Status of UPD boards S9011AUv2 and S9011B<br />
• S9011AUv2 for control of DC/DC converters in<br />
UPD-Box<br />
• S9011AUv2 QM2 production finished at CSIST.<br />
2 boards already tested in Europe.<br />
• Last board will be tested at CSIST in the week<br />
8th November.<br />
• S9011B Filter<br />
• S9011B QM2 production finished at CSIST.<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 6
TRD front end simulator (UFS)<br />
for TVT at NSPO<br />
During TVT, not enough real front ends will be available.<br />
A device is needed to simulate the load to the USPFEboards<br />
and to answer the signals of the <strong>UDR2</strong>-boards to<br />
recognize any faults.<br />
<strong>UDR2</strong><br />
Load resistors<br />
UPSFE<br />
DAC<br />
FPGA/DSP<br />
Power for front ends<br />
DAC level<br />
control signals<br />
Clock ADC<br />
digitzed DAC level<br />
Heat Interface<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 7<br />
ADC<br />
LVDS<br />
Load<br />
resistors<br />
UFS
Monitor lines<br />
LeCroy<br />
Dallas<br />
Temp.<br />
sensor bus<br />
UPSFEv2<br />
slot<br />
power<br />
connections<br />
QM2 UPSFE tests: tests<br />
UPSFE Test-Workbench<br />
Test Workbench<br />
geom. address<br />
status LEDs<br />
for<br />
UHVG,<strong>UDR2</strong><br />
ON/OFF<br />
variable load<br />
(28x)<br />
USB interface<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 8
QM2 UPSFE tests: tests:<br />
Linear regulator test circuit principle<br />
Personal Computer with Labview Software<br />
I/O-Warrior<br />
USB Interface Microcontroller<br />
DS1803<br />
Digital Potentiometer<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 9<br />
MAX 890L<br />
MOSFET<br />
I<br />
RLoad<br />
UPSFE<br />
linear regulator
-2.0V<br />
Max 890L<br />
MOSFET<br />
Load resistor<br />
QM2 UPSFE tests: tests<br />
Variable load<br />
Status LED<br />
Optocoupler<br />
UPSFEv2 feed back<br />
+2.0V<br />
to PC (via MC)<br />
control lines<br />
from PC (via MC)<br />
DS 1803 Digital<br />
Potentiometer<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 10
QM2 UPSFE tests: tests<br />
Control software<br />
• Labview Software for UPSFE tests<br />
• automatic testing of<br />
14 UPSFE channels<br />
• ramping load<br />
• reading linear regulator<br />
feed back and storing<br />
switch-off currents.<br />
• monitoring of UPSFE<br />
supply currents<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 11
QM2 UPSFE tests: tests<br />
Test of slow control communication<br />
Test of Lecroy communication<br />
to S9011AUv2 and UPSFEv2<br />
using Alexei Lebedev‘s Lebedev<br />
control software. software<br />
(Many Many thanks to Alexei!!)<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 12
Cosmics at Karlsruhe<br />
New cosmics test stand at Karlsruhe for long term data taking.<br />
PM HV<br />
Trigger<br />
electronics<br />
Power supply<br />
Trigger A<br />
Trigger B<br />
64 channel strawtube jig<br />
U-Crate<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 13
Summary<br />
• <strong>UDR2</strong> QM2 production finished. Boards successfully tested. 10/10 boards<br />
working.<br />
• UPSFEv2 QM2 production completed. Preparation for last QM2 tests<br />
S9011AUv2 and UPSFEv2 completed.<br />
• Cosmics test stand for long term electronics tests available soon.<br />
• Front end simulator UFS for space qualification tests at NSPO developed.<br />
• All QM2 boards for TRD will be tested and available on November 19th.<br />
• OK for flight module production will be given, as soon as space<br />
qualification tests have been completed. (TVT, vibration, …)<br />
October 18th-23th, 2004 TIM, JSC Florian Hauler/Levin Jungermann, IEKP 14
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