FAS366U Fast Architecture SCSI Processor

QLogic Corporation 

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Features 

� Compliance with ANSI draft Fast–20 standard 

� Compliance with ANSI X3T10/855D SCSI–3 

parallel interface (SPI) standard 

� Compliance with ANSI SCSI configured 

automatically (SCAM) protocol levels 1 and 2 

� Sustained SCSI data transfer rates of up to: 

� 40 Mbytes/sec synchronous (ultra and wide 

SCSI) 

� 14 Mbytes/sec asynchronous (wide SCSI) 

� Synchronous DMA timing; DMA speed of 

50 Mbytes/sec 

� REQ and ACK programmable assertion and 

deassertion control 

DB BUS 

PAD BUS 

COMMAND 

RECOMMAND 

COUNTER 

TRANSFER 

COUNT 

SEL/RESEL 

BUS ID 

SEL/RESEL 

TIMEOUT 

SYNC PERIOD 

SYNC OFFSET/ 

SYNC ASSERT/ 

SYNC DEASSERT 

CLOCK 

CONVERSION 

CONFIGURATION 

TEST (SCAM) 

FIFO 

�� 

SEQUENCERS 

Figure 1. FAS366U Block Diagram 

� Support for hot plugging 

� Target and initiator block transfer sequences 

� Bus idle timer 

� Split–bus architecture 

� Pipelined command structure 

� On–chip, single–ended SCSI transceivers 

(48–mA drivers) 

� Initiator and target roles 

� Active negation 

� 16–bit recommand counter 

� Differential mode 

� SCSI bus reset watchdog timer 

BLOCK 

REGISTERS 

TRANSFER 

COUNTER 

INTERRUPT 

SEQUENCE 

STEP 

SCSI 

DATA 

PARITY (2) 

DATA (16) 


CONTROL 

53366–580–01 B FAS366U 1 

STATUS


Product Description 

The FAS366U is a new addition to the QLogic fast 

architecture SCSI processor (FAS) chip family. The 

FAS366U supports advanced SCSI–3 options including 

ultra SCSI synchronous transfers. Also included is the 

advanced SCAM level 2 SCSI controller core. 

The FAS366U is a single–chip controller for use in 

host and peripheral applications. It is firmware and 

pin–out compatible with the QLogic FAS366 chip. The 

FAS366U block diagram is shown in figure 1. 

The FAS366U implements QLogic’s new SCSI 

target and initiator block transfer sequences. The block 

sequences reduce firmware overhead and are composed 

of the following new commands: Target Block 

Sequence (including the bus idle timer), Initiator Block 

Sequence, Load/Unload Block Registers sequences, 

Abort Block Sequence, and Disconnect Abort Block 

Sequence. 

The FAS366U supports both single–ended and 

differential mode SCSI operations and operates in 

initiator and target roles. The FAS366U has been 

optimized for interaction with a DMA controller and 

the controlling microprocessor. 

The versatile split–bus architecture supports various 

microprocessor and DMA bus configurations. A 

separate 8–bit microprocessor bus (PAD) provides 

access to all internal registers, and a 16–bit DMA bus 

(DB) provides a path for DMA transfers through the 

FIFO. Each bus is protected by a parity bit (byte–wide 

parity) to improve data integrity. During data transfer, 

the microprocessor has instant access to status and has 

the ability to execute commands. 

SCAM Implementation 

The FAS366U supports levels 1 and 2 of the SCAM 

protocol. Refer to the latest revision of X3T10/855D, 

Annex B. The SCAM protocol requires direct access 

and control over the SCSI data bus and several of the 

SCSI phase and control signals. The majority of the 

SCAM protocol can be implemented in firmware at 

microprocessor speeds. The following SCAM features 

are supported in the hardware: 

� Arbitration without an ID 

� Slow response to selection with an unconfirmed ID 

� Detection of and response to SCAM selection 

Fast DMA Protocol 

The fast DMA protocol is required for supporting 

the full bandwidth of ultra, wide SCSI. 

The DREQ signal initiates DMA transfers and runs 

asynchronous to the user’s clock. For read operations, 

DACK acts as a chip select to enable the FAS366U 

drivers onto the DMA bus. The chip select role of 

DACK helps support the burst timing of fast DMA 

mode. DACK selects the FAS366U after DREQ is 

asserted and is removed either after DREQ is deasserted 

or when the DMA transfer is paused. 

DBRD requests data from the FAS366U and DBWR 

validates data sent to the FAS366U. Data is valid 

around the rising (trailing) edge of DBRD or DBWR. 

DMA transfers are terminated by deasserting 

DREQ. Deassertion of DREQ is triggered by the 

leading edge of DBRD or DBWR (see timing 

parameter t1 in figures 2 and 3) under any of the 

following conditions: 

� To prevent FIFO overrun conditions 

� To prevent FIFO underrun conditions 

� When the required amount of data has been 

transferred 

When DREQ is deasserted, the FAS366U ignores 

DBRD and DBWR. Data transfers do not take place 

unless DREQ is asserted. 

The FAS366U does not generate parity on the 

incoming DMA bus. Correct parity must always be 

supplied with the data. 

The DMA interface signals are given in table 1. 

DMA timing is given in table 2 and figures 2 and 3. 

Table 1. DMA Interface Signals 

Active 

Level 

Description 

DREQ ÁÁÁ 

O ÁÁÁÁÁ 

High The FAS366U DMA 

request line begins and 

ends DMA cycles. 

ÁÁÁÁÁÁÁÁ 

I Low DACKÁÁÁ 

The acknowledge is ÁÁÁÁÁ 

used 

as a chip select to activate 

FAS366U drivers and to 

acknowledge acceptance of 

DREQ. 

ÁÁÁ ÁÁÁÁÁÁÁÁ 

ÁÁÁÁÁ 


DBRDÁÁÁ ÁÁÁÁÁ 

ÁÁÁ I 

ÁÁÁ 

ÁÁÁ 

ÁÁÁÁÁ 

Rising edge 

ÁÁÁÁÁ 

ÁÁÁÁÁ 


The trailing edge accepts 

data ÁÁÁÁÁÁÁÁ 

from the FAS366U for 

DMA read ÁÁÁÁÁÁÁÁ 

operations. 

DBWR ÁÁÁ 

I 

ÁÁÁ 

ÁÁÁ 

ÁÁÁÁÁ 

Rising 

ÁÁÁÁÁ 

edge 

ÁÁÁÁÁ 


The trailing edge strobes 


data into the FAS366U 

FIFO on DMA write 


operations. 

DB15–0 ÁÁÁ 

N/A This is the DMA data bus. 

ÁÁÁ 

ÁÁÁ 

PinÁÁÁ 

ÁÁÁ 

TypeÁÁÁÁÁ 

ÁÁÁÁÁ 



ÁÁÁ ÁÁÁÁÁ 


ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 

ÁÁÁ ÁÁÁ 

ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 

ÁÁÁ 



ÁÁÁ 

ÁÁÁ 

ÁÁÁ 

ÁÁÁ 

ÁÁÁ 

ÁÁÁ 

ÁÁÁ 

ÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 

ÁÁÁ 

ÁÁÁ ÁÁÁ 

I/OÁÁÁÁÁ 

ÁÁÁÁÁ 



2 FAS366U 53366–580–01 B

Table 2. DMA Timing 

ÁÁÁÁÁÁÁÁÁÁÁ 

Symbol Description 

(ns)ÁÁÁÁÁÁ 

Minimum Maximum ÁÁÁ 

(ns) Note 

t1 

DBRD/DBWR low to DREQ low 

ÁÁÁÁ 

ÁÁÁÁÁ 

ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ 

ÁÁÁÁ 

ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ 


ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ 

ÁÁÁÁÁÁ ÁÁÁ 

ÁÁÁÁ 

ÁÁÁÁÁÁ 

t2 

ÁÁÁ 

ÁÁÁÁ 


DACK high to DREQ ÁÁÁÁÁ 

high 

TBD 


ÁÁÁÁÁÁ 


ÁÁÁ 

t3 ÁÁÁÁ 

ÁÁÁÁ 


DACK high to DACK ÁÁÁÁÁ 

low 

40 


ÁÁÁÁÁÁ 


ÁÁÁÁÁ ÁÁÁ 

ÁÁÁÁ 


tR1 ÁÁÁÁÁÁÁÁÁÁÁ 

DACK low to DBRD low 


DBRD assertion pulse width 


DBRD deassertion pulse width 

ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ 

ÁÁÁÁ 

ÁÁÁÁÁ 

ÁÁÁÁÁ 

ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ 


ÁÁÁÁ 

ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ 



DBRD high to DACK high 


DBRD low to DBRD low cycle 

ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ 

ÁÁÁÁ 

ÁÁÁÁÁ 

ÁÁÁ 

ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ 

ÁÁÁÁÁÁ 


ÁÁÁÁ 

ÁÁÁ 


ÁÁÁÁ 

ÁÁÁÁÁ 

ÁÁÁÁÁ 

ÁÁÁÁÁÁ 


ÁÁÁÁ 

ÁÁÁ 

tR6 

ÁÁÁÁ 


DACK low to DB15–0 

ÁÁÁÁÁ 

read 


on 

2 

ÁÁÁÁÁÁ 


ÁÁÁ 

c 

ÁÁÁÁ 

tR7 

ÁÁÁÁ 


DACK high to DB15–0 


read off 

ÁÁÁÁÁ 

ÁÁÁÁÁ ÁÁÁÁÁÁ 

15 

ÁÁÁÁÁÁ 

ÁÁÁ 

ÁÁÁ 

c 

ÁÁÁÁ 

tR8 

ÁÁÁÁ 


DBRD low to DB15–0 


read valid 

ÁÁÁÁÁ 


15 

ÁÁÁÁÁÁ 

ÁÁÁ 

ÁÁÁ 

c 

ÁÁÁÁ 



tR9 DBRD low to DB15–0 read 

ÁÁÁÁÁ 

invalid 

ÁÁÁÁÁÁ ÁÁÁÁ 

0 


ÁÁÁ 

ÁÁÁ c 


ÁÁÁÁÁ 


ÁÁÁÁ 

tW1 

tW2 

tW3 

DACK low to DBWR low 

DBWR assertion pulse width 

DBWR deassertion pulse width 

ÁÁÁÁ 




ÁÁÁ 


ÁÁÁÁ 

ÁÁÁ 

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 

ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ 

ÁÁÁÁÁÁ 

ÁÁÁÁÁ 


ÁÁÁÁ 


tW4 DBWR high to DACK ÁÁÁÁÁ 

high ÁÁÁÁÁÁ 

tW3 d 


tW5 DBWR low to DBWR low ÁÁÁÁÁ 

cycle ÁÁÁÁÁÁ 

40 

ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ 

ÁÁÁÁ 

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 

ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ 

ÁÁÁ 


ÁÁÁÁ 


ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ 

ÁÁÁ 

ÁÁÁÁ 

ÁÁÁ 


ÁÁÁ 

tW6 ÁÁÁÁÁÁÁÁÁÁÁ 

DB15–0 ÁÁÁÁ write setup to DBWR high ÁÁÁÁÁ 

10 ÁÁÁÁÁÁ ÁÁÁ 


ÁÁÁ 

ÁÁÁÁ 

ÁÁÁ 


ÁÁÁ 

ÁÁÁ 


tW7 DB15–0 write hold from DBWR ÁÁÁÁÁ 

high ÁÁÁÁÁÁ 

5 

Table Notes 

aDREQ loading is 30 pf. 

bDBRD low to DACK high�tR5 

cData loading is 50 pf. 

dDBWR low to DACK high�tW5 



tR5 

15 

15 

tR3 

40 

tW5 

15 

15 

12 

a 

b


DREQ 

DACK 

DBRD 

DB15–0 

DREQ 

DACK 

DBWR 

DB15–0 

Figure 2. DMA Read Cycle 

Figure 3. DMA Write Cycle 


Interfaces 


The FAS366U interfaces consist of the microprocessor bus and the SCSI bus. Pins that support these interfaces 

and other chip operations are shown in figure 4. 

MICROPROCESSOR 

INTERFACE 

DMA AND 

MICROPROCESSOR 

INTERFACE 

RESET 

CLOCK 

POWER 

AND GROUND 

A3–0 

CS 

INT 

PAD7–0 

PADP 

PAUSE 

RD 

WR 

DACK 

DB15–0 

DBP1–0 

DBRD 

DBWR 

DREQ 

RESETI 

RESETO 

CLK 

VDD 

VSS 

42–45 

13 

FAS366U 

3 61 

92–97, 99, 100 

91 

10 

14 

15 57 

9 

SEE NOTE 

127, 117 

4 

5 

8 

2 

1 

88 

SEE NOTE 

SEE NOTE 

Figure 4. FAS366U Functional Signal Grouping 


58 

62 

33 

31 

56 

32 

SEE NOTE 

75, 63 

55 

11 

47 

39 

20 

38 

SEE NOTE 

86, 48 

36 

19 

41, 40 

SEE NOTE 

NOTE: DB15–0 = 126–122, 120–118, 116, 115, 113–108 

ESD15–0 = 101–104, 21–24, 49–52, 82–85 

NO CONNECT = 16, 37, 53, 60, 67, 90, 105 

SD15–0 = 76, 78–80, 26–28, 30, 64, 65, 68–70, 72–74 

VDD = 7, 12, 17, 35, 87, 106 

VSS = 6, 18, 25, 29, 34, 46, 54, 59, 66, 71, 77, 81, 89, 98, 107, 114, 121, 128 

ACK 

ATN 

BSY 

CD 

IO 

MSG 

REQ 

RST 

SD15–0 

SDP1–0 

SEL 

DIFFM 

DIFFSENS 

EBSY 

EIGS 

ERST 

ESD15–0 

ESDP1–0 

ESEL 

ETGS 

MODE1–0 


INTERFACE 

DIFFERENTIAL 

MODE SUPPORT 

BUS CONFIGURATION 

NO CONNECT


Packaging 

The FAS366U is available in a 128–pin plastic quad flat pack (PQFP). The pin diagram for this package is 

illustrated in figure 5. The FAS366U package dimensions are shown in figure 6. 

ESD13 

ESD12 

NC 

VDD 

VSS 

DB0 

DB1 

DB2 

DB3 

DB4 

DB5 

VSS 

DB6 

DB7 

DBP0 

DB8 

DB9 

DB10 

VSS 

DB11 

DB12 

DB13 

DB14 

DB15 

DBP1 

VSS 

ESD14 

ESD15 

PAD0 

PAD1 

102 

101 

100 

99 

98 

97 

96 

95 

94 

93 

92 

91 

103 

104 

105 

106 

107 

108 

109 

110 

111 

112 

113 

114 

115 

116 

117 

ÁÁ 

ÁÁ 

118 

119 

120 

ÁÁ 

ÁÁ 

121 

122 

123 

ÁÁ 

ÁÁ 

124 

125 

126 

127 

128 

ÁÁ 

ÁÁ 

1 

2 

3 

4 

5 

6 

7 

8 

9 

10 

11 

12 

13 

14 

15 

16 

17 

18 

19 

20 

21 

22 

23 

24 

25 

26 

27 

28 

29 

30 

31 

32 

33 

34 

35 

36 

37 

38 

ÁÁ 

ÁÁ 

RESETO 

RESETI 

INT 

DBRD 

PAD2 

VSS 

PAD3 

PAD4 

PAD5 

PAD6 

PAD7 

PADP 

NC 

VSS 

CLK 

VDD 

ESDP1 

ESD0 

ESD1 

ESD2 

ESD3 

VSS 

SD12 

SD13 

SD14 

VSS 

SD15 

SDP1 

90 

89 

88 

87 

86 

85 

84 

83 

82 

81 

80 

79 

78 

77 

76 

75 

74 

73 

72 

71 

70 

69 

68 

67 

66 

65 

FAS366U 

DBWR 

VSS 

VDD 

DREQ 

DACK 

PAUSE 

DIFFM 

VDD 

CS 

RD 

WR 

NC 

VDD 

VSS 

ETGS 

EIGS 

ESD11 

ESD10 

ESD9 

ESD8 

VSS 

SD11 

NC = NO CONNECT 

Figure 5. FAS366U Pin Diagram 

SD0 

SD1 

SD2 

VSS 

SD3 

SD4 

SD5 

NC 

VSS 

SD6 

VSS 

SD8 

IO 

REQ 

CD 

VSS 

VDD 

ESEL 

NC 

ERST 

6 FAS366U 53366–580–01 B 

SD10 

SD9 

64 

63 

62 

61 

ÁÁ 

SD7 

SDP0 

ATN 

Á53 Á 52 

Á 

Á 51 

50 

Á 

Á 49 

Á48Á Á 47 

Á 

Á 46 

45 

Á 

Á 

60 

59 

58 

57 

56 

55 

54 

44 

Á43Á Á 42 

Á 

Á 

41 

40 

Á 39 

BSY 

NC 

VSS 

ACK 

RST 

MSG 

SEL 

VSS 

NC 

ESD4 

ESD5 

ESD6 

ESD7 

ESDP0 

DIFFSENS 

VSS 

A0 

A1 

A2 

A3 

MODE1 

MODE0 

EBSY

17.2 � 0.25 

PIN 102 

PIN 103 

14.00 

PIN 128 

PIN 1 

23.2 � 0.25 

20.00 

INDEX MARK 

Electrical Characteristics 

PIN 38 

PIN 65 

PIN 64 

PIN 39 

0.8 � 0.15 

Figure 6. FAS366U Mechanical Drawings 



4� TYP 

Table 1. Operating Conditions 

A 

0.18 � 0.05 

1.6 

REF 

DETAIL A 

0.23 � 0.05 

0.5 � 0.1 

2.8 TYP 

3.4 MAX 

+ 0.1 

0.3 

–0.05 

NOTE: ALL DIMENSIONS ARE IN MILLIMETERS. 

Symbol Description Minimum Maximum Unit 

VDD Supply voltage 4.75 5.25 V 

IDD a Supply current (static IDD) TBD mA 

IDD b Supply current (dynamic IDD) TBD mA 

TA Ambient temperature 0 70 o C 

Table Notes 

Conditions not within the operating conditions but within the absolute maximum stress ratings may cause the chip to 

malfunction. 

a Static IDD is measured with no clocks running and all inputs forced to VDD, all outputs unloaded, and all 

bidirectional pins configured as inputs. 

b Dynamic IDD is dependent on the application.


Specifications are subject to change without notice. 

QLogic is a trademark of QLogic Corporation. 

�July 14, 1995 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON–CHIP–1 or (714) 438–2200

FAS366U Fast Architecture SCSI Processor

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