Project One Report

ECE 406: Project One Report Barwick
Each of these modules were outlined with specific requirements. Once these
requirements were defined, they were implemented as well as tested individually.
For example, the Controller block, which keeps track of the different states of the
system, was first outlined using a state diagram and then implemented in Verilog
using a case statement and register.
III. TESTING AND DEBUGGING
Perhaps the most difficult part of this project was testing and debugging.
After each module was designed, a test bench was written for that module to
determine if the module met the requirements detailed in the design process.
Testing each individual module first rather than waiting to test the entire system
proved to be extremely helpful. It caught obvious bugs and prevented me from
feeling overwhelmed. However, it turned out that testing the modules individually
does not guarantee that the over system will function properly. Once the modules
were connected together, there were several issues some of which have been outlined
below.
a. Improper connections
When the microprocessor was first compiled, several errors were received
stemming from the top level module. The specific error was:
ncelab: *W,CUVMPW (./proj1.v,30|74): port sizes differ
in port connection.
The error resulted from not explicitly stating multiple wire labels that
connect each module. If a single wire connects the modules, such as the “clock”,
it does not need to be defined as a wire. However, if it is multiple wires, such as
“D_Data”, the label needs to be defined (ex. “wire [47:0] D_Data;”). I defined
the wires needed wires explicitly and the program complied without error.
b. Bad Fetch Module
After the system successfully compiled, the anomalous behavior shown in
figure two was observed. The system did not seem to be getting the proper
memory address, which is determined by the fetch module. The schematic for
the fetch module was reevaluated and it was determined that the “pc” signal was
not being set properly. During certain states the “pc” signal from the fetch
module needed to be high impedance due to a shared bus. A simple change in the
code within the fetch module fixed this. This obvious bug should have been
caught during the individual module testing and may have gotten through due to
poor testing.
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