Project One Report

ECE 406: Project One Report Barwick
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; Analysis & Synthesis Messages ;
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition
Info: Processing started: Wed Mar 19 23:28:42 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off proj1 -
c proj1
Info: Found 10 design units, including 10 entities, in source file proj1.v
Info: Found entity 1: proj1
Info: Found entity 2: Execute
Info: Found entity 3: alu
Info: Found entity 4: extension
Info: Found entity 5: Controller
Info: Found entity 6: Fetch
Info: Found entity 7: MemAccess
Info: Found entity 8: Writeback
Info: Found entity 9: Decode
Info: Found entity 10: RegFile
Info: Elaborating entity "proj1" for the top level hierarchy
Info: Elaborating entity "Fetch" for hierarchy "Fetch:f"
Info: Elaborating entity "MemAccess" for hierarchy "MemAccess:memacc"
Info: Elaborating entity "Controller" for hierarchy "Controller:cont"
Info: Elaborating entity "Decode" for hierarchy "Decode:dec"
Info: Elaborating entity "RegFile" for hierarchy "Decode:dec|RegFile:regf"
/**These warnings are due to the assignment of the register, but the variable is not
read in my code. These assignments were made to see what the registers contain in
Simvision**/
Warning (10036): Verilog HDL or VHDL warning at proj1.v(532): object "R0" assigned a
value but never read
Warning (10036): Verilog HDL or VHDL warning at proj1.v(532): object "R1" assigned a
value but never read
Warning (10036): Verilog HDL or VHDL warning at proj1.v(532): object "R2" assigned a
value but never read
Warning (10036): Verilog HDL or VHDL warning at proj1.v(532): object "R3" assigned a
value but never read
Warning (10036): Verilog HDL or VHDL warning at proj1.v(532): object "R4" assigned a
value but never read
Warning (10036): Verilog HDL or VHDL warning at proj1.v(532): object "R5" assigned a
value but never read
Warning (10036): Verilog HDL or VHDL warning at proj1.v(532): object "R6" assigned a
value but never read
Warning (10036): Verilog HDL or VHDL warning at proj1.v(532): object "R7" assigned a
value but never read
Info: Elaborating entity "Writeback" for hierarchy "Writeback:write"
Info: Elaborating entity "Execute" for hierarchy "Execute:exe"
Info: Elaborating entity "extension" for hierarchy "Execute:exe|extension:u1"
Info: Elaborating entity "alu" for hierarchy "Execute:exe|alu:u2"
Info: Generated suppressed messages file
C:/Users/Chris/Desktop/PROJECT1/proj1.map.smsg
Info: Implemented 501 device resources after synthesis - the final resource count
might be different
Info: Implemented 19 input pins
Info: Implemented 33 output pins
Info: Implemented 449 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Allocated 163 megabytes of memory during processing
Info: Processing ended: Wed Mar 19 23:28:56 2008
Info: Elapsed time: 00:00:14
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