Algorithms and Data Structures for External Memory

18 Parallel Disk Model (PDM)
architecture-specific. The relative memory sizes and block sizes of the
levels vary from computer to computer. Another issue is how blocks
from one memory level are stored in the caches at a lower level. When
a disk block is input into internal memory, it can be stored in any
specified DRAM location. However, in level 1 and level 2 caches, each
item can only be stored in certain cache locations, often determined
by a hardware modulus computation on the item’s memory address.
The number of possible storage locations in the cache for a given item
is called the level of associativity. Some caches are direct-mapped (i.e.,
with associativity 1), and most caches have fairly low associativity (typically
at most 4).
Another reason why the hierarchical models tend to be more
architecture-specific is that the relative difference in speed between
level 1 cache and level 2 cache or between level 2 cache and DRAM
is orders of magnitude smaller than the relative difference in latencies
between DRAM and the disks. Yet, it is apparent that good EM
design principles are useful in developing cache-efficient algorithms. For
example, sequential internal memory access is much faster than random
access, by about a factor of 10, and the more we can build locality into
an algorithm, the faster it will run in practice. By properly engineering
the “inner loops,” a programmer can often significantly speed up the
overall running time. Tools such as simulation environments and system
monitoring utilities [221, 294, 322] can provide sophisticated help
in the optimization process.
For reasons of focus, we do not consider hierarchical and cache models
in this manuscript. We refer the reader to the previous references
on cache-oblivious algorithms, as well to as the following references:
Aggarwal et al. [20] define an elegant hierarchical memory model, and
Aggarwal et al. [21] augment it with block transfer capability. Alpern
et al. [29] model levels of memory in which the memory size, block
size, and bandwidth grow at uniform rates. Vitter and Shriver [346]
and Vitter and Nodine [344] discuss parallel versions and variants
of the hierarchical models. The parallel model of Li et al. [234] also
applies to hierarchical memory. Savage [305] gives a hierarchical pebbling
version of [306]. Carter and Gatlin [96] define pebbling models of
nonassociative direct-mapped caches. Rahman and Raman [287] and