UML for Embedded Systems III. Detailed Design - Eurecom
UML for Embedded Systems III. Detailed Design - Eurecom
UML for Embedded Systems III. Detailed Design - Eurecom
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slide 31<br />
slide 32<br />
Composite States: Hierarchical State<br />
Machines<br />
State1<br />
State2.1<br />
State2.1<br />
State2.2<br />
H<br />
Page 16<br />
State3<br />
(C) Ludovic Apvrille <strong>UML</strong> <strong>for</strong> <strong>Embedded</strong> <strong>Systems</strong> - Fall 2012<br />
Order of Actions<br />
S1<br />
exit/exS1<br />
S11<br />
exit/exS11<br />
E/actE<br />
Execution sequence when E:<br />
H<br />
H*<br />
S2<br />
entry/enS2<br />
initS2<br />
S21<br />
entry/enS21<br />
exS11 � exS1 � actE � enS2 � initS2 � enS21<br />
(C) Ludovic Apvrille <strong>UML</strong> <strong>for</strong> <strong>Embedded</strong> <strong>Systems</strong> - Fall 2012<br />
Swallow history<br />
Deep history
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