UML for Embedded Systems III. Detailed Design - Eurecom
UML for Embedded Systems III. Detailed Design - Eurecom
UML for Embedded Systems III. Detailed Design - Eurecom
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<strong>Detailed</strong> <strong>Design</strong> Stage<br />
� Purpose<br />
• <strong>Design</strong> the behavior of classes<br />
� State machine diagrams<br />
• Signal sending<br />
• Signal receiving<br />
• Composite states<br />
• Loop, tests<br />
• Setting and use of variables<br />
• Etc.<br />
(C) Ludovic Apvrille <strong>UML</strong> <strong>for</strong> <strong>Embedded</strong> <strong>Systems</strong> - Fall 2012<br />
<strong>Detailed</strong> <strong>Design</strong><br />
� Basics of automata<br />
� Modeling objects with states machines<br />
� <strong>UML</strong> state machine diagram<br />
� TAU G2 state machines<br />
� Examples<br />
(C) Ludovic Apvrille <strong>UML</strong> <strong>for</strong> <strong>Embedded</strong> <strong>Systems</strong> - Fall 2012<br />
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