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SENSOR SIGNAL CONDITIONING
HIGH IMPEDANCE SENSORS
The situation just described for the AD820BN DIP packaged device is by no means
unique, as pin 1 is a standard offset trim pin on many op amps. This circumstance will
always tend to leak current into any high impedance source seen at pin 2. There are also
cases for follower-connected stages where leakage is just as critical, if not more so. In
such cases the leakage goes into pin 3 as a high impedance, typically from pin 4, which is
–VS. Fortunately however, there is a highly effective answer to controlling both of these
leakage problems, and that is the use of circuit guard techniques.
Guarding is used to reduce parasitic leakage currents, by isolating a sensitive amplifier
input from large voltage gradients across the PC board. It does this by interposing a
conductive barrier or screen between a high voltage source and a sensitive input. The
barrier intercepts the leakage which would otherwise flow into the sensitive node, and
diverts it away. In physical terms, a guard is a low impedance conductor that completely
surrounds an input line or node, and it is biased to a potential equal to the line's voltage.
GUARD
INPUT
GUARD
GUARD
INPUT
GUARD
1
2
3
4
1
2
3
4
AD820BN
"N"
PACKAGE
AD820BN
"N"
PACKAGE
8
7
6
5
8
7
6
5
INVERTER
FOLLOWER
Figure 4-41: Guard techniques for inverting and non-inverting op amp stages
using DIP package devices
Note that the low impedance nature of a guard conductor shunts leakage harmlessly away.
The biasing of the guard to the same potential as the guarded pin reduces any possibility
of leakage between the guard itself and the guarded node. The exact technique for
guarding depends on the amplifier’s mode of operation, i.e., whether the connection is
inverting (like Fig. 4-40), or a non-inverting stage.
Figure 4-41 above shows a PC board layout for guarding the inputs of the AD820 op
amp, as operated within either an inverting (top) or a non-inverting gain stage (bottom).
This setup uses the DIP ("N") package, and would also be applicable to other devices
where relatively high voltages occur at pin 1 or 4. Using a standard 8 pin DIP outline, it
can be noted that this package’s 0.1” pin spacing allows a PC trace (the guard trace) to
pass between adjacent pins. This is the key to implementing effective DIP package
guarding— the complete surrounding of the guarded trace with a low impedance trace.
3
2
3
_
AD820BN
+
+
AD820BN
2 _
6
6
4.45