M.Sc. (IT.) First Semester Examination,2011 Paper-III(MIT-102 ...

M.Sc. (IT.) First Semester Examination,2011
Paper-III(MIT-102):Computer Architecture
Model Question Paper
Attempt all questions. Marks are shown against each question.
Section –A
Time:1:30hrs Max Marks :75
Answer the following questions. 1*45=45
1. Acorn RISC machine, a microprocessors family developed by
A).US B). UK
C). SPAIN D). RUSSIA ( )
2. What is SECDED?
A). Single error correcting double error
B). Single email correcting double error
C). Single error correcting double email
D). Single email correcting double email ( )
3. Load operation of our CPU IS presented by
A). AC: =M (adr) B).DR: =M (adr)
C). M (adr) = AC D). M (Z):= AC ( )

4. Who proposed CPU organization…………………:
A). Von Neuman B).Denis richi
C). Mick D). Bell and newels ( )
5. A 32-bit floating point no. conforming to the IEEE 754 standard represents the real no. n is given
by the formula.
A). N= (-1) s 2- e+127 (1,M) B). N= (1) s 2- e+127 (1, M)
C). N= (-1) s 2- e+127 (1, M-1) D). N= (-1) s 2- e-127 (1,M) ( )
6. Which machine perform load and store architecture.
A). Cisc machine B). Risc machine
C). Intel D). CISC-Motorola ( )
7. A handhelds” personal digital assistant “is introduced by?
A). Apple corp. B). IBM
C). Cruse D). ARM1 ( )
8. Which processors family is primarily aimed to design low-power, low cost applications.
A). Intel B). Cisc developer
C). IBM D).arm ( )
9. Implementation of ACXN is refers as:
A). AC+AC +……..+AC B). AC+AC -……..+AC
C). AC+AC +……..-AC D). AC*AC +……..+AC ( )

10. Floating point multiplication can be expressed in the term of :
A).Pi+1:=Pi+xj2 i y B). Pi1:=Pi+xj2 i y
C).Pi-1:=Pi+xj2 i y D). Pi+2:=Pi+xj2 i y ( )
11. ALU expansion can be divided in which one of the following.
A). Temporal expansion and spatial expansion
B). Temporal expansion and integral expansion
C). Local expansion and spatial expansion
D). Temporal expansion and local expansion ( )
12. Advanced micro devices 2901 bit sliced ALU developed by.
A). Mick and brick B). Mux and brick
C). Brick and deiv D).Mick and grill ( )
13. In multiplication the shift multiplier is added to the multiplicand to form the …………………:
A). Relation B).product
C). Divisor D). Semiconductor DRAM ( )
14. Array implementation of the booth multiplication algo. Developed as.
A). Brick B). Koren
C). Grill D). Moore ( )
15. The owner of booth multiplication algorithms is.
A). Andrew D. BOOTH B). SD BOOTH
C). Brick Booth D). 4. Mick ( )

16. Combinational arithmetic logic unit design by?
A). Cruse B). Robertson
C). Hansen & Hayes D). Mick ( )
17. Robertson describe multiplication algorithms for ………………… fraction.
A). 1’s complement B). 2’s complement
C). 0’s complement D). None ( )
18. Booth multiplier algo which can be implemented with :
A). Cisc machine B). Robert’s multiply instruction
C). ARM’S multiply instruction D).Intel machine ( )
19. Hardwired controller approaches design by
A).Shanley and Anderson B). Shill
C). Hayes and barnov D). Grill ( )
20. Which one is used Finite – state machine theory for control design.
A). Mealy & Moore B). Robertson
C). Hayes D). Grill ( )
21. In which year Euclid’s algorithm used for a calculating gcd(x,y):
A). 1990 B). 1993
C). 1992 D). 1999 ( )
22. One-Hot method which can be used in the area of:

A). GCD processing B). Hardwired control
C). Pipeline D). Error detection ( )
23. In control designing One –Hot method always used.
A). one flip-flop per state B). Two flip-flop per state
C). Three flips-flop per state D). None ( )
24. Pipeline used performance/cost ratio in PCR define as.
A). PCR=F/K B). PCR=1/K
C). PCR=F-1/K D). PCR=1/F ( )
25. Pipeline organization of the MIPS R2/3000 is organized by.
A). Kane& Heinrich B). Steve
C). Robertson D). Grill ( )
26. Euclid’s algorithm used for gcd (x, y) calculating is designed by.
A). Cormov B). Grill
C). Moore D). Mick ( )
27. Every clock cycle logic circuit in microprogramming performs the operation, in the term of:
A). Cout µPC:=Y+Cin B). Cin µPC:=Y+Cin
C). Cout µPC:=µY+Cin D). Cout µPC:=Y+Cout ( )
28. Define the cost c of memory as n follows as :
A).c=C/S Dollar per bit B). c=C-1/S Dollar per bit
C). c=S/S-1 Dollar per bit D). c=S/C Dollar per bit ( )

29. In memory system Cost/performance is designed by.
A). Mealy & Moore B). Robertson
C). Cooke & white D). Grill ( )
30. Which type of semiconductor memory contain refreshing unit.
A). DRAM B). DRO
C). SRAM D).ROM ( )
31. 64-MB dram chip was developed for semiconductor memory design:
A). IBM B).micron technology
C). Microsoft D). Semiconductor DRAM CMOS lab ( )
32. Data line can be used in complex way which one is used.
A). Robertson B). Weste and Eshraghian
C). Grill D). Moore ( )
33. Memory address depends upon the characterizes of computer program called ………………….. .
A). ACCESS time B). Cost
C). Locality of reference D). Virtual address ( )
34. Which one is continuous increasing when we are used in memory hierarchical design?
A). Cost B). Access time
C). Capacity D). Time ( )
35. Cost can be referring in the term of.
A). C=S1c1+c2S2/S1+S2 B). c=S1c1-c2S2/S1-S2
C). C=S1c1+c2S2/S1-S2 D). c=S1c1-c2S2/S1+S2 ( )

36. cache design for the power pc 620 designed by:
A). Ewedemi, Todd B). Mick
C). Robertson D). Grill ( )
37. Peripheral component are interconnected with bus design describe by.
A). Shanley and Anderson B). Shill
C). Robertson D). Grill ( )
38. Interrupt occurring during the execution of an instruction is precise condition follows by.
A). Moudgill B). Robertson
C). Shanley D). Grill ( )
39. Degree of parallism is “n” in term of :
A). Sn= T (1)/T (n) B). Sn= T (1)-1/T (n)
C). Sn= T (n)/T (1) D). Sn= T (1)/T (n) -1 ( )
40. Cache coherence protocol design in which year.
A). 1996 B). 1920
C). 1995 D). 1960 ( )
41. MESI Cache coherence protocol design by.
A). Shanley and Anderson B). Andrew
C). Robertson D). Mick ( )
42. Each ARPANET site had a computer called.

A). IMP B). ICP
C). CMP D). GCC ( )
43. ARPANET which provide packet switching in which year.
A).1960 B). 1918
C). 1971 D). 1970 ( )
44. The K-masked interrupted signal is fed in to a priority encoder that produces.
A). a [log2K-1 ]-bit B). a-1 [log2K-1 ]-bit
C). a [log2K ]-bit D). a-1 [log2K]-bit ( )
45. Acknowledge signal allow a long delay one or more bus cycles called.
A). Read state B). Clock state
C). Waite state D). Write state ( )