Low Power VLSI Design For Multimedia Applications Compression ...

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Low Power VLSI Design For Multimedia Applications
第二屆 (2003) 國家新創事業獎公開賽 優選獎
(創紀錄最年輕的得獎公司)
Compression IP is us!
Born in 工研院 52館308室, Feb. 2003
IITGmbH in Munich, German Federal Government sponsored
Taiwan Imaging Tek (TIT)
Combines
top talents,
exciting technology and
the best business cultures
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Historical Moment (29-10-03, 27-05-01)
優選獎 winner, 10-2003
among 193 companies 2003
TOP 10 winner (among 257 teams)
in MBPW 2001, Munich, Germany
沛錦科技願景 - 快樂 創新 的 研發 團隊,踏實 守紀 的追求效益
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美國
綠色矽島
台
灣
Pioneer of A-V IP business
德國
產、官、學、研
+ 國際合作
致力台灣 科技 質與量 的 躍昇
謹將慈愛、萬能的 上帝
恩賜給沛錦的一切
獻給我們熱愛的祖國!
Royalty Fee
Royalty
沛錦
The Dream Is Alive! (NASA Museum 3D Movie Title)
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Fee

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Low Power VLSI Design for Visual Communications
� Power saving from system, algorithm and architecture
� Principle of low power VLSI design
� Logic gate
� Circuit
� Application specific VLSI Cell library
� Low power memory design (DRAM, SRAM, ROM, NVM)
� Low power analog circuit (Ex. Sense/Op amp)
� Application specific designs
� Locality
� Stand-by mode
� Device/Process
� Low power process with low power cells
� Design tradeoffs (Examples: Data Path, CPU)
Reference:
1. Gary K. Yeap “Practical Low Power Digital VLSI Design” by Kap, 1998
2. Dr. SY Huang, NTHU (Dr.黃錫瑜, 清華 U)
3. K. Roy, S. Prasad “Low-Power CMOS VLSI Circuit Design”
4. “VLSI Memory Chip Design”
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Hierarchical Low Power VLSI Design
System
Algorithm
Architecture
Circuit/Logic
Layout
Process
Power budgeting, component selection, S/W vs. H/W
block partitioning, power management
Algorithm, data transformation, supply voltage scheduling,
data representation, application specific
Parallelism, pipelining, re-timing, adaptive voltage scaling,
optimal choice of data representation, optimization of signal
ordering, minimization of glitch/noise, optimal resource
allocation
Re-sizing, logic style, parallelism, MTCMOS, VTCMOS,MSV,
DGCMOS, power management, stand-by
Power driven P&R, low power layout, low power cell library
Low powered device, Extended technologies (with special cell lib
incl: MTCMOS, VTCMOS, DGCMOS, MSV ), alternative
technology (SOI, SOIAS…)
(Modified from TUM, Tech. Univ. Munich)
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Software
Hardware
Software vs. Hardware
Advantage Disadvantage
�Seems to be free
�High flexibility
�Ease of compatibility
�High speed
�Low power
�High efficiency
� Hardware solution:
�High power consumption
�Slow in execution
�Inefficient
�High die cost
�Less flexibility
�Low compatibility
Rule of Work partitioning
� Computing power hunger: ME/MC, DCT, VLC
� Fixed and routine calculation
� Software solution:
� Misc.
� Packing, data parsing,
A-V synchronization
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Data Compression Algorithms to Save Data & Power
PC /
Internet
Good algorithm achieves:
High performance
Low cost
Low Power
US patent pending
U-Controller
(Ex. 8051)
SM1 SM2 . . . SMn
Data Path ROM/SRAM
VLC
沛錦 IP
Flash
Memory
ImagingTek
Compression
Codec
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Low Power CPU and Caching System (1)
� Instruction hit rate vs. ration between Register and L1/L2cache
� Application dependent!
� Hit rate vs. the cache size and instruction allocation
� Access and storage of the most frequently used instructions (M.E.,
DCT, VLC)
� Probability of the most recent accessed instruction
� Continuous instruction and data access by Column Switching
. . .
Thumb of rule: Avoid accessing larger cache/buffer
CPU
Reg.
Reg.
Reg.
L1
Cache
L2
Cache
Off-Chip
Memory
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Power Management Mode
� Example: PowerPC 603
Mode 80 MHz
No power management 2.54 W
Dynamic power management 2.20 W
DONE 366 mW
NAP 135 mW
SLEEP 105 mW
SLEEP without PLL 19 mW
SLEEP without system clock 2 mW
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Principle of Low Power VLSI Design
� Reducing the power supplier level
� Using lowest frequency of Clocks
� Minimizing the geometry
� Minimizing the switching activities
� Applying parallel and/or pipelining design to lower
requirement frequency of operation
� Removing redundant buffer/loadings and
operations (SoC)
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Performance management(1):Multiple CLKs
Multiple clocking schemes: each driving circuit of different
performance requirement
66 MHz
Cache
Memory 1
Cache
Memory 2
133 MHz
JPEG/DCT
50 MHz
100 MHz
System
Controller
(8051/ARM7)
200 MHz
Motion
Estimator
Frame
Buffer
Buffer
10 MHz
20 MHz
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Performance management (1):Multiple VDDs
Multiple voltage schemes: each driving circuit of different
performance requirement
3.0V
Cache
Memory 1
Cache
Memory 2
133 MHz
JPEG/DCT
2.7V
2.5V
System
Controller
(8051/ARM7)
3.3V
Motion
Estimator
Buffer
2.0V
Frame
Buffer
1.5V
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Performance management (Continued)
Boost supply voltage in critical path
DC Voltage controller/regulator (US patent pending)
Data In
Clock
Critical
timing
info
VCC Level
Controller
Regulator
Target Block
300 MHz
Data Out
Break 1
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Instruction
Fetch
.
.
.
.
Switching Activity Management
Avoid unnecessary switching!
Ex. Mux the input to multiplier and ALU
ALU_Enable
ALU Multiplier
Multiplier_Enable
DA[0:15]
DB[0:15]
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Switching Activity Management (Continue)
Wide width CPU/ALU/Data Path/Multiplier…
� Mask out some nonfunctioning bits
� Both HW or SW solution work
8-bit
CPU
8-bit
CPU
8-bit
CPU
8-bit
CPU
O-Bus
X-Bus
Y-Bus
Chip
Select
Chip
Select
Chip
Select
Chip
Select
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Switching Activity Management (Continue)
Bus sharing (long bus load)
� With timing or phase control
� Min. coupling noise effect
� Min. switching activities
� Min. area
s1 D1
s2 D2
Separate data bus
s1 D1
s2 D2
Shared data bus
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Switching Activity Management (Continue)
Reducing long load
� By removing the redundant load
1 1
A[0:15] B[0:15]
FA
1’s complement [0:15]
1’s complement
1 1
A[0:15] B[0:15]
FA [0:15]
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CLK:1/3 f
Lower Supply Voltage: Pipelined architecture
CLK: f
Function 1
Function
Function 2
3 pipes of sub-function: cut down the frequency and supply voltage level
Function3
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Lower Supply Voltage: Parallel Architecture
Trade VCC with lower clock rate
to achieve the same output throughput
Input Output
Processor
CL=C
VCC=V
Freq.=f
f
Input
CL=2.2C
VCC=0.6V
Freq.=0.5f
Processor
f / 2
Processor
f / 2
Output
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Low Power Profit (From the Gap)
Low Power
SoC
Limitation
Logic
(CPU)
Memory
Low Power Multimedia System:
Trade logic with memory
MPEG vs. JPEG
MPEG 1 vs. MPEG 4
MP3 vs. AAC (audio)
IO
Power
Technology migration trend
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Reduce Operation: Length Reduction
Operand selection: Take advantage of the correlation between
pixels. Calculate only a certain length of the LSB bits
Benefit:
� Performance enhancement
� Reduce power consumption
164 162 162 162 162 163 163 164
163 161 159 162 167 164 165 163
164 163 163 161 159 156 159 160
163 158 152 152 153 155 153 156
154 153 152 151 150 149 148 149
149 151 150 150 151 152 150 149
147 146 148 151 149 150 148 149
148 149 148 148 147 147 146 146
A sub-Claim of
an US patent in
M.E. & DCT
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Reduce Operation: Simple Operator
Take advantage of the smaller gate of circuit
Ex1. Y = AB + AC � Y = A * (B + C)
Ex2. Y = 7X � Y = (X

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Noise
� Where the noise come from?
� Inductance effect (from current flow, L(di/dt) )
� Supply noise: Power and ground bouncing
� Coupling noise
� Others:
� Alpha particle (Dangerous to DRAM)
� External noise sources
� Thermal noise (sensitivity high circuit)
� Solution of noise reduction
� Avoid simultaneously switching: distributed timing
� Keep sensitive circuits away from noise source
� Substrate coupling: guard ring, moving away the source
� Noise elimination circuits: Cap, RC, circuits …
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Low Power Layout
How layout can minimize the power consumption
� Small Diffusion area (output node) in layout
� Use upper layer connecting material (M6,M5… than M1)
� Distance from coupling signal
� Minimized input gate size (W_min.)
Co
Cc
Cg
CL = Co + Cc + Cg
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Low Power Memory Design (Continue)
.
.
The Diagram of a Memory Block
Row
Decoder
Word
Line
Driver
Sense Amplifier
Column Decoder
Cell
SA
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Low Power Memory Design(Continue)
� Most power consuming circuit:
� Word line driver
� Sense amplifier
� Pre-charging
� Scalable word line driver: depends on the load capacitance
� Scalable sense amplifier: current source vs. gain
� Multiple bank of memory arrays (cost. Applications…): small
cap. Load, low power waste
� Continuous data accessing: from column switching
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Pre-charge
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CBL
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Low Power Memory Design(Continue)
Pre-charging scheme
� For performance and cell size consideration, most memories
Ex. SRAM
pre-charge BL and BL to Vcc
SA
BL
CBL
CLK
WL
Pre-charge
BL vs. BL-Bar
SA_Enable
Data Out
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� Ground the BL and BL!! Why?
ImagingTek’s Sensing Scheme
� Clean Ground! Discharge
faster thru NMOS
� Slow pull-up by PMOS
� Less noise!
� Allow more time for access
� Allow less input
differential voltage
� Low power
� Non-overlapping
between WL and
discharging
(US patent
pending)
D
WL Disable
31
36 37
Self-timer
39
BL
BL
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SA
331
35
38
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void Glitch And Overlapping In Memory
� Glitch might turn on memory cell (SRAM/ROM even severe)
� Overlapping during word line transition
� Overlapping of Word line and pre-charging
� Word line glitch causes power consumption within cell
Decoder
M-Cell
M-Cell
X 1000
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� Architecture: Multiple banks
Low Power DRAM
� Self stand-by mode: Refreshing only
those banks with valuable data
� Longer refreshing duration: Reducing
the leaking current
� Leaking current
� Sub-threshold current
� Tradeoff between Vdd and Vt
I_ stand-by = I_leak + I_sub-threshold
P+
BL
WL
I_S
N+ N+
Reversely
biased
I_L
Deep
Drench
Capacitor
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-
-
-
-
-
-
-
-
P- well or
substrate

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Principle of the NMV
� Vt difference to identify the “programmed” and “Erased”
bits.
� V_WL/VCC can turn on the erased cell,
� V_WL/VCC can not turn on the programmed cell.
How to change the Vt
� Programming (Vt=VCC+2V): Hot electron injection
� Erasing (Vt=VCC-1V): Electron tunneling
Vpp
e-
E
Vpp/Vcc
N+ N+
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Vt
Vg= -12V, ..
-8V
Erasing Time
(Log function)
Timing vs. HV Levels
X-, Y- scale are
log function
Vs=12V, ..
8V
Vt
Vg=
Programming Time
(Log function)
12V
11V
10V
9V
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Issues in NVM
� High voltages cause risk of junction breakdown in G,D,S
� Programmed and erased bit voltage margin vs. reprogrammable
cycle times
� Over erase: Vt shift to cause leakage of erases bits(and
circuit failure in reading), might cause failure in reading
� Circuits can minimize the risk: reduced E
WL
Defect
Erased Programmed
0V 2V VCC 5V
Normal
WL
Erased Programmed
0V 2V VCC 5V
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Principle of the Low Power NVM
Consumes high power during programming and erasing
How to achieve low power?
� Reduce the 3 factors: CL, Vcc/Vpp, Time
� Low voltage in Source, Gate and Drain!
� Shorter time of circuit ON!
� Smaller device
� Future trends:
� New NVM ( > year 2006)
Application specific!!!
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Low Power Bus
Conventional: Bus voltage swings from Vdd to Gnd
Low power bus
� Low voltage swing (similar to the USB bus)
Driver
V_bus
V_ref (optional depends on
speed requirement)
“1”
“0”
V_bus
CB
(+/- 100mV swing)
Receiver
V_ref
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Charge Recycling
Energy saving approaches: no discharge if possible
� Charge on higher order data bit moves to lower data bit
� Charge in one circuit moves to another
� Charge flows from one node to another
� One circuit, multiple function
Ex. 1. From B15 discharge to B13
Ex. 2. From a charge pump to a sense amplifier
Ex. 3. From a node moves to another
Ex. 4. From one level changes to another
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Charge recycling from Charge Pump to S.A.
A charge pump with output level of 12V and load of 5pF
� These charge can be used to be the supply of a sense amplifier
� Can be used to charge another charge pump
12 V charge pump
1
2
1 1
2 1
. . .
Regulator
Vo
5 pF
V+
V-
S.A.
Power
Supply
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� Select the right one!
Storage Devices
Latch and Flip-Flop
� In general: a Flip-Flop requires 2X gate/area than a latch
� In HDL coding: understand the coding style and the
synthesis tool’s capability
� Each of the latch and FF is tradeoff among setup time, hold
time, clocking design complexity, time delay. . .
� Key different between latch and Flip-Flop: Latch has ONE
stage and FF has 2 stages (Master-Slave) of storage
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Low power
Q
Low Power Flip-Flop
Q
CLK
D
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D
High gain, High speed, Low power
Q
Q

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Tradeoff Between Gain And Speed
Reducing the current source level still keeps
good speed, but reduce power consumption
� Gain is proportional to the inverse square of the biased current:
Av ~ 1 / I_Bias
� Speed is linearly proportional to the bias current
BW ~ I_Bias
� Performance is proportional to the product of Gain and BW
Av
A1
A2
Area1 = Area2
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High Speed Sensing Amplifier
� Breaking a high gain stage into multiple low gain stages
� Optimizing the current load ration of the current sources
� Trade performance for low power
SA SA SA1 SA SA2
Av=100
I-cs= 50 uA
Av1 = Av2 = 10
I-cs1= 5 uA, I-cs2= 15 uA
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SoC and the Benefit in Low Power
Why SoC
Semiconductor process migration trend: cost down
� Benefit: lower cost of
� Die
� Packaging
� Testing
� Low power from SoC
� Removing redundant buffer
� Remove redundant operation
� Remove I/O pad load capacitor
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Stand-By Mode in Transceiver
Principle: (similar to ) One way Tx / Rx
Why wasting power if no voice to be sent?
� Standby mode + detection
� Multiple stages driver
� Parallelism (US patent pending)
Voice
detector
Stand-By
SA
Signal processing
SA1 SA SA2 . . .
SA
PA
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MTCMOS: Multiple Threshold CMOS Devices
Stand-by
Stand-by
Hi Vt
CMOS Logic
With low Vt
Hi Vt
Low Vt
� Two kinds of devices in cut
down the stand-by current
� Low Vt: operating mode
� High Vt: Stand-by mode
(lower leakage)
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VTCMOS: Variable-Threshold Circuits: Back Biasing
� Low power principle: low Vdd (along with) low Vt
� Problem: higher sub-threshold current
� Solution: Adjust Vt during stand-by mode: back biasing
� Twin well process
VBP: 2V (active)
4V (stand-by)
VBN: 0V (active)
-2V (stand-by)
2 Substrate
Bias Circuits
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Low Power VLSI for Visual Communication
Rule: Algorithm! Algorithm! Algorithm! + Tradeoffs
� SoC: Compressing the Frame Buffer!
� Fast DCT
� Fast ME: Accurate starting point prediction
� Scalable searching range
� Stop buffer clock during DCT, M.E.
� Hi-speed pixel bus
� LSBs and sub-sampling calculations
� Performance (Vdd, Freq.) management
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Low Power Communication System
Cut down the power in critical devices
� Low stand-by current
� Low power display
� Low power level: less bright
� Interleaving mode
� Low power transceiver
� Reducing the switching activity
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Low Power Data Path With Timing Control
PM
T Machine
Flow
Control
8x8/16x16 Buffer
+-

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ImagingTek’s Low Power DCT: world fastest DCT
Means Add Multiply Shift
Gate
Switch
Rate
Eq. 4000 9200 256 150X
Fast
DCT
Integer
DCT
464 192 0 1X
(REF.)
466 96 0 4X
TIT1

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Frame Buffer Compression!
MPEG
V-encoder
Previous
Frame
Off-chip
Next
Frame
US patent
PF
MPEG
V-encoder
Lossless Codec
NF
Single Chip
US Patent
pending
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M.E. Scalable Searching Range
MV=
(0,0)
52
MV=
(6,0)
53
MV=
(0,6)
51
54
US patent
pending
MV=
(3,0)
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TIT’s MPEG Performance Enhancement (1)
Motion
Estimation
17% 10 13%
6 5 13
MC+DCT+Q+
VLC+Packing
55% 32% 13%
SW / FW solution (>2.5X speedup)
ImagingTek
FW + ASIC solution (>4X speedup)
Others
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ImagingTek ASIC solution for MPEG/JPEG
World fastest V-core with
lowest power consumption
(

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Summary
� Principle: Never over design!
Algorithm + Architecture + Circuit + Memory
� System Spec. power budget, floor plan (VDD/GNG)
� Software vs. Hardware partitioning
� Caching system
� Algorithm + VLSI architecture
� Performance management (Vdd, f)
� Switching activity minimization
� Memory (architecture + circuit)
� Cell selection
� Noise, glitch minimization
� Charge recycling
� Analog: Av ��BW trade off
� Standby current reduction
� Low Power VLSI design for Multimedia applications
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CAD for Low Power VLSI Design (1)
Business opportunity
� Industry is crying for low power tools
CAD company
� Automatic (or semi-automatic) optimizing the VLSI
� Pre-design design guidelines (rules)
Service company
� Low power optimization service
� Low power cell library
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CAD for Low Power VLSI Design (2)
� Circuit
� Logic
Automatically Optimization Tool
� Low CL
� Low leakage, low noise, low glitch
� Reducing switching activities
� Optimization HDL coding
� Memory
� CPU
� Scalability
� Bank re-ordering
� Caching
� Power management instruction
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CAD for Low Power VLSI Design (3)
� Architecture:
� stand-by mode
� Minimizing redundant circuit (SoC or …)
� Algorithm transformations
� Low power algorithm selection
� DWT to DCT
� MP3�MP2
� ADPCM-DPCM
� Application specific:
� Flash (memories)
� LCD
� Image sensors, …
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CAD for Low Power VLSI Design (4)
� Steps
� 80-20 theory !!
� Resources
� NSC supported projects
� Industry’s need
� SIG: Special Interest Group
� IP Mall
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