Evaporation vs. Sputtering of metal layers on the - John Covey ...

<strong>Evaporation</strong> <strong>vs</strong>. <strong>Sputtering</strong> <strong>of</strong> <strong>metal</strong> <strong>layers</strong> on the
Backside <strong>of</strong> Silicon wafers
Martina Ciacchi
DEEI, University <strong>of</strong> Trieste,
Trieste, Italy
Infineon Technologies AT
Villach, Austria
martina.ciacchi@infineon.com
Abstract
We present the results <strong>of</strong> the differences observed between
evaporated and sputtered backside <strong>metal</strong>lization processes
on silicon wafers: These two methods <strong>of</strong> fabricating
<strong>metal</strong> <strong>layers</strong> and the activation <strong>of</strong> the backside semiconductor-<strong>metal</strong>
contact follow different physical mechanisms.
Differing crystalline structures <strong>of</strong> the <strong>metal</strong> <strong>layers</strong>
can be observed and the thermal budget <strong>of</strong> the overall
process <strong>of</strong> the wafer is affected in different ways. In this
paper we describe these differences, provide a description
<strong>of</strong> the known physical and mechanical mechanisms
and propose some models. Additionally we report a few
production issues and experiences.
Keywords
Backside <strong>metal</strong>lization, evaporation, sputtering.
INTRODUCTION
In the semiconductor technology the basic requirements
for a backside <strong>metal</strong>lization are: (a) good ohmic contact
between the semiconductor and the first <strong>metal</strong> layer; (b)
good physical adhesion between the silicon and the first
<strong>metal</strong> layer and among the different <strong>metal</strong> <strong>layers</strong> to prevent
detachment effects like peeling; (c) formation <strong>of</strong> an inter<strong>metal</strong>lic
phase <strong>of</strong> the backside <strong>metal</strong>lization with the solder
material during the assembly process in the package.
The challenges for backside <strong>metal</strong>lization in production are
to ensure these basic requirements with high reliability
and low yield loss on thin wafers. In the following we describe
the different physical principles <strong>of</strong> evaporation and
sputtering, present the physical differences <strong>of</strong> the produced
films, and compare the two different deposition
techniques in production.
PHYSICAL PRINCIPLES
The traditional approach to the backside <strong>metal</strong>lization in
semiconductor technology is the evaporation process,
where the target materials are contained in a crucible
mounted at the bottom <strong>of</strong> a large vacuum chamber (Figure
1).
1-4244-0255-07/06/$20.00©2006 IEEE
Hannes Eder
Infineon Technologies AT
Villach, Austria
hannes.eder@infineon.com
Hans Hirscher
UNAXIS Balzers AG
Balzers, Fürstentum Liechtenstein
hans.hirscher@unaxis.com
Figure 1: Scheme <strong>of</strong> principle <strong>of</strong> an evaporation system.
A beam <strong>of</strong> electrons is generated, accelerated and directed
towards the crucible containing the material to be deposited
[1]. Part <strong>of</strong> the surface melts and the material evaporates.
The <strong>metal</strong> deposits itself on wafers mounted on a
rotating cap (this configuration is named “planetary system”).
Some <strong>of</strong> the basic advantages <strong>of</strong> this method are the high
deposition rate and the low damage caused by the deposited
atoms because <strong>of</strong> their low energy. Furthermore , the
evaporation process is an inexpensive process. Many
materials can be evaporated in one run, high throughput
can be achieved for wafers with diameter up to 150mm
(The throughput is determined by the number <strong>of</strong> possible
wafers within one run. W ith increasing <strong>of</strong> the wafer diameter,
the number <strong>of</strong> possible wafers mounted on the wafer
holder is decreasing).
The physical principle <strong>of</strong> the sputtering is the dislocation
<strong>of</strong> atoms from the surface <strong>of</strong> a <strong>metal</strong> target. The dislocation
<strong>of</strong> <strong>metal</strong> atoms is caused by the collision <strong>of</strong> high energy
ions generated in a magnetron assisted DC plasma. The
ejected neutral atoms fly through the plasma and land on
the wafer situated in the opposite side <strong>of</strong> the target [2], [3]
(Figure 2).
99 2006 IEEE/SEMI Advanced Semiconductor Manufacturing Conference

Figure 2: Principal scattering mechanisms affecting
the <strong>metal</strong> atoms during sputtering process.
Multilayer <strong>metal</strong>lizations can be produced in single wafer
tools by visits to chambers with different targets, or in
batch tools with different targets in one chamber. Fig. 3
shows the scheme <strong>of</strong> a single wafer equipment with different
sputtering modules and a central robot to handle the
wafers in high vacuum from chamber to chamber.
Etch
NiV
Al Ti
Central Handler
NiV
Figure 3: Scheme <strong>of</strong> a single wafer sputtertool.
The reproducibility <strong>of</strong> the sputtering process is higher
because the composition <strong>of</strong> the sputter-deposited layer is
better controlled than in the case <strong>of</strong> evaporation. This
leads to a higher uniformity <strong>of</strong> the mechanical and electrical
properties <strong>of</strong> the backside <strong>metal</strong>lization.
Before deposition <strong>of</strong> the backside <strong>metal</strong>lization it is necessary
to remove any native oxides from the silicon backsurface.
Otherwise these oxides prevent the formation <strong>of</strong> a
good electrical contact. In a sputtering clustertool (see fig.
3) it is possible to perform an in situ etching step (Argon
pre-clean chamber) under high vacuum conditions,
whereas in case <strong>of</strong> evaporation an additional prior cleaning
step is needed.
The optimization <strong>of</strong> the backside <strong>metal</strong>lization process was
performed by the analysis <strong>of</strong> the different characteristics
observed in the crystalline structure <strong>of</strong> the <strong>metal</strong>s composing
the backside, the influence <strong>of</strong> the two processes on
key electrical parameters <strong>of</strong> the devices and in the mechanical
behavior <strong>of</strong> the sputtered <strong>metal</strong> <strong>layers</strong>. We ob-
Ag
100
served a difference in all <strong>of</strong> these features when changing
from evaporation to sputtering. It has been observed that
it is possible with the sputtered process to obtain a more
reproducible process. The level <strong>of</strong> the contaminations that
normally are present in the traditional evaporation process
can be decreased and finally the cycle time and throughput
increased for backside <strong>metal</strong>lization.
PROCESS CHARACTERIZATION
The evaporated backside <strong>metal</strong>lization (Al/Ti/Ni/Ag) is
performed in vacuum deposition equipment. The contact
to the semiconductor is achieved via the aluminum layer.
The first function <strong>of</strong> the Al is the electrical interconnection
with low ohmic resistivity. Since this process is quite
“cold” (the temperature during the evaporation is in the
range <strong>of</strong> 150-180°C), after the <strong>metal</strong>lization a further step <strong>of</strong>
thermal annealing is needed in order to activate the ohmic
contact. This is performed inside a furnace with a temperature
higher than 300°C in a controlled inert atmosphere.
According to the phase-diagrams (see fig. 4, [4]) interdiffusion
<strong>of</strong> silicon and aluminum takes place, which leads to
a phenomenon known as “spiking”.
Temperature °C
900
700
500
300
660.452 °C
(Al)
L
12.6
577 °C
0 10 20 30
Al Weight Percent Silicon Si
Figure 4: Al-Si phase diagram
The Al layer also prevents the interdiffusion between Ti
and Si which would lead to Ti-silicates. These compounds
can have very high melting temperatures and thus can be
very brittle.
The Ti-layer is a barrier against the diffusion <strong>of</strong> the Ni
through the Al toward the Si. The Ni layer is the main
component for the soldering process since it easily reacts
with most <strong>of</strong> the common s<strong>of</strong>t solders. The function <strong>of</strong> the
silver layer is to protect the underlying <strong>layers</strong> <strong>of</strong> Ni and Ti
from oxidation which can cause problems at the solder and
glue die-attach steps.

Figure 5 shows the cross-section <strong>of</strong> an evaporated backside
<strong>metal</strong>lization. It can be observed that the evaporated
Ni has a “clustered” crystalline structure.
Figure 5: Cross section <strong>of</strong> an evaporated Ni layer.
The main difference <strong>of</strong> the sputtered b ackside <strong>metal</strong>lization
developed by Infineon Technologies compared to the
evaporated <strong>metal</strong>lization is the use <strong>of</strong> a Ni-7V (wt %) target.
By adding Vanadium the target NiV changes to a
nonmagnetic material. This firstly allows the application <strong>of</strong>
a standard ma gnet system (Planar Magnetron) and secondly
an increased target thickness (no loss <strong>of</strong> magnetic
flux). The function <strong>of</strong> each layer is the same as for the
evaporated backside <strong>metal</strong>lization. An in situ sputtered
pre-clean is performed in the etch module prior the first Al
deposition.
The main parameters taken into account to define the target
process were the sputtering energy, the thicknesses <strong>of</strong>
the <strong>metal</strong> <strong>layers</strong> and the time needed for each <strong>of</strong> the sputtering
processes. These parameters affect the temperature
<strong>of</strong> the wafer during deposition. A reliable temperature performance
is needed, since we wanted to develop an in situ
annealing process without an additional annealing step
after <strong>metal</strong>lization. Figure 6 shows a simulation <strong>of</strong> a typical
temperature pr<strong>of</strong>ile during sputtering. The temperature
was monitored by a pyrometer fixed at the chuck <strong>of</strong> the
sputtering chamber. One <strong>of</strong> the basic targets <strong>of</strong> all fabrication
processes is to define a process-window where stability
in terms <strong>of</strong> homogeneity and reproducibility is assured.
To understand how the stability <strong>of</strong> the process has been
accomplished, consider the temperature pr<strong>of</strong>ile in figure 6
in more detail. Each point <strong>of</strong> the curve corresponds to a
certain thickness <strong>of</strong> the sputtered layer and as the time
goes on the layer <strong>of</strong> course becomes thicker.
It is important to check in which range <strong>of</strong> the curve <strong>of</strong> Figure
6 the process lies. If the process lies in the range “A”
this means that a slight shift <strong>of</strong> some process parameters
could lead to a lower temperature budget with the possible
consequence that the backside ohmic contact is not activated.
So it is important that the target-process lies far
from the “knee” <strong>of</strong> that curve as for instance in the area
101
“B”. In this range, a slight deviation <strong>of</strong> some process parameters
will not a ffect the activation <strong>of</strong> the ohmic contact.
temperature [°C]
A B
t1 t2 t1´ t2´
Figure 6: Temperature/time characteristics for the
sputtering <strong>of</strong> the NiV layer.
Reliable temperature behavior is important because at
sputtering temperatures <strong>of</strong> around 300°C inter-diffusion
between silicon and aluminum according to the phase diagram
shown in Figure 4 takes place. As the silicon atoms
move inside the <strong>metal</strong> the aluminum fills the voids left by
the semiconductor. This phenomenon, as already mentioned,
is known as “spiking”. With this starting point, a
qualitative approach in the analysis <strong>of</strong> the backside has
been the observation <strong>of</strong> the spiking density at the interface
between silicon and backside <strong>metal</strong>lization. We removed
the backside <strong>metal</strong>lization and took SEM pictures
<strong>of</strong> the remaining silicon surface.
An objective approach to judge the electrical contact is
measuring the ohmic resistance <strong>of</strong> the silicon-<strong>metal</strong> interface
via TLM measurements (basically a 4-point test) [5],
[6]. The results <strong>of</strong> these measurements show that the optical
inspection <strong>of</strong> the spiking is a good qualitative prediction
<strong>of</strong> the ohmic behavior <strong>of</strong> the <strong>metal</strong>lization. It has been
verified that an increase <strong>of</strong> the spiking density (due to an
increased thermal budget) can be related to a lower value
<strong>of</strong> the ohmic resistance. Moreover, in the limit <strong>of</strong> no spiking
the TLM measurement will reveal a Schottky contact.
Figure 7: Example <strong>of</strong> high spiking density.
time [s]

In Figure 7 a quite high and homogeneous distribution <strong>of</strong>
spikes can be observed. The probe had a low ohmic contact,
whereas figure 8 shows the example <strong>of</strong> a probe with
no spikes and bad contact. In the two cases a different
amount <strong>of</strong> silicon grain precipitates can be observed. Also
this phenomenon is related to the thermal budget achieved
during the pro cess.
Figure 8: Example <strong>of</strong> no spiking.
Figure 9 shows the cross-section <strong>of</strong> a sputtered NiV layer.
The sputtered NiV layer shows a quite regular “vertical”
structure, a pore-free texture and small grain size. These
two features contribute to a better adhesion between the
<strong>layers</strong> and an improved behavior during the soldering
process.
Figure 9: Cross section <strong>of</strong> a sputtered NiV layer.
The sputtering process generates a rougher aluminum
layer compared to the evaporation process. The root
cause is the different deposition temperature: <strong>Evaporation</strong>
takes place at about 150°C - 180°C, during the sputtering
process <strong>of</strong> Al we reach about 300°C.
PROCESS EXPERIENCES
The main advantages <strong>of</strong> the sputtering process versus the
evaporation in production are: (a) in situ activation <strong>of</strong> the
electrical contact (b) less manual handling <strong>of</strong> thin wafers
(c) easier control <strong>of</strong> the thickness <strong>of</strong> the <strong>layers</strong> through the
definition <strong>of</strong> a set <strong>of</strong> process parameters (d) higher
throughput.
102
WET PRE-CLEAN
WAFERS LOADING
EVAPORATION
WAF. UNLOADING
ANNEALING
Figure 10: Flow <strong>of</strong> the two <strong>metal</strong>lization processes: (a)
evaporation; (b) sputtering.
This simplifies the whole fabrication flow; a schematic
comparison <strong>of</strong> evaporation <strong>vs</strong>. sputtering is drawn in figure
10. For the sputtered flow the wet pre -clean is substituted
by an in situ Argon sputter pre-clean and the annealing
is carried out during the deposition <strong>of</strong> the backside
<strong>metal</strong>lization.
Table 1 summarizes the comparison between evaporation
and sputtering with reference to a set <strong>of</strong> relevant process
parameters related to the backside <strong>metal</strong>lization. The data
collected was from more than 300.000 processed wafers for
both variants.
Table 1: Comparison <strong>of</strong> some significant process parameter
between evaporation and sputtering.
Process
parameter
Operator time
(minutes for 100
wafers)
Global process
time (minutes
for 50 wafers)
Defect density
(particle/cm 2 )
WAFERS LOADING
SPUTTERING &
INSITU PRE-CLEAN
WAF. UNLOADING
(a) (b)
<strong>Evaporation</strong> <strong>Sputtering</strong> Ratio
243 36 6,7
567 117 4,8

ameter. The “scrap rate” arising from process, operator or
machine failures for the sputtered flow is more than a factor
<strong>of</strong> 3 better than for the evaporation flow.
The sputtered backside <strong>metal</strong>lization and the simplified
fabrication flow minimize manual handling. Due to this fact
and the advantages <strong>of</strong> the in situ Argon pre -clean without
vacuum break the rate for backside adhesion problems
reported from backend is a factor <strong>of</strong> 100 better than for the
evaporated backside.
CONCLUSIONS
The sputtering process developed by Infineon Technologies
has been shown to improve the quality <strong>of</strong> the backside
<strong>metal</strong>liza tion on silicon wafers and reduce process
time. It has also been shown that this method leads to a
“cleaner” process due to the fact that no more wet etch <strong>of</strong>
the silicon surface is needed before starting the sputtering
<strong>of</strong> the first <strong>metal</strong> layer and the number <strong>of</strong> the handling
steps are reduced. These two facts help to avoid contaminations,
which leads to a lower peeling rate and a lower
yield loss from process, operator or machine-failures.
ACKNOWLEDGMENTS
We thank Dr. Vallant, chief <strong>of</strong> the Infineon Technologies
Metal Deposition Unit <strong>of</strong> the Villach Fab, for his support
and all <strong>of</strong> his team for the realization <strong>of</strong> our experiments. A
major contrib ution to this research during the development
and tuning <strong>of</strong> the process was from the collaboration
with UNAXIS. Thanks also goes to Mr. Franz Stückler, Dr.
Daniel Kraft and to all the people in the Failure Analysis
Lab that supported us to further understand and improve
our sputtering process.
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REFERENCES
[1] L. Eckertova: “Physics <strong>of</strong> thin films”, Plenum Press,
1977, chap. 2.
[2] S. Wolf, R.N. Tauber: “Silicon Processing for the VLSI
Era”, Lattice Press, 1986. Vol.1, chap. 10.
[3] C.Y. Chang, S. Sze: “ULSI Technology”, McGrawHill,
1996. Chap. 8.
[4] B.M.Thaddeus: “Binary Alloy Phase Diagramms“,
ASM International, 1990, Vol. 1
[5] S. Kramp: "Quantitative Bestimmung des Rückseitenkontaktwiderstandes",
Infineon Technologies internal
report, 2004.
[6] D.K. Schroder: „Semiconductor material & device
characterization“, 2nd Edition, Wiley Interscience,
1998, chap. 1.
BIOGRAPHY
Martina Ciacchi received her PhD in Electronics at the
University <strong>of</strong> Trieste (Italy) with a thesis regarding semiconductor
device physics. She is currently working for
Infineon Technologies as process engineer and she participated
in the integration <strong>of</strong> the sputtered 4 layer backside
<strong>metal</strong>lization for IC products.
Hannes Eder received his PhD in Physics at the University
<strong>of</strong> Vienna (Austria) with a thesis regarding studies <strong>of</strong> electron
emission <strong>of</strong> solid surfaces under ion impact. He is
currently working as a <strong>metal</strong>lization process engineer for
Infineon Technologies.
Hans Hirscher received his PhD in Physics at the University
Tübingen (Germany) with a thesis regarding the development
<strong>of</strong> a high resolution STEM at 100 kV. He is currently
working as senior process development engineer for
thin wafer processing for Unaxis .