Tutorial de VHDL: Contadores y Simulación
Tutorial de VHDL: Contadores y Simulación
Tutorial de VHDL: Contadores y Simulación
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UTN- FRC Centro C.U.D.A.RManfredi Gustavo Ariel-----------------------------------------------------------------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;-- Uncomment the following lines to use the <strong>de</strong>clarations that are-- provi<strong>de</strong>d for instantiating Xilinx primitive components.--library UNISIM;--use UNISIM.VComponents.all;entity <strong>Contadores</strong> isPort ( Dsalida : out std_logic_vector(3 downto 0);Cinicial : in std_logic_vector(3 downto 0);Habilitacion : in std_logic;Reset : in std_logic;Clk : in std_logic);end <strong>Contadores</strong>;architecture Behavioral of <strong>Contadores</strong> is--************************************************************Signal Dsalida_se : STD_LOGIC_VECTOR(3 downto 0);beginProcess (clk,reset)beginif (Reset = '1') thenDsalida
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