tle4270_V1_6.pdf - Infineon

5-V Low Drop Fixed Voltage Regulator
Features
• Output voltage tolerance ≤ ±2%
650 mA output current capability
Low-drop voltage
Reset functionality
Adjustable reset time
Suitable for use in automotive electronics
Integrated overtemperature protection
Reverse polarity protection
Input voltage up to 42 V
Overvoltage protection up to 65 V (≤ 400 ms)
Short-circuit proof
Wide temperature range
ESD protection > 4000 V
Functional Description
This device is a 5-V low drop fixed-voltage regulator.
The maximum input voltage is 42 V (65 V, ≤ 400 ms). Up
to an input voltage of 26 V and for an output current up
to 650 mA it regulates the output voltage within a 2%
accuracy. The short circuit protection limits the output
current of more than 650 mA. The device incorporates
overvoltage protection and a temperature protection
which turns off the device at high temperatures.
P-TO220-5-11
P-TO220-5-12
P-TO263-5-1
TLE 4270
P-TO252-5-1 P-TO252-5-11
Type Ordering Code Package
TLE 4270 Q67000-A9209 P-TO220-5-11
TLE 4270 S Q67000-A9243 P-TO220-5-12
TLE 4270 G Q67006-A9201 P-TO263-5-1
TLE 4270 D Q67006-A9360 P-TO252-5-1, P-TO252-5-11
Data Sheet 1 Rev. 1.6, 2005-08-09

P-TO220-5-11
(P-TO220-5-1)
1
Figure 1 Pin Configuration (top view)
Table 1 Pin Definitions and Functions
Pin Symbol Function
5
RO D
Ι GND Q
AEP01923
P-TO220-5-12
(P-TO220-5-2)
TLE 4270
1 I Input; block to ground directly at the IC with a ceramic capacitor.
2 RO Reset Output; the open collector output is connected to the
5-V output via an integrated resistor of 30 kΩ.
3 GND Ground; internally connected to heatsink.
1
Ι
GND Q
RO D
AEP02172
1 5
AEP01922
4 D Reset Delay; connect a capacitor to ground for delay time adjustment.
5 Q 5-V Output; block to ground with 22 µF capacitor, ESR < 3 Ω.
Data Sheet 2 Rev. 1.6, 2005-08-09
5
P-TO263-5-1
(P-TO220-5-8)
Ι
RO D
GND
GND
Q
P-TO252-5 (D-PAK)
1 5
Ι RO D Q
AEP02580

Circuit Description
TLE 4270
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of a series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturation of the power element.
The IC also incorporates a number of internal circuits for protection against:
Overload
Overvoltage
Overtemperature
Reverse polarity
Application Description
The IC regulates an input voltage in the range of 5.5 V < V I < 36 V to V Q,nom = 5.0 V. Up
to 26 V it produces a regulated output current of more than 650 mA. Above 26 V the
save-operating-area protection allows operation up to 36 V with a regulated output
current of more than 300 mA. Overvoltage protection limits operation at 42 V. The
overvoltage protection hysteresis restores operation if the input voltage has dropped
below 36 V. A reset signal is generated for an output voltage of V Q < 4.5 V. The delay for
power-on reset can be set externally with a capacitor.
Data Sheet 3 Rev. 1.6, 2005-08-09

Adjustment
Temperature
Sensor
Bandgap
Reference
Figure 2 Block Diagram
Control
Amplifier
Buffer
Saturation
Control and
Protection
Circuit
1
5
I Q
3
GND
Reset
Generator
AEB01924
TLE 4270
Data Sheet 4 Rev. 1.6, 2005-08-09
2
4
RO
D

Table 2 Absolute Maximum Ratings
T j = -40 to 150 °C
Parameter Symbol Limit Values Unit Notes
Input I
Voltage
Voltage
Current
Reset Output RO
Voltage
Current
Reset Delay D
Voltage
Current
Output Q
Voltage
Current
Ground GND
V I
V I
I I
V RO
I RO
V D
I D
V Q
I Q
Min. Max.
-42
–
–
-0.3
–
-0.3
–
-1.0
–
Current I GND -0.5 – A –
Temperatures
Junction temperature
Storage temperature
T j
T stg
Table 3 Operating Range
–
-50
TLE 4270
Data Sheet 5 Rev. 1.6, 2005-08-09
42
65
–
7
–
7
–
16
–
150
150
Parameter Symbol Limit Values Unit Notes
Min. Max.
Input voltage V I 6 42 V –
Junction temperature T j -40 150 °C –
Thermal Resistance
Junction ambient R thj-a – 65
79
V
V
–
V
–
V
–
V
–
°C
°C
K/W
K/W
1) Mounted on PCB, 80 × 80 × 1.5 mm 3 ; 35µ Cu; 5µ Sn; Footprint only; zero airflow.
–
t ≤ 400 ms
internally limited
–
Internally limited
–
Internally limited
–
Internally limited
–
–
–
TO263, TO252 1)
Junction case R thj-c – 3 K/W TO-220/263
Packages

Table 4 Characteristics
V I = 13.5 V; -40 °C ≤ T j ≤ 125 °C (unless otherwise specified)
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
TLE 4270
Output voltage V Q 4.90 5.00 5.10 V 5 mA ≤ I Q ≤ 550 mA;
6 V ≤ V I ≤ 26 V
Output voltage V Q 4.90 5.00 5.10 V 26 V ≤ V I ≤ 36 V;
I Q ≤ 300 mA
Output current
limiting
IQmax 650 850 – mA VQ = 0 V
Current
consumption
Iq = II - IQ Iq – 1 1.5 mA IQ = 5 mA
Current
consumption
Iq = II - IQ Iq – 55 75 mA IQ = 550 mA
Current
consumption
Iq = II - IQ Iq – 70 90 mA IQ = 550 mA; VI = 5 V
Drop voltage VDR – 350 700 mV IQ = 550 mA 1)
Load regulation ∆VQ,Lo – 25 50 mV IQ = 5 to 550 mA;
VI = 6 V
Line regulation ∆VQ,Li – 12 25 mV VI = 6 to 26 V
IQ = 5 mA
Power supply Ripple
rejection
Reset Generator
PSRR – 54 – dB f r = 100 Hz;
V r = 0.5 Vpp
Switching threshold VRT 4.5 4.65 4.8 V –
Reset High voltage VROH 4.5 – – V –
Reset low voltage V ROL – 60 – mV R int = 30 kΩ 2) ;
1.0 V ≤ V Q ≤ 4.5 V
Reset low voltage V ROL – 200 400 mV I R = 3 mA, V Q = 4.4 V
Reset pull-up R int 18 30 46 kΩ internally connected
to Q
Charge current I D,c 8 14 25 µA V D = 1.0 V
Data Sheet 6 Rev. 1.6, 2005-08-09

Table 4 Characteristics (cont’d)
VI = 13.5 V; -40 °C ≤ Tj ≤ 125 °C (unless otherwise specified)
Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
V DU 1.4 1.8 2.3 V –
Upper reset timing
threshold
Lower reset timing
threshold
VDL 0.2 0.45 0.8 V VQ < VRT Delay time trd – 13 – ms CD = 100 nF
Reset reaction time trr – – 3 µs CD = 100 nF
Overvoltage Protection
Turn-Off voltage V I, ov 42 44 46 V –
TLE 4270
1) Drop voltage = VI - VQ (measured when the output voltage has dropped 100 mV from the nominal value
obtained at 13.5 V input)
2) Reset peak is always lower than 1.0 V.
Data Sheet 7 Rev. 1.6, 2005-08-09

V I
Figure 3 Test Circuit
Input
Reset
to µC
Figure 4 Application Circuit
II
1000 µF
470 nF
470 nF
I
RO
I
1
VD
4
D
TLE 4270G
ID
CD
1 5
2
TLE 4270
3
GND
3
2
RO
GND
AES01925
TLE 4270
Data Sheet 8 Rev. 1.6, 2005-08-09
5
IGND
4
Q
D
Q
I Q
IR
100 nF
V R
22 µF
22 µF
V Q
5 V - Output
AES01926

Design Notes for External Components
TLE 4270
An input capacitor C I is necessary for compensation of line influences. The resonant
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1 Ω in series with C I. An output capacitor C Q is necessary for the stability of
the regulating circuit. Stability is guaranteed at values of C Q ≥ 22 µF and an ESR of
< 3 Ω.
Reset Circuitry
If the output voltage decreases below 4.5 V, an external capacitor C D on pin 4 (D) will be
discharged by the reset generator. If the voltage on this capacitor drops below V DL, a
reset signal is generated on pin 2 (RO), i.e. reset output is set low. If the output voltage
rises above the reset threshold, C D will be charged with constant current. After the
power-on-reset time the voltage on the capacitor reaches V DU and the reset output will
be set high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of C D.
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
C D which can be calculated as follows:
C D = (∆t × I D,c)/∆V (1)
Definitions:
C D = delay capacitors
∆t = reset delay time t rd
I D,c = charge current, typical 14 µA
∆V = V DU , typical 1.8 V
V DU = upper reset timing threshold at C D for reset delay time
t rd = ∆V × C D/I D,c
The reset reaction time t rr is the time it takes the voltage regulator to set the reset out
LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs
for delay capacitor of 47 nF. For other values for C D the reaction time can be estimated
using the following equation:
t rr ≈ 20 s/F × C D
Data Sheet 9 Rev. 1.6, 2005-08-09
(2)
(3)

VI
V Q
V D
VRO
VRT
VDU
VDL trd
Figure 5 Reset Time Response
t rr
Power-ON Thermal
Reset Shutdown
TLE 4270
AES01927
Data Sheet 10 Rev. 1.6, 2005-08-09
< trr
Voltage Drop Under- Secondary Load
at Input voltage Spike Bounce
dV
d t
ID,
c
=
C
D

Output Voltage V Q versus
Temperature T j
VQ
5.2
V
5.1
5.0
4.9
4.8
4.7
V I = 13.5 V
Output Current I Q versus
Temperature T j
1200
mA
I Q max
AED01928
4.6
-40 0 40 80 120 ˚C 160
T
1000
800
600
400
200
j
AED01930
0
-40 0 40 80 120 ˚C 160
T
j
Output Voltage V Q versus
Input Voltage V I
R L = 25 Ω
Output Current I Q versus
Input Voltage V I
TLE 4270
Data Sheet 11 Rev. 1.6, 2005-08-09
VQ
I Q
12
V
10
8
6
4
2
0
0 2
1.2
A
1.0
0.8
0.6
0.4
0.2
T j
4
= 125 ˚C
25 ˚C
6 8
V Ι
AED01929
V
10
AED03038
0
0 10 20 30 40
V
V 50
I

Current Consumption I q versus
Output Current I Q
Ι q
3
mA
2
1
0 0
= 13.5 V
Current Consumption I q versus
Input Voltage V I
I q
120
mA
100
80
60
40
20
VΙ
AED03092
20 40 60 80 mA 120
R L = 10 Ω
R L =
20 Ω
50 Ω
Ι Q
AED01934
0
0 10 20 30 40
V
V 50
I
Current Consumption I q versus
Output Current I Q
Drop Voltage V DR versus
Output Current I Q
TLE 4270
Data Sheet 12 Rev. 1.6, 2005-08-09
Ι q
V DR
80
mA
70
60
50
40
30
20
10
0 0
800
mV
700
600
500
400
300
200
100
0
0
VΙ
= 13.5 V
AED03093
100 200 300 400 mA 600
T j = 125 ˚C
25 ˚C
Ι Q
AED01935
200 400 600 mA
I
1000
Q

Charge Current I D,c versus
Temperature T j
I
20
µA
18
16
14
12
10
8
6
4
-40
I D, c
V I = 13.5 V
VD
= 1 V
AED03047
0 40 80 120 ˚C 160
T j
TLE 4270
Upper Reset Timing Threshold V DU
versus Temperature T j
Data Sheet 13 Rev. 1.6, 2005-08-09
V DU
4.0
mA
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0 -40
VΙ
= 13.5 V
V DU
AED03094
0 40 80 120 ˚C 160
T j

Package Outlines
17±0.3
15.65±0.3
1)
13.4
0...0.15
1)
C
9.8 ±0.15
1.7
10 ±0.2
8.5 1)
3.7-0.15 Figure 6 P-TO220-5-11 (Plastic Transistor Single Outline)
±0.2
2.8
±0.3
8.6
A
10.2 ±0.3
0.8 ±0.1
0.25 M
Typical
All metal surfaces tin plated, except area of cut.
GPT09064
TLE 4270
Data Sheet 14 Rev. 1.6, 2005-08-09
A
C
1.27±0.1
0.05
2.4
4.4
9.25 ±0.2
8.4 ±0.4
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
SMD = Surface Mounted Device
3.7±0.3
0.5 ±0.1
3.9 ±0.4
Dimensions in mm

17±0.3
15.65±0.3
1)
13.4
C
0...0.15
Typical
10 ±0.2
9.8 ±0.15
1.7
8.5 1)
3.7-0.15
Figure 7 P-TO220-5-12 (Plastic Transistor Single Outline)
±0.2
2.8
A
6x
0.8 ±0.1
0.25 M
1) All metal surfaces tin plated, except area of cut.
GPT09065
TLE 4270
Data Sheet 15 Rev. 1.6, 2005-08-09
A
B
C
B
1.27 ±0.1
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
SMD = Surface Mounted Device
±0.5
11
13 ±0.5
0.05
2.4
4.4
9.25 ±0.2
0.5 ±0.1
Dimensions in mm

(15)
9.25 ±0.2 1±0.3
0...0.3
5 x 0.8 ±0.1
10
0.25 M
Figure 8 P-TO263-5-1 (Plastic Transistor Single Outline)
±0.2
8.5 1)
1)
7.55
0...0.15
4 x
A
1.7
TLE 4270
Data Sheet 16 Rev. 1.6, 2005-08-09
A
B
4.7 ±0.5
1.27 ±0.1
B
0.05
±0.3
2.7
2.4
0.1
8˚ MAX.
1) Typical
Metal surface min. X = 7.25, Y = 6.9
All metal surfaces tin plated, except area of cut.
4.4
0.5 ±0.1
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
SMD = Surface Mounted Device
0.1 B
GPT09113
GPT09113
Dimensions in mm

±0.5
9.9
6.22 -0.2
1±0.1
(4.17)
0.15 max
per side
4.56
6.5 -0.10
+0.15
5.4 ±0.1
Figure 9 P-TO252-5-1 (Plastic Transistor Single Outline)
±0.15
0.8
5x0.6
1.14
A
±0.1
0.25 M
All metal surfaces tin plated, except area of cut.
+0.05
2.3 -0.10
+0.08
0.9 -0.04
GPT09161
TLE 4270
Data Sheet 17 Rev. 1.6, 2005-08-09
A
B
B
1
0...0.15
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
SMD = Surface Mounted Device
0.51 min ±0.1
+0.08
0.5 -0.04
0.1
Dimensions in mm

5.7 MAX.
±0.1
9.98 ±0.5
6.22 -0.2
(4.24) 1
1)
0.15 MAX.
per side
4.56
6.5
+0.15
-0.05
1.14
0.25 M A
1) Includes mold flashes on each side.
All metal surfaces tin plated, except area of cut.
Figure 10 P-TO252-5-11 (Plastic Transistor Single Outline)
(5)
±0.15
0.8
A
5 x 0.6
±0.1
0.1 B
TLE 4270
Data Sheet 18 Rev. 1.6, 2005-08-09
B
B
0.9 -0.01
+0.20
0...0.15
0.51 MIN.
+0.05
2.3 -0.10
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
SMD = Surface Mounted Device
0.5
0.5
+0.08
-0.04
+0.08
-0.04
GPT09527
Dimensions in mm

Remarks
TLE 4270
Data Sheet 19 Rev. 1.6, 2005-08-09

Edition 2005-08-09
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
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We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
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