Uniprocessor Computer Architecture MP Example: Intel Pentium Pro ...

Chapter 2: Computer-System Structures
■ Last lecture: why study operating systems?
■ Purpose of this lecture: general knowledge of the
structure of a computer system and understanding
technology trends
■ Key issues in a computer system
✦ General System Architecture (CPU, $s, MM, disk, bus, IO
devices and controllers), Uni vs. Multi Processors
✦ I/O Structure (IO interrupts, IO methods, HW support, e.g.,
DMA)
✦ Storage Structure (CPU regs, $, MM, disk)
✦ Storage Hierarchy (why? expensive cheap; small large)
✦ Hardware Protection (user/system, IO protection, Mem
protection)
Uniprocessor Computer Architecture
Example: SUN Enterprise
P P
$ $
✦ 16 cards of either type: processors + memory, or I/O
$ 2
Gigaplane bus (256 data, 41 address, 83 MHz)
100bT, SCSI
$2 Mem ctrl
Bus interface/switch
Bus interface
SBUS
SBUS
SBUS
2 FiberChannel
✦ All memory accessed over bus, so symmetric multiproc. (SMP)
✦ Higher bandwidth, higher latency bus
CPU/mem
cards
I/O cards
Hmm … this looks like a Computer System?
Algorithms Programming
Languages
Compiler
The System
Hardware
Technology,
Architecture
✦ Figure by courtesy of Anant Agarwal, MIT
Runtime,
Operating System
MP Example: Intel Pentium Pro Quad
CPU
Interrupt
controller
256-KB
L 2 $
Bus interface
P-Pro
module
P-Pro bus (64-bit data, 36-bit address, 66 MHz)
PCI
I/O
cards
PCI
bridge
PCI bus
PCI
bridge
PCI bus
✦ Multiprocessor
Example: Cray T3E
P-Pro
module
P-Pro
module
Memory
controller
MIU
1-, 2-, or 4-way
interleaved
DRAM
✦ All coherence and
multiprocessing glue in
processor module
✦ Highly integrated, targeted at
high volume
External I/O
•Multiprocessor system
•Scale up to 1024 processors, 480MB/s links
XY
P
$
Mem
ctrl
and NI
Switch
Z
Mem
1

Let’s look at trends, 1 st Technology Trends
Performance
100
10
1
Mainframes
Supercomputers
Minicomputers
Microprocessors
0.1
1965 1970 1975 1980 1985 1990 1995
The natural building block for multiprocessors is now also about the fastest!
Clock Frequency Growth Rate
Clock rate (MHz)
• 30% per year
1,000
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100
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10 i8086 i80286
i8080
1
i8008
i4004
i80386
R10000
Pentium100
0.1
1970 1980 1990 2000
1975 1985 1995 2005
Architectural Trends: Bus-based MPs
•Micro on a chip makes it natural to connect many to shared memory
– dominates server and enterprise market, moving down to desktop
•Faster processors began to saturate bus, then bus technology advanced
– today, range of sizes for bus-based systems, desktop to large servers
Number of processors
70
60
50
40
30
20
10
Sequent B2100
●
● Sequent B8000
Symmetry81
●
SGI Challenge
●
CRAY CS6400●
●
Sunı
E10000
SE60
Sun E6000
● ●
SE70
●
Sun SC2000●
● SC2000E
● SGI PowerChallenge/XL
AS8400
Symmetry21
●
Power ●
SE10
●
SS1000●
●
SE30
●
● SS1000E
SS690MP 140 ● AS2100●
HP K400 ● P-Pro
SGI PowerSeries ●
SS690MP 120 ● SS10●
● SS20
0
1984 1986 1988 1990 1992 1994 1996 1998
General Technology Trends
• Microprocessor performance increases 50% - 100% per year
• Transistor count doubles every 3 years
• DRAM size quadruples every 3 years
• Huge investment per generation is carried by huge commodity market
180
160
140
120
100
DEC
alpha
80
60
40
20
0
MIPS
Sun 4
M/120
260
IBM
RS6000
540
MIPS
M2000
HP 9000
750
1987 1988 1989 1990 1991 1992
Integer FP
• Not that single-processor performance is plateauing, but that
parallelism is a natural way to improve it.
Transistor Count Growth Rate
Transistors
100,000,000
10,000,000
1,000,000
100,000
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◆ R10000
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i80386
i80286
R3000
R2000
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◆ i8086
10,000
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i8080
i8008
i4004
1,000
1970 1980 1990 2000
1975 1985 1995 2005
• 100 million transistors on chip by early 2000’s A.D.
• Transistor count grows much faster than clock rate
- 40% per year, order of magnitude more contribution in 2 decades
Shared bus bandwidth (MB/s)
100,000
10,000
1,000
100
Bus Bandwidth
Sun E10000
●
SGIı
● Sun E6000
PowerChı
XL ● AS8400
SGI Challenge ● ●
● CS6400
● HPK400
● SC2000E
● SC2000 ● AS2100 ● P-Pro
SS690MP 120ı
●
SS690MP 140
SS1000 ●
SS10/ı ●
SE10/ı
● SS1000E
● SS20
● SE70/SE30
Symmetry81/21
SE60
●
● SGI PowerSeries ● Power
●
Sequentı
B8000
● Sequent B2100
10
1984 1986 1988 1990 1992 1994 1996 1998
2

Phases in VLSI Generation
Transistors
100,000,000
10,000,000
1,000,000
100,000
10,000
i8080
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◆ i8008
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◆ i4004
Bit-level parallelism Instruction-level Thread-level (?)
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Pentium
i80386
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◆ R2000
1,000
1970 1975 1980 1985 1990 1995 2000 2005
■ How good is instruction-level parallelism?
■ Thread-level needed in microprocessors?
Computer-System Operation
■ I/O devices and the CPU can execute concurrently.
■ Each device controller is in charge of a particular device
type.
■ Each device controller has a local buffer.
■ CPU moves data from/to main memory to/from local
buffers
■ I/O is from the device to local buffer of controller.
■ Device controller informs CPU that it has finished its
operation by causing an interrupt.
Interrupt Handling
■ The operating system preserves the state of the CPU by
storing registers and the program counter.
■ Determines which type of interrupt has occurred:
✦ polling
✦ vectored interrupt system
■ Separate segments of code determine what action should
be taken for each type of interrupt
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Economics
■ Commodity microprocessors not only fast but CHEAP
• Development cost is tens of millions of dollars (5-100 typical)
• BUT, many more are sold compared to supercomputers
✦ Crucial to take advantage of the investment, and use the commodity
building block
✦ Exotic parallel architectures no more than special-purpose
■ Multiprocessors being pushed by software vendors (e.g. database) as
well as hardware vendors
■ Standardization by Intel makes small, bus-based SMPs commodity
■ Desktop: few smaller processors versus one larger one? Multiprocessor
on a chip is here.
Common Functions of Interrupts
■ Interrupt transfers control to the interrupt service routine
generally, through the interrupt vector, which contains the
addresses of all the service routines.
■ Interrupt architecture must save the address of the
interrupted instruction.
■ Incoming interrupts are disabled while another interrupt is
being processed to prevent a lost interrupt.
■ A trap is a software-generated interrupt caused either by
an error or a user request.
■ An operating system is interrupt driven.
Interrupt Time Line For a Single Process Doing Output
3

I/O Structure
■ After I/O starts, control returns to user program only upon
I/O completion.
✦ Wait instruction idles the CPU until the next interrupt
✦ Wait loop (contention for memory access).
✦ At most one I/O request is outstanding at a time, no
simultaneous I/O processing.
■ After I/O starts, control returns to user program without
waiting for I/O completion.
✦ System call – request to the operating system to allow user
to wait for I/O completion.
✦ Device-status table contains entry for each I/O device
indicating its type, address, and state.
✦ Operating system indexes into I/O device table to determine
device status and to modify table entry to include interrupt.
Two I/O Methods
Synchronous Asynchronous
Device-Status Table Direct Memory Access Structure
Storage Structure
■ Main memory – only large storage media that the CPU
can access directly.
■ Secondary storage – extension of main memory that
provides large nonvolatile storage capacity.
■ Magnetic disks – rigid metal or glass platters covered with
magnetic recording material
✦ Disk surface is logically divided into tracks, which are
subdivided into sectors.
✦ The disk controller determines the logical interaction
between the device and the computer.
■ Used for high-speed I/O devices able to transmit
information at close to memory speeds.
■ Device controller transfers blocks of data from buffer
storage directly to main memory without CPU
intervention.
■ Only on interrupt is generated per block, rather than the
one interrupt per byte.
Moving-Head Disk Mechanism
4

Storage Hierarchy
■ Storage systems organized in hierarchy.
✦ Speed
✦ Cost
✦ Volatility
■ Caching – copying information into faster storage system;
main memory can be viewed as a last cache for
secondary storage.
Caching
■ Use of high-speed memory to hold recently-accessed
data.
■ Requires a cache management policy.
■ Caching introduces another level in storage hierarchy.
This requires data that is simultaneously stored in more
than one level to be consistent.
■ Caching is typically transparent to the OS
■ Dual-Mode Operation
■ I/O Protection
■ Memory Protection
■ CPU Protection
Hardware Protection
Storage-Device Hierarchy
Migration of A From Disk to Register
Dual-Mode Operation
■ Sharing system resources requires operating system to
ensure that an incorrect program cannot cause other
programs to execute incorrectly.
■ Provide hardware support to differentiate between at least
two modes of operations.
1. User mode – execution done on behalf of a user.
2. Monitor mode (also kernel mode or system mode) –
execution done on behalf of operating system.
5

Dual-Mode Operation (Cont.)
■ Mode bit added to computer hardware to indicate the
current mode: monitor (0) or user (1).
■ When an interrupt or fault occurs hardware switches to
monitor mode.
Interrupt/fault
monitor user
set user mode
Privileged instructions can be issued only in monitor mode.
I/O Protection
■ All I/O instructions are privileged instructions.
■ Must ensure that a user program could never gain control
of the computer in monitor mode (I.e., a user program
that, as part of its execution, stores a new address in the
interrupt vector).
Use of A System Call to Perform I/O Memory Protection
■ Must provide memory protection at least for the interrupt
vector and the interrupt service routines.
■ In order to have memory protection, add two registers
that determine the range of legal addresses a program
may access:
✦ Base register – holds the smallest legal physical memory
address.
✦ Limit register – contains the size of the range
■ Memory outside the defined range is protected.
Use of A Base and Limit Register Hardware Address Protection
6

Hardware Protection
■ When executing in monitor mode, the operating system
has unrestricted access to both monitor and user’s
memory.
■ The load instructions for the base and limit registers are
privileged instructions.
■ Local Area Networks (LAN)
■ Wide Area Networks (WAN)
Network Structure
Wide Area Network Structure
CPU Protection
■ Timer – interrupts computer after specified period to
ensure operating system maintains control.
✦ Timer is decremented every clock tick.
✦ When timer reaches the value 0, an interrupt occurs.
■ Timer commonly used to implement time sharing.
■ Time also used to compute the current time.
■ Load-timer is a privileged instruction.
Local Area Network Structure
7