Synopsys Design Flow

© Synopsys 2012 1 

Digital IC Design 

Victor Grimblatt 

R&D Group Director 

SASE 2012

Agenda 

Introduction 

Electronic systems, an historic 

prospective 

Synopsys Design Flow 

© Synopsys 2012 2

Introduction 


Consumers Driving “Smart” Electronics 

Product Complexity / Capabilities 

1980 1990 2000 2010 2020 



Mobile 

100 

15 

12 

80 

60 

40 

20 

9 

6 

3 

0 

0 

Handset IC Market Value ($B) 

2010 2011 2012 2013 2014 2015 

Tablet IC Market Value ($B) 

2010 2011 2012 2013 2014 2015 

Source IBS, February 2011 

$38B to $109B in 

non-memory ICs in 5 years!

Cloud Infrastructure: 

Data, Data, Data 

Access 

Access 

Access 


Creation Transportation 

Manipulation 

Data 

Storage 

IP Traffic, Exabytes 

Billions 

$80 

$70 

$60 

$50 

$40 

$30 

$20 

$10 

$0 

1990 

1992 

Microprocessor Sales 

1994 

1996 

1998 

2000 

Source: Data Center Knowledge 2011; P. Otellini, Intel, Investor Meeting 2010 

1,200 

1,000 

800 

600 

400 

200 

0 

241.8 

Global IP Traffic 

336.3 

451.2 

2002 

2004 

2006 

593.0 

2008 

2010 

759.2 

2012F 

2014F 

965.5 

2010 2011F 2012F 2013F 2014F 2015F 

Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2011 

10 

8 

6 

4 

2 

0 

0.8 

1.227 

Data Storage 

1.8 

7.91 

2009 2010 2011 2012 2013 2014 2015 

Source: Wikipedia, 2011; Google, Stockholder Meeting 2010

Smart Everything 

Grid Buildings Cars Toasters Dogs…? 

“Smart” 


Software 

Sensors 

Microprocessors 

Storage 

Communication 

Example 

1990 

Lines of 

Code 

1M 

SW & E/E 

% Vehicle 

Cost 

1970 100K 40%

Semiconductor Content 

Electronic Content in Systems Increases 

30% 

25% 

20% 

15% 

10% 

5% 

0% 

Source: ST, TI, IC Insights 


Drivers of Innovation 

and Differentiation 

2 

Better 


Cheaper 

1 

Sooner 

3 

EDA + IP 

Applications 

Electronics 

~$1.31T 

Semi 

$320.8B 

EDA & IP 

$8.4B 

Source: IC Insights, VDC Research, 

Synopsys Estimates

What Drives the Drivers? 

Mobile 

Cloud 

Infrastructure 

“Smart” 


Performance 

Power 

Power 

Performance 

Power/Cost/Perf. 

Integration

Advanced Designs and Tapeouts 

Source: Synopsys Global Technical Services 


Leading the Way at 32/28nm Design 



> 370 32/28nm Active Designs









Advanced Design Trends 

100% 

75% 

50% 

25% 


56% of Respondents Currently Designing at 45nm or Below 

180nm 

130nm 

90nm 

65/55nm 

45/40nm 

32/28nm 

≥250nm 

0% 

2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 

Source: 2011 Synopsys Global User Survey 

Advanced Design Trends 

35% 

30% 

25% 

20% 

15% 

10% 

5% 

0% 

3% 


5% 6% 5% 

≥250nm 180 130 90 65/55 45/40 32/28 22/20

Clock Frequency Trends 

100% 

80% 

60% 

40% 

20% 


101-200MHz 

51-100MHz 

201-300MHz 

301-400MHz 

401-500MHz 

751MHz-1GHz 

>2GHz 

1-2GHz 

0% 

≤50MHz 

2004 2005 2006 2007 2008 2009 2010 2011 


Frequency is Increasing Over 1GHz 

42%

Designs Are Growing More Complex 

30% 

20% 

10% 

0% 

13% 

28% 


12% 13% 

13% 

12% 

6% 

7% 

9% 

6% 

9% 10% 

6% 

9% 

5% 4% 

1-100K 101-500K 501K-1M 1-2M 2-5M 5-10M 10-20M 20-50M 50-100M >100M 


Memory = 48% of Gate Count (on average) 

Logic Memory 

7% 

6% 

16% 

10%

$M 

Hardware/Software Development Costs 

$2.50 

$2.00 

$1.50 

$1.00 

$0.50 

$- 

Source: IBS, Synopsys 

1 3 5 7 9 11 13 15 17 19 21 23 25 27 

Months 


Software Is Half of Time-to-Market 

App-Specific SW 

Low-Level SW 

OS Support 

Design Management 

Post-silicon Validation 

Masks 

Physical Design 

RTL Verification 

RTL Development 

Spec Development 

IP Qualification

Electronic Systems, an Historic 

Prospective 


Key Innovations in Electronics: 

Audio/Video 



Audio/Video 



Audio/Video 



Audio/Video 



Audio/Video 



Audio/Video 



Audio/Video 



Audio/Video 



Audio/Video 



Audio/Video 



Audio/Video 



Audio/Video 


2005 

Sonos


Computers & Communications 


Going to a satellite not so far away! 

Apollo Guidance Computer, ~100 Microns, MIT 


1961 

10 -3 MIPS 

Source: MIT, 1961




























Key Innovations in Semiconductors 




Once Upon a Time … 


April, 1961 first integrated circuit developed by 

Robert Noyce, from Fairchild Semiconductor







A Big Event … 

4004, 10 Microns, Intel 


1971 

10 -1 MIPS 

Source: 4004, Intel, 1971



A 10,000X Improvement, Thanks To… 

“A Computer Code Entitled SCALD […] Speeds the Job” 


Source: Lawrence Livermore National Laboratory, Newsline, January 10 th , 1979



1961-1981, A 10,000X Improvement… 

S-1 Supercomputer, ~3 Microns, LLNL 


1981 

10 MIPS 

Source: Lawrence Livermore National Laboratory, 1983

Time Flies Away … 

DEC Alpha 21064, 64bits, 750 nm CMOS, 200Mhz 


1991 

300 

DMIPS 

Source: Wikimedia Commons; Courtesy of A. Domic







Another Time Stamp … 

Itanium, 180 Nanometers, Intel 


2001 

~25 GOPS 

Source: Intel, 2001



1961-2011, A 100,000,000X Improvement… 

Ivy Bridge, 22 Nanometers, Intel 


2011 

100 GOPS 

~160mm 2 , 1.4B transistors, 2.5-4GHz, 45-80W 

Source: M. Bohr, Intel, IDF 2011; S. Siers, Intel, ISSCC 2012; Sandra 2011

The Wireless Side in 2011: 

ST AP9540 

• Application processor for 

smart phones and tablets 

– Dual ARM Cortex A9 

@ 1.85GHz 

– Imagination GPU SGX544 

@ 500MHz 

– Dual 32 bits LPDDR2 

@ 533MHz 

• 32nm technology 

– 10 metal layers 

• Advanced power 

management 

– 10+ switchable power 

domains with multivoltage/multi-supply 

scenarios 


Periph3 

Periph1 

DSS 

G1 

MCDE 

SGX544 

HVA 

DDR1 PHY 

SVA 

DDR 

CTRL1 

CSI 

MMDSP 

SIA 

MMDSP 

A9 

Periph2 

C2C 

DDR 

CTRL0 

DDR0 PHY

Gordon E. Moore’s Law 

Twice the Number of Transistors for the Same Price, 

Every Two Years 

0.5 = ~0.7 

The Scaling Factor 

“The complexity for minimum component 

costs has increased at a rate of roughly a 

factor of two per year ... Certainly over 

the short term this rate can be expected to 

continue, if not to increase. Over the 

longer term, the rate of increase is a bit 

more uncertain, although there is no 

reason to believe it will not remain nearly 

constant for at least 10 years.” Gordon E. 

Moore, Electronic Magazine, April 19 th , 

1965 


Area = 0.5 

Area = 1

Ley de Moore 

LOG2 OF THE NUMBER OF 

COMPONENTS PER INTEGRATED FUNCTION 


16 

15 

14 

13 

12 

11 

10 

9 

8 

7 

6 

5 

4 

3 

2 

1 

0 

1959 

1960 

1961 

1962 

1963 

1964 

1965 

1966 

1967 

1968 

1969 

1970 

1971 

1972 

1973 

1974 

1975 

http://download.intel.com/museum/Moores_Law/Articles- 

Press_releases/Gordon_Moore_1965_Article.pdf 

Fuente: Electronics, 19 Abril, 1965

Wafer 1” – 1959 


Wafer 300 mm 


Proyecciones para el 2000 en 1975 


Moore no siempre tuvo 

razón

Design - Layout 


EDA Back Then… 

CALMAGRAPHIC, Calma 


Source: D.E. Weisberg, The Engineering Design Revolution, 2008 (www.cadhistory.net)



1970 – From Manual Layout to Manufacturing 

Digitizing 

Table/Tablet 

• Applicon- PCB & IC Digitizing, CAM* 

• ComputerVision- Wiring, Mapping, Documentation, PCB 

• David Mann output for IC masks 

• Gerber for PCB artwork 

• Autotrol for digitizing 

* Computer Aided Manufacturing 


Keyboard, Tablet 

and CRT 

Mainframe-500 lbs 

128k; 8-16 bit 

The Age of 

the Gods 

SENSES 

33 MB Disk 

Plotter 

Mag Tape-Output 

Photo-Mask Generation



Basic Early CAD Applications 

Gridded 

Pencil IC/PCB 

Layouts 


Primitive 

Database 

Artwork 

for 

Manufacturing 

Schematic Card Deck from 

Simulation 

Keypunch 

01110010 

00011001 

10010110 

00011001 

01110010 

Analog

Standard Cells & Channel Routing 


Source: GE Avionics, 1968

Technology Or… Art? 


Source: Intel & MoMA, 1974

Design - Synthesis 






Design - Fab 


Design - Fab 


Design - Verification 






The Key Components of Modern EDA 

1980s 

Mead & 

Conway 


VHDL & 

Verilog 

DRC 

& LVS 

Dracula 

BBL & 

Timberwolf 

Logic 

Synthesis 

Framework 

Hardware 

Emulation 

Podem X 

Scan Test 

BDD 

Flex 

Cathedral 

Ptolemy 

Interconnect 

modeling

Some Key Contributors to EDA 

Commercial 

Industry 

High-Level 

Design 


DRC/LVS 

System, 

Layout 

Verilog 

Place & 

Route 

Multi 

Discipline 

Innovators 

Logic 

Synthesis



Design Process 

Verify: verify the correctness of 

design and implementation 


Design: specify and enter the 

design intent 

Implement: refine the design 

through all phases

Bottom – up / Top – down 

• Bottom – up 

– Start from simple modules 

– Goes to complex modules 

– Suitable to create small parts that will be reused 

• Top – down 

– Start from complex modules 

– Goes to simple modules 

– Suitable for big systems 


Bottom – up / Top – down 

Bottom – up 


Complex system 

Module (one function) 

Register and gates 

Transistors 

Top – down

IC Design . . . A Simplified Explanation 

process begin 

wait until not 

CLOCK'stable 

and CLOCK=1; 

if(ENABLE='1') then 

TOGGLE

The Front End 

Architecture: 

• Key Algorithms (filtering, for example) 

• Amount of on-chip Memories, sizes? 

• How many Integer Proc Units? 

RTL: Register Transfer Language 

• Verilog (1988), VHDL, SystemVerilog: an executable spec 

for the chip, amounting to over a million lines of code 

• Lots of simulations to verify the spec (literally billions of 

cycles) 

• Timing constraints, clock definitions, etc 


The Front End 

Logic Design: convert the RTL to logic gates 

(NAND-NORs, NOTs, Registers) 

• A manual process in the past, still mostly manual for Analog 

• Logic Synthesis (1989): automate the process 

• Many discrete optimization techniques used here: boolean 

minimization, static timing analysis, state equivalence, etc, 

etc. 

• End point is a “netlist”, meaning a set of logic gates and their 

connections. A large netlist is in the 10s of millions of gates 

• Can be simulated or “formally verified” versus the RTL. 

• Key technique: how do you prove that two logic equations 

are equivalent? 


The Back End 

Floorplanning 

• Where do we place the large blocks? Where do we place 

the “random” logic and “structured blocks”? A 

combination of manual and automated approaches is 

used 

• Need to keep connections short to meet timing, but also 

cannot “congest” the design too much or we cannot 

complete the connections 

• Note that connections do have R and C (to substrate and 

coupling between wires) so they introduce delay! Meeting 

timing can be very difficult! 

• The Power and Ground lines usually get decided here 


The Back End 

Placement: 

• Now we need to complete the exact details of 

where each block and gate will be 

• Automation has been a key for many years 

(1980). A block may contain hundreds of 

thousands of cells, so it is very hard problem: 

minimize area, be routable and meet timing 

• Note may have to add logic: repeaters to 

restore signals a key example 


The Back End 

Routing 

• Complete all the connections! 

• But, need to meet timing and keep signal integrity. This also 

involve separating some wires, for example, to avoid bad 

couplings 

• Automation is the norm here (1980) 

Verification: 

• Spacing and sizing rules are checked for all polygons (1980) 

• Parasitics are extracted, netlists back annotated and time 

analyzed using static techniques (1990) 

• Manufacturing requires complicated rules, such as wire density 

been “uniform” 


Design Goes to Fabrication 


Sounds simple, but have a host of 

very hard problems to solve!

Fabrication 

Mask fabrication 

Wafer fabrication 

Wafer testing 

Assembly and packaging 

IC test 


What’s a design flow? 

System 

Analysis 

System Studio 

Logic Modeling 

VERA 

Testbench 

VCS-MX 

Blah blah blah 

yada 

Blah 

yada 

blah blah 

Blah blah 

yada 

blah 

Blah 

yada 

yidie blah blah 

Blah 

yadie 

blah 

yada 

blah 

So on and yada 

yidie 

so 

Blah 

yadie 

forth 

blah blah 

So 

on 

on 

and 

and 

on 

yidie 

so 

yadie 

forth 

Jibber jabber 

So 

on 

on 

and 

jibber 

and 

on 

so forth 

Jibber 

just jawing 

jabber 

on and 

jibber 

Yackety on 

Jibber 

just 

yack 

jawing 

Ya'll com jabber jibber 

Yackety 

back 

just 

yack 

jawing 

Ya'll com 

Yackety 

back 

yack 

Ya'll com back 

VCS-MX 

Magellan 

Formality 

PrimeTime 

PrimePower 

Post-Route 

Verification 

PrimeTime 

NanoSim 

HSPICE 



yada 

Blah 

yada 

blah blah 

Blah blah 

yada 

blah 

Blah 

yada 


Blah 

yadie 

blah 

yada 

blah 


yidie 

so 

Blah 

yadie 

forth 

blah blah 

So 

on 

on 

and 

and 

on 

yidie 

so 

yadie 

forth 

Jibber jabber 

So 

on 

on 

and 

jibber 

and 

on 

so forth 

Jibber 

just jawing 

jabber 

on and 

jibber 

Yackety on 

Jibber 

just 

yack 

jawing 


Yackety 

back 

just 

yack 

jawing 

Ya'll com 

Yackety 

back 

yack 


Select 

Architecture 


ATPG 

TetraMAX 

Gate-level 

verification 

Specification 

Module Compiler 

RTL Gates 

Physical Compiler 

JupiterXT 

STAR-RCXT 

Hercules 

Synthesis 

Design Planning 

Gate-level 

netlist 

Place & Route 


Checks 

…the steps you take to design a chip! 

Scripts 

Initial constraints 


yada 

Blah 

yada 

blah blah 

Blah blah 

yada 

blah 

Blah 

yada 


Blah 

yadie 

blah 

yada 

blah 


yidie 

so 

Blah 

yadie 

forth 

blah blah 

So 

on 

on 

and 

and 

on 

yidie 

so 

yadie 

forth 

Jibber jabber 

So 

on 

on 

and 

jibber 

and 

on 

so forth 

Jibber 

just jawing 

jabber 

on and 

jibber 

Yackety on 

Jibber 

just 

yack 

jawing 


Yackety 

back 

just 

yack 

jawing 

Ya'll com 

Yackety 

back 

yack 


Design Compiler 

Power Compiler 

DFT Compiler 


Constraints 


Astro 

Technology 

Process 

Models / IP 

Proteus 

Physical Data 

Creation 

Library Compiler 

DesignWare Library 

Links-to- 

Layout 


yada 

Blah 

yada 

blah blah 

Blah blah 

yada 

blah 

Blah 

yada 


Blah 

yadie 

blah 

yada 

blah 


yidie 

so 

Blah 

yadie 

forth 

blah blah 

So 

on 

on 

and 

and 

on 

yidie 

so 

yadie 

forth 

Jibber jabber 

So 

on 

on 

and 

jibber 

and 

on 

so forth 

Jibber 

just jawing 

jabber 

on and 

jibber 

Yackety on 

Jibber 

just 

yack 

jawing 


Yackety 

back 

just 

yack 

jawing 

Ya'll com 

Yackety 

back 

yack 


Mask Writer 

GDSII 

CATS

Design Implementation 

System 

Analysis 

System Studio 

Logic Modeling 

VERA 

Testbench 


yada 

Blah 

yada 

blah blah 

Blah blah 

yada 

blah 

Blah 

yada 


Blah 

yadie 

blah 

yada 

blah 


yidie 

so 

Blah 

yadie 

forth 

blah blah 

So 

on 

on 

and 

and 

on 

yidie 

so 

yadie 

forth 

Jibber jabber 

So 

on 

on 

and 

jibber 

and 

on 

so forth 

Jibber 

just jawing 

jabber 

on and 

jibber 

Yackety on 

Jibber 

just 

yack 

jawing 


Yackety 

back 

just 

yack 

jawing 

Ya'll com 

Yackety 

back 

yack 


VCS-MX 

Verification 

VCS-MX 

Magellan 

Formality 

PrimeTime 

PrimePower 

Post-Route 

Verification 

PrimeTime 

NanoSim 

HSPICE 



yada 

Blah 

yada 

blah blah 

Blah blah 

yada 

blah 

Blah 

yada 


Blah 

yadie 

blah 

yada 

blah 


yidie 

so 

Blah 

yadie 

forth 

blah blah 

So 

on 

on 

and 

and 

on 

yidie 

so 

yadie 

forth 

Jibber jabber 

So 

on 

on 

and 

jibber 

and 

on 

so forth 

Jibber 

just jawing 

jabber 

on and 

jibber 

Yackety on 

Jibber 

just 

yack 

jawing 


Yackety 

back 

just 

yack 

jawing 

Ya'll com 

Yackety 

back 

yack 


Select 

Architecture 


ATPG 

TetraMAX 

Gate-level 

verification 

Specification 

Module Compiler 

RTL Gates 


JupiterXT 

STAR-RCXT 

Hercules 

Synthesis 

Design Planning 

Gate-level 

netlist 

Place & Route 


Checks 

Scripts 

Initial constraints 


yada 

Blah 

yada 

blah blah 

Blah blah 

yada 

blah 

Blah 

yada 


Blah 

yadie 

blah 

yada 

blah 


yidie 

so 

Blah 

yadie 

forth 

blah blah 

So 

on 

on 

and 

and 

on 

yidie 

so 

yadie 

forth 

Jibber jabber 

So 

on 

on 

and 

jibber 

and 

on 

so forth 

Jibber 

just jawing 

jabber 

on and 

jibber 

Yackety on 

Jibber 

just 

yack 

jawing 


Yackety 

back 

just 

yack 

jawing 

Ya'll com 

Yackety 

back 

yack 



Power Compiler 

DFT Compiler 


Constraints 


Astro 

Technology 

Process 

Models / IP 

Proteus 

Physical Data 

Creation 

Library Compiler 

DesignWare Library 

Links-to- 

Layout 

Design for Manufacturing 


yada 

Blah 

yada 

blah blah 

Blah blah 

yada 

blah 

Blah 

yada 


Blah 

yadie 

blah 

yada 

blah 


yidie 

so 

Blah 

yadie 

forth 

blah blah 

So 

on 

on 

and 

and 

on 

yidie 

so 

yadie 

forth 

Jibber jabber 

So 

on 

on 

and 

jibber 

and 

on 

so forth 

Jibber 

just jawing 

jabber 

on and 

jibber 

Yackety on 

Jibber 

just 

yack 

jawing 


Yackety 

back 

just 

yack 

jawing 

Ya'll com 

Yackety 

back 

yack 


Mask Writer 

GDSII 

CATS

Systems 

SoC 

Silicon 


System Design 

Verification IP 

Implementation 

Manufacturing

Classic IC Design Flow 


Architectural choices, RTL compilation and simulation 

(VCS) 

Logic synthesis (Design Compiler) 

Formal verification (Formality) 

Generation of test patterns (TetraMAX) 

Physical design (IC Compiler) 

Physical verification (Hercules) 

Layout parasitics extraction (StarRC) 

SPICE level simulation of completed design (HSPICE)


Architectural choices, RTL Compilation and Simulation 

(VCS) 


VCS Overview 

VCS supports multiple languages 

• Verilog 

• VHDL 

• C/C++ 

• SystemC 

• SystemVerilog 

• OpenVera 

• Analog 

Intuitive GUI help find bugs quickly 

• Assertions 

• Testbench 

• Coverage 

• Post-simulation analysis 


VCS Features 

The most used features 

are: 

• Tracing the Cause of Failed 

Assertion 

• Trace drivers and loads of a 

signal at any time to see the 

drivers and loads that caused a 

value change and see all the 

drivers/loads that possibly 

contributed to a signal value. 

RTL and Gate Signal 

Comparison 

Highlighting the net in gatelevel 

schematic and Verilog 



Logic Synthesis 

(Design Compiler) 


Introduction to Design Compiler 

Design Compiler performs logic synthesis and 

optimization of design 

• Synthesizes HDL designs into optimized technologydependent 

gate-level designs. 

• Results in smallest and fastest logical representation of a 

given function 

• Design Compiler supports a wide range of flat and 

hierarchical design styles 

• Combinational and sequential designs can be optimized for 

• timing 

• area 

• power 


DC and Design Flow 


Constraints 

IP DesignWare 

Library 

Technology 

Library 

Symbol Library 

SDF 

PDEF 

Timing 

optimization 

Area 

optimization 

Back-annotation 

HDL 

Datapath 

optimization 

Test 

synthesis 

Optimized 

gate-level netlist 

Place & route 


Power 

optimization 

Timing 

closure 

Timing & power 

analysis 

Formal verification

Basic Synthesis Flow 

Design rule constraints 

set_max_transition 

set_max_fanout 

set_max_capacitance 

compile 

write 


Develop HDL files 

Specify libraries 

Read design 

Define design environment 

Set design constraints 

Optimize the design 

Analyze and resolve design 

problems 

Save the design database 

Design optimization constraints 

create_clock 

set_clock_latency 

set_propagated_clock 

set_clock_uncertaintly 

set_clock_transition 

set_input_delay 

set_output_delay 

set_max_area 

check_design 

report_area 

report_constraint 

report_timing

Design Compiler Input and Output Files 


Design source 

Code 

Verilog(.v ) 

VHDL (.vhd) 

Synthesis 

scripts (.tcl) 


constraints 

(.con, .sdc) 


Compiler 

Reports and logs 

(text formats) 

Design database 

(.db - Synopsys internal 

database format) 

Gate level Verilog description

Design for Test 

Synopsys' design-for-test (DFT) synthesis 

solution (DFT Compiler) – enables scan 

insertion within Design Compiler 

DFT Compiler's integration with Design 

Compiler ensures DFT with optimization of 

area, power, and timing constraints, and 

predictable timing closure of physically 

optimized scan designs. 


DFT Key Features 

One-pass test synthesis 

Comprehensive RTL and gate-level DFT design rule checking 

Rapid scan synthesis 

Adaptive scan technology 

Hierarchical scan synthesis 

Observe point insertion 

Automatic fixing of scan violations (autoFix) 

Location-based scan ordering 

Timing-based scan ordering 



Formal Verification 

(Formality) 


Formality Introduction 

Formality checks whether two designs are functionally equivalent or not 

Its purpose is to detect unexpected differences that may have been introduced into 

a design during development. 

Design level 1 Design level 2 

Design process 


Formality 

Equivalent 

Yes/No ?

Key Concepts 

Compare Point 

• Primary output of a circuit 

• Registers within a circuit 

• An input to black boxes within circuit 

Logic Cone 

• A block of combinational logic which 

drives a compare point 


Equivalence Checking Verification Process 

Equivalence checking is a four-phase 

process: 

• Reading and elaborating language 

descriptions into logical representations 

• Setting up prompt for verification 

• Mapping of corresponding compare points 

between pairs of designs (Matching) 

• Comparison of logic cones that drive the 

compare points (Verification) 


Input Files of Formality 

Formality supports the following input formats: 

Input formats Command 

Verilog (synthesizable subset) - read_verilog 

Verilog (simulation libraries) - read_verilog -vcs 

VHDL (synthesizable subset) - read_vhdl 

EDIF - read_edif 

Synopsys binary files - read_db, read_ddc, read_mdb (*) 


Formality Flow Overview 

Guidance (Loading of automated setup file) 

• The purpose of automated file (.svf) is to help Formality process design changes caused by other 

tools, which it should have access to as the changes are made. 

Referencing (Specifying the reference design) 

• The reference design is the design against which the transformed (implementation) design is 

compared. 

Implementation (Specifying the implementation design) 

• This is the changed design. It is the design correctness that needs to be verified. 

Matching (Matching compare points) 

• Process of aligning compare points between two designs. 

Verification (Verify the Designs) 

• Process of proving or disproving that compare points are equivalent (have same functionality). 

Debug 

• During debug the user should determined where and why the comparison results were 

unsuccessful. 



Generation of Test Patterns 

(TetraMAX) 


Introduction 

TetraMAX is a high-speed, high-capacity automatic test 

pattern generation (ATPG) tool. 

It can generate test patterns that maximize test 

coverage while using a minimum number of test vectors 

for a wide variety of design types and design flows. 

It is well suited for designs of all sizes up to millions of 

gates. 


ATPG Modes 

Basic-Scan ATPG, an efficient combinationalonly 

mode for full-scan designs 

Fast-Sequential ATPG for limited support of 

partial-scan designs 

Full-Sequential ATPG for maximum test 

coverage in partial-scan designs. 


Design Flow Using DFT Compiler and 

TetraMAX 

STIL test protocol 

file 

Verilog library 


HDL netlist 

Design for test 

Writing test protocol 


TetraMAX ATPG 

Compiled, 

scanned netlist

TetraMAX Design Flow 


Models 

Netlist 

Pre-process netlist 

Read netlist 

Read Library 

Build the model 

Perform test design rule 

checking(DRC) 

Prepare to run ATPG 

Run ATPG 

Review test coverage 

Re-run ATPG 

Save test patterns 

Test protocol 

STL test protocol file

Steps of Running TetraMAX 

Reading the netlist 

Reading Verilog library models 

Building the ATPG model 

Performing Test Design Rule Checking (Test DRC) 

Generating test protocols 


Test Design Rule Checking 

Test DRC checks for the following conditions: 

Whether the scan chains inputs and outputs are logically connected 

Whether all the clocks and asynchronous set/reset pins connected to scan 

chain flip-flops are controlled only by primary input ports 

Whether the clocks/sets/resets are off when you switch from normal mode 

to scan shift mode and again when you switch back to normal mode 

Whether any internal multiple-driver nets can be in contention 



Static Timing Analysis of Test Patterns 

(PrimeTime) 


Introduction 

PrimeTime is a full-chip, gate-level static timing 

analysis tool that is an essential part of the 

design and analysis flow for today's large chip 

designs. 

PrimeTime validates the timing performance of 

a design by checking all possible paths for 

timing violations, without using logic simulation 

or test vectors. 


PrimeTime Inputs and Outputs 

Parasitics 

Initial timing 

reports 


SDF 

Gate-level 

netlist 

PrimeTime 

Restore session in 

PrimeTime for further 

debugging 

Libraries 


Constraints 

Saved 

session

Using PrimeTime in Physical Synthesis 

Flow 

RTL 

description 

Synthesis 

Gate-level 

description 

Place & Route 

Chip layout 

description 

Design sign-off 


Timing constraints for 

resynthesis and logic 

optimization 

.lcctcl, .sdc 

Design data 

.db, Verilog, VHDL 

Path constraints 

.sdf 

Delay data; detailed 

parasitic data for 

back-annotation 

.sdf; RSPF, DSPF, SPEF, SBPF 

Technology 

library 

PrimeTime 

(Static Timing Analysis) 

Timing 

models 

.db 

Cell delays, transition 

times, capacitance, 

wire load models, 

design rules, 

operating conditions 

.tcl 

.sdc 

.pt 

.db, interface logic 

models, extracted 

timing models 

Command-specified 

conditions



(IC Compiler) 


Input and Output Files of IC Compiler 

Netlist 

(.v, .ddc) 

Cell Library .db 

(.db) 

TluPlus, 

.map 

Tech file 

.tf .tf 

Milkyway Ref 

library 


IC Compiler 

Verilog 

(.v) 

GDSII 

(.gds) 

Standard 

Parasitics 

Exchange 

Format 

(.spef)

IC Compiler Design Flow 


Invoke ICC 

Data preparation 

Floorplanning 

Power Planning 

Placement 

Clock Tree Synthesis 

Routing 

Finishing 

Results (.v, .gds, .spef)

Physical Design Steps (1) 

Data preparation 

• Milkyway design library creation, logic libraries setup and parasitic 

models setup, design import. 

Floorplanning 

• Setting up the core area, top-level ports, and placement sites. 

Power Planning 

• Rectangular rings creation, power straps creation, etc. 

Core Placement and Optimization 

• During the placement phase the design's standard cells will be 

automatically placed in horizontal placement rows. 

• Allows following optimizations: power, optimize_dft, effort, etc 


Physical Design Steps (2) 

Core Clock Tree Synthesis and Optimization 

• During clock tree synthesis, IC Compiler builds clock trees that meet the clock tree 

design rule constraints while balancing the loads and minimizing the clock skew. 

Allows the following options: area_recovery, power, optimize_dft, only_cts, etc. 

Core Routing and Optimization 

• This command performs simultaneous routing and postroute optimization on the 

current design. Allows following optimizations: power, size_only, stage, 

only_hold_time, only_design_rule etc. 

Check DRC (Design Rule Checking) and LVS (layout vs. schematic) 

Export the design 

• Allows following formats: Verilog ,GDS format etc. 



Physical Verification 

(Hercules) 


Introduction 

Hercules is a hierarchical 

physical verification tool 

that performs design rule 

checking (DRC) and layout 

vs. schematic (LVS) on IC 

design. 


Input Files of Hercules 

Hercules uses several input files to perform 

DRC, LVS, LPE and ERC design verification. 

These input files are: 

• Database 

• Runset file 

• Schematic netlist 

The primary input file is the runset file. 


Design Database 

In the beginning of a Hercules run, primary group 

files are created that consist of one file per layer 

listed in the ASSIGN section of the runset file. 

Read different design databases using: 

• GDSII 

• GDSOUT 

• OASIS 

• Milkyway 


Runset File 

Runset file is a control file that instructs 

Hercules where to find input data, which checks 

to perform and where to write output files. 

Separate runsets are typically created for DRC 

and LVS. 

• A DRC Runset instructs Hercules to check layout files for 

errors. 

• A LVS Runset instructs Hercules to compare the layout 

netlist to the schematic netlist of a design. 


Schematic Netlist 

The schematic Netlist file is used during LVS comparison. 

It provides complete net information with each cell. 

If schematic netlist is in CDL, NetTran will translate it to 

Hercules format. 

nettran –verilog Johnson_count.v –cdl-a-cdl-s-sp-S-verilog-b1 VDD –verilog-b0 VSS\ 

-rootCell Johnson_count –sp ./saed90nm.cdl –outName Johnson_count.sp 


7/14/10 

Netlist Translation 

Hercules uses the NetTran utility to translate the netlist 

between different formats. 

(e.g. Verilog to SPICE, SPICE to Hercules netlist format) 


INPUT 

OUTPUT 

Hercules 

SPICE SPICE 

CDL Netlist 

Verilog 

Verilog NetTran NetTran EDIF 

EDIF EDIF3 

EDIF3 Hercules 

(default) 

Hercules 

Silos

DRC Flow 


Physical 

database 

Hercules 

(DRC run) 

Output Summary files 

(Error database) 

Input DRC Runset 

runset.ev

LVS Flow 


Physical 

database 

Hercules 

(LVSrun) 

Output Summary files 

(Error database) 

Input LVS Runset 

runset.ev


Layout Parasitics Extraction 

(StarRC) 


StarRC Overview 

StarRC is a layout parasitic extraction tool. StarRC can be used at any 

physical design cycle stage to extract accurate parasitics. 

StarRC reads OpenAccess, Milkyway, LEF/DEF or Hercules connected 

databases directly, without external processing. 

Extracted parasitics can be written into the Synopsys centralized Milkyway 

database for use by analysis and optimization tools. 

Because StarRC gracefully handles designs with layout versus schematic 

(LVS) violations, including opens and shorts, timing convergence can be 

ensured before the physical verification cycle begins. 


Inputs and Outputs of StarRC 

TCAD_GRD_FILE 

saed90nm_9lm.nxtgrd 

MAPPING_FILE 

tech2itf.map 

star_cmd 

rcx_cmd 

• TCAD_GRD_FILE -File containing the modeled layers of a circuit. 

• MAPPING_FILE-File containing physical layer mapping information between the 

input database and the specified TCAD_GRD_FILE 

• star_cmd -ASCII file containing StarRC commands that controls extraction functions 


StarRC 

.spf

Input and Output Formats of StarRC 

StarRC supports these industry-standard formats: 

Input formats 

• LEF(Layout Exchange Format)/DEF(Design Exchange Format) 

• GDSII 

• Milkyway 

Output Netlist Formats 

• SPICE 

• Synopsys Binary Parasitic Format (SBPF) 

• Standard Parasitic Exchange Format (SPEF) 

• Detailed Standard Parasitic Format (DSPF) 

StarRC accepts input from GDSII, LEF/DEF, and IC Compiler formats. 


StarRC Extraction Flow 

StarRC Command File 

Technology data 

(layer physical information) 

*.nxtgrd 

Mapping file (used to map 

layers used in StarRC to 

technology layers) 


Milkyway 

database 

OR 

Physical Database 

GDSII 

StarRC 

Parasitic Netlist 

Schematic 

Netlist


SPICE-level Simulation of Completed Design 

(HSPICE) 


HSPICE Features 

HSPICE supports: 

• Analog/RF/mixed-signal IC Design 

• Verilog-A Behavioral Modeling 

• Design For Yield- Process Variability 

and MosRa Device Reliability Analysis 

• Transient Noise Analysis 

• Cell and Memory Characterization 


Input and Output Files of HSPICE 

Netlist 

Measure 

Analyze type 

Options 

Model file 


HSPICE 

Waveforms 

(*.tr) 

Measurement Results 

(*.mt)



Architectural choices, RTL compilation and simulation 

(VCS) 

Logic synthesis (Design Compiler) 

Formal verification (Formality) 

Generation of test patterns (TetraMAX) 

Physical design (IC Compiler) 

Physical Verification (Hercules) 

Layout Parasitics Extraction (StarRC) 

SPICE-level simulation of completed design (HSPICE)


Thank You

Synopsys Design Flow

Create successful ePaper yourself

Delete template?

Save as template?