- Page 1 and 2: © Synopsys 2012 1 Digital IC Desig
- Page 3 and 4: Introduction © Synopsys 2012 3
- Page 5 and 6: © Synopsys 2012 5 Mobile 100 15 12
- Page 7 and 8: Smart Everything Grid Buildings Car
- Page 9 and 10: Drivers of Innovation and Different
- Page 11 and 12: Advanced Designs and Tapeouts Sourc
- Page 13 and 14: Leading the Way at 22/20nm Design S
- Page 15 and 16: Advanced Design Trends 100% 75% 50%
- Page 17 and 18: Clock Frequency Trends 100% 80% 60%
- Page 19 and 20: $M Hardware/Software Development Co
- Page 21 and 22: Key Innovations in Electronics: Aud
- Page 23 and 24: Key Innovations in Electronics: Aud
- Page 25 and 26: Key Innovations in Electronics: Aud
- Page 27 and 28: Key Innovations in Electronics: Aud
- Page 29 and 30: Key Innovations in Electronics: Aud
- Page 31 and 32: Key Innovations in Electronics: Aud
- Page 33 and 34: Key Innovations in Electronics: Com
- Page 35 and 36: Key Innovations in Electronics: Com
- Page 37 and 38: Key Innovations in Electronics: Com
- Page 39 and 40: Key Innovations in Electronics: Com
- Page 41: Key Innovations in Electronics: Com
- Page 45 and 46: Key Innovations in Semiconductors
- Page 47 and 48: Key Innovations in Semiconductors
- Page 49 and 50: Key Innovations in Semiconductors
- Page 51 and 52: Key Innovations in Semiconductors
- Page 53 and 54: Key Innovations in Semiconductors
- Page 55 and 56: Time Flies Away … DEC Alpha 21064
- Page 57 and 58: Key Innovations in Semiconductors
- Page 59 and 60: Another Time Stamp … Itanium, 180
- Page 61 and 62: 1961-2011, A 100,000,000X Improveme
- Page 63 and 64: Gordon E. Moore’s Law Twice the N
- Page 65 and 66: Wafer 1” - 1959 © Synopsys 2012
- Page 67 and 68: Proyecciones para el 2000 en 1975
- Page 69 and 70: EDA Back Then… CALMAGRAPHIC, Calm
- Page 71 and 72: 1970 - From Manual Layout to Manufa
- Page 73 and 74: Basic Early CAD Applications Gridde
- Page 75 and 76: Technology Or… Art? © Synopsys 2
- Page 77 and 78: Design - Synthesis © Synopsys 2012
- Page 79 and 80: Design - Fab © Synopsys 2012 79
- Page 81 and 82: Design - Verification © Synopsys 2
- Page 83 and 84: Design - Verification © Synopsys 2
- Page 85 and 86: Some Key Contributors to EDA Commer
- Page 87 and 88: Design Process Verify: verify the c
- Page 89 and 90: Bottom - up / Top - down Bottom - u
- Page 91 and 92: The Front End Architecture: • Key
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The Back End Floorplanning • Wher
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The Back End Routing • Complete a
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Fabrication Mask fabrication Wafer
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Design Implementation System Analys
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Classic IC Design Flow © Synopsys
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VCS Overview VCS supports multiple
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Synopsys Design Flow Logic Synthesi
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DC and Design Flow © Synopsys 2012
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Design Compiler Input and Output Fi
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DFT Key Features One-pass test synt
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Formality Introduction Formality ch
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Equivalence Checking Verification P
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Formality Flow Overview Guidance (L
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Introduction TetraMAX is a high-spe
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Design Flow Using DFT Compiler and
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Steps of Running TetraMAX Reading t
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Synopsys Design Flow Static Timing
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PrimeTime Inputs and Outputs Parasi
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Synopsys Design Flow Physical Desig
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IC Compiler Design Flow © Synopsys
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Physical Design Steps (2) Core Cloc
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Introduction Hercules is a hierarch
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Design Database In the beginning of
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Schematic Netlist The schematic Net
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DRC Flow © Synopsys 2012 141 Physi
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Synopsys Design Flow Layout Parasit
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Inputs and Outputs of StarRC TCAD_G
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StarRC Extraction Flow StarRC Comma
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HSPICE Features HSPICE supports:
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Synopsys Design Flow © Synopsys 20