Synopsys Design Flow

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The Front End Logic Design: convert the RTL to logic gates (NAND-NORs, NOTs, Registers) • A manual process in the past, still mostly manual for Analog • Logic Synthesis (1989): automate the process • Many discrete optimization techniques used here: boolean minimization, static timing analysis, state equivalence, etc, etc. • End point is a “netlist”, meaning a set of logic gates and their connections. A large netlist is in the 10s of millions of gates • Can be simulated or “formally verified” versus the RTL. • Key technique: how do you prove that two logic equations are equivalent? © Synopsys 2012 92
The Back End Floorplanning • Where do we place the large blocks? Where do we place the “random” logic and “structured blocks”? A combination of manual and automated approaches is used • Need to keep connections short to meet timing, but also cannot “congest” the design too much or we cannot complete the connections • Note that connections do have R and C (to substrate and coupling between wires) so they introduce delay! Meeting timing can be very difficult! • The Power and Ground lines usually get decided here © Synopsys 2012 93
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© Synopsys 2012 1 Digital IC Desig
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Introduction © Synopsys 2012 3
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© Synopsys 2012 5 Mobile 100 15 12
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Smart Everything Grid Buildings Car
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Drivers of Innovation and Different
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Advanced Designs and Tapeouts Sourc
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Leading the Way at 22/20nm Design S
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Advanced Design Trends 100% 75% 50%
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Clock Frequency Trends 100% 80% 60%
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$M Hardware/Software Development Co
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Page 61 and 62: 1961-2011, A 100,000,000X Improveme
Page 63 and 64: Gordon E. Moore’s Law Twice the N
Page 65 and 66: Wafer 1” - 1959 © Synopsys 2012
Page 67 and 68: Proyecciones para el 2000 en 1975
Page 69 and 70: EDA Back Then… CALMAGRAPHIC, Calm
Page 71 and 72: 1970 - From Manual Layout to Manufa
Page 73 and 74: Basic Early CAD Applications Gridde
Page 75 and 76: Technology Or… Art? © Synopsys 2
Page 77 and 78: Design - Synthesis © Synopsys 2012
Page 79 and 80: Design - Fab © Synopsys 2012 79
Page 81 and 82: Design - Verification © Synopsys 2
Page 83 and 84: Design - Verification © Synopsys 2
Page 85 and 86: Some Key Contributors to EDA Commer
Page 87 and 88: Design Process Verify: verify the c
Page 89 and 90: Bottom - up / Top - down Bottom - u
Page 91: The Front End Architecture: • Key
Page 95 and 96: The Back End Routing • Complete a
Page 97 and 98: Fabrication Mask fabrication Wafer
Page 99 and 100: Design Implementation System Analys
Page 101 and 102: Classic IC Design Flow © Synopsys
Page 103 and 104: VCS Overview VCS supports multiple
Page 105 and 106: Synopsys Design Flow Logic Synthesi
Page 107 and 108: DC and Design Flow © Synopsys 2012
Page 109 and 110: Design Compiler Input and Output Fi
Page 111 and 112: DFT Key Features One-pass test synt
Page 113 and 114: Formality Introduction Formality ch
Page 115 and 116: Equivalence Checking Verification P
Page 117 and 118: Formality Flow Overview Guidance (L
Page 119 and 120: Introduction TetraMAX is a high-spe
Page 121 and 122: Design Flow Using DFT Compiler and
Page 123 and 124: Steps of Running TetraMAX Reading t
Page 125 and 126: Synopsys Design Flow Static Timing
Page 127 and 128: PrimeTime Inputs and Outputs Parasi
Page 129 and 130: Synopsys Design Flow Physical Desig
Page 131 and 132: IC Compiler Design Flow © Synopsys
Page 133 and 134: Physical Design Steps (2) Core Cloc
Page 135 and 136: Introduction Hercules is a hierarch
Page 137 and 138: Design Database In the beginning of
Page 139 and 140: Schematic Netlist The schematic Net
Page 141 and 142: DRC Flow © Synopsys 2012 141 Physi
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Synopsys Design Flow Layout Parasit
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Inputs and Outputs of StarRC TCAD_G
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StarRC Extraction Flow StarRC Comma
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HSPICE Features HSPICE supports:
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Synopsys Design Flow © Synopsys 20
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Synopsys Design Flow

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