Synopsys Design Flow

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Designs Are Growing More Complex 30% 20% 10% 0% 13% 28% © Synopsys 2012 18 12% 13% 13% 12% 6% 7% 9% 6% 9% 10% 6% 9% 5% 4% 1-100K 101-500K 501K-1M 1-2M 2-5M 5-10M 10-20M 20-50M 50-100M >100M Source: 2011 Synopsys Global User Survey Memory = 48% of Gate Count (on average) Logic Memory 7% 6% 16% 10%
$M Hardware/Software Development Costs $2.50 $2.00 $1.50 $1.00 $0.50 $- Source: IBS, Synopsys 1 3 5 7 9 11 13 15 17 19 21 23 25 27 Months © Synopsys 2012 19 Software Is Half of Time-to-Market App-Specific SW Low-Level SW OS Support Design Management Post-silicon Validation Masks Physical Design RTL Verification RTL Development Spec Development IP Qualification
Page 1 and 2: © Synopsys 2012 1 Digital IC Desig
Page 3 and 4: Introduction © Synopsys 2012 3
Page 5 and 6: © Synopsys 2012 5 Mobile 100 15 12
Page 7 and 8: Smart Everything Grid Buildings Car
Page 9 and 10: Drivers of Innovation and Different
Page 11 and 12: Advanced Designs and Tapeouts Sourc
Page 13 and 14: Leading the Way at 22/20nm Design S
Page 15 and 16: Advanced Design Trends 100% 75% 50%
Page 17: Clock Frequency Trends 100% 80% 60%
Page 21 and 22: Key Innovations in Electronics: Aud
Page 33 and 34: Key Innovations in Electronics: Com
Page 45 and 46: Key Innovations in Semiconductors
Page 55 and 56: Time Flies Away … DEC Alpha 21064
Page 59 and 60: Another Time Stamp … Itanium, 180
Page 61 and 62: 1961-2011, A 100,000,000X Improveme
Page 63 and 64: Gordon E. Moore’s Law Twice the N
Page 65 and 66: Wafer 1” - 1959 © Synopsys 2012
Page 67 and 68: Proyecciones para el 2000 en 1975
Page 69 and 70:
EDA Back Then… CALMAGRAPHIC, Calm
Page 71 and 72:
1970 - From Manual Layout to Manufa
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Basic Early CAD Applications Gridde
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Technology Or… Art? © Synopsys 2
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Design - Synthesis © Synopsys 2012
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Design - Fab © Synopsys 2012 79
Page 81 and 82:
Design - Verification © Synopsys 2
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Design - Verification © Synopsys 2
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Some Key Contributors to EDA Commer
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Design Process Verify: verify the c
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Bottom - up / Top - down Bottom - u
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The Front End Architecture: • Key
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The Back End Floorplanning • Wher
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The Back End Routing • Complete a
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Fabrication Mask fabrication Wafer
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Design Implementation System Analys
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Classic IC Design Flow © Synopsys
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VCS Overview VCS supports multiple
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Synopsys Design Flow Logic Synthesi
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DC and Design Flow © Synopsys 2012
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Design Compiler Input and Output Fi
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DFT Key Features One-pass test synt
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Formality Introduction Formality ch
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Equivalence Checking Verification P
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Formality Flow Overview Guidance (L
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Introduction TetraMAX is a high-spe
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Design Flow Using DFT Compiler and
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Steps of Running TetraMAX Reading t
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Synopsys Design Flow Static Timing
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PrimeTime Inputs and Outputs Parasi
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Synopsys Design Flow Physical Desig
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IC Compiler Design Flow © Synopsys
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Physical Design Steps (2) Core Cloc
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Introduction Hercules is a hierarch
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Design Database In the beginning of
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Schematic Netlist The schematic Net
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DRC Flow © Synopsys 2012 141 Physi
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Synopsys Design Flow Layout Parasit
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Inputs and Outputs of StarRC TCAD_G
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StarRC Extraction Flow StarRC Comma
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HSPICE Features HSPICE supports:
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Synopsys Design Flow © Synopsys 20
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