Synopsys Design Flow

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Leading the Way at 16/14nm Design Source: Synopsys Global Technical Services © Synopsys 2012 14 > 12 16/14nm Active Designs
Advanced Design Trends 100% 75% 50% 25% © Synopsys 2012 15 56% of Respondents Currently Designing at 45nm or Below 180nm 130nm 90nm 65/55nm 45/40nm 32/28nm ≥250nm 0% 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 Source: 2011 Synopsys Global User Survey
Page 1 and 2: © Synopsys 2012 1 Digital IC Desig
Page 3 and 4: Introduction © Synopsys 2012 3
Page 5 and 6: © Synopsys 2012 5 Mobile 100 15 12
Page 7 and 8: Smart Everything Grid Buildings Car
Page 9 and 10: Drivers of Innovation and Different
Page 11 and 12: Advanced Designs and Tapeouts Sourc
Page 13: Leading the Way at 22/20nm Design S
Page 17 and 18: Clock Frequency Trends 100% 80% 60%
Page 19 and 20: $M Hardware/Software Development Co
Page 21 and 22: Key Innovations in Electronics: Aud
Page 33 and 34: Key Innovations in Electronics: Com
Page 45 and 46: Key Innovations in Semiconductors
Page 55 and 56: Time Flies Away … DEC Alpha 21064
Page 59 and 60: Another Time Stamp … Itanium, 180
Page 61 and 62: 1961-2011, A 100,000,000X Improveme
Page 63 and 64: Gordon E. Moore’s Law Twice the N
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Wafer 1” - 1959 © Synopsys 2012
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Proyecciones para el 2000 en 1975
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EDA Back Then… CALMAGRAPHIC, Calm
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1970 - From Manual Layout to Manufa
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Basic Early CAD Applications Gridde
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Technology Or… Art? © Synopsys 2
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Design - Synthesis © Synopsys 2012
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Design - Fab © Synopsys 2012 79
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Design - Verification © Synopsys 2
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Design - Verification © Synopsys 2
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Some Key Contributors to EDA Commer
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Design Process Verify: verify the c
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Bottom - up / Top - down Bottom - u
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The Front End Architecture: • Key
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The Back End Floorplanning • Wher
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The Back End Routing • Complete a
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Fabrication Mask fabrication Wafer
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Design Implementation System Analys
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Classic IC Design Flow © Synopsys
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VCS Overview VCS supports multiple
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Synopsys Design Flow Logic Synthesi
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DC and Design Flow © Synopsys 2012
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Design Compiler Input and Output Fi
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DFT Key Features One-pass test synt
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Formality Introduction Formality ch
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Equivalence Checking Verification P
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Formality Flow Overview Guidance (L
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Introduction TetraMAX is a high-spe
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Design Flow Using DFT Compiler and
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Steps of Running TetraMAX Reading t
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Synopsys Design Flow Static Timing
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PrimeTime Inputs and Outputs Parasi
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Synopsys Design Flow Physical Desig
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IC Compiler Design Flow © Synopsys
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Physical Design Steps (2) Core Cloc
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Introduction Hercules is a hierarch
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Design Database In the beginning of
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Schematic Netlist The schematic Net
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DRC Flow © Synopsys 2012 141 Physi
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Synopsys Design Flow Layout Parasit
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Inputs and Outputs of StarRC TCAD_G
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StarRC Extraction Flow StarRC Comma
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HSPICE Features HSPICE supports:
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Synopsys Design Flow © Synopsys 20
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