Synopsys Design Flow

More documents

Recommendations

Info

Input Files of Hercules Hercules uses several input files to perform DRC, LVS, LPE and ERC design verification. These input files are: • Database • Runset file • Schematic netlist The primary input file is the runset file. © Synopsys 2012 136
Design Database In the beginning of a Hercules run, primary group files are created that consist of one file per layer listed in the ASSIGN section of the runset file. Read different design databases using: • GDSII • GDSOUT • OASIS • Milkyway © Synopsys 2012 137
Page 1 and 2:
© Synopsys 2012 1 Digital IC Desig
Page 3 and 4:
Introduction © Synopsys 2012 3
Page 5 and 6:
© Synopsys 2012 5 Mobile 100 15 12
Page 7 and 8:
Smart Everything Grid Buildings Car
Page 9 and 10:
Drivers of Innovation and Different
Page 11 and 12:
Advanced Designs and Tapeouts Sourc
Page 13 and 14:
Leading the Way at 22/20nm Design S
Page 15 and 16:
Advanced Design Trends 100% 75% 50%
Page 17 and 18:
Clock Frequency Trends 100% 80% 60%
Page 19 and 20:
$M Hardware/Software Development Co
Page 21 and 22:
Key Innovations in Electronics: Aud
Page 23 and 24:
Page 25 and 26:
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Key Innovations in Electronics: Com
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Key Innovations in Semiconductors
Page 47 and 48:
Page 49 and 50:
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Time Flies Away … DEC Alpha 21064
Page 57 and 58:
Page 59 and 60:
Another Time Stamp … Itanium, 180
Page 61 and 62:
1961-2011, A 100,000,000X Improveme
Page 63 and 64:
Gordon E. Moore’s Law Twice the N
Page 65 and 66:
Wafer 1” - 1959 © Synopsys 2012
Page 67 and 68:
Proyecciones para el 2000 en 1975
Page 69 and 70:
EDA Back Then… CALMAGRAPHIC, Calm
Page 71 and 72:
1970 - From Manual Layout to Manufa
Page 73 and 74:
Basic Early CAD Applications Gridde
Page 75 and 76:
Technology Or… Art? © Synopsys 2
Page 77 and 78:
Design - Synthesis © Synopsys 2012
Page 79 and 80:
Design - Fab © Synopsys 2012 79
Page 81 and 82:
Design - Verification © Synopsys 2
Page 83 and 84:
Design - Verification © Synopsys 2
Page 85 and 86: Some Key Contributors to EDA Commer
Page 87 and 88: Design Process Verify: verify the c
Page 89 and 90: Bottom - up / Top - down Bottom - u
Page 91 and 92: The Front End Architecture: • Key
Page 93 and 94: The Back End Floorplanning • Wher
Page 95 and 96: The Back End Routing • Complete a
Page 97 and 98: Fabrication Mask fabrication Wafer
Page 99 and 100: Design Implementation System Analys
Page 101 and 102: Classic IC Design Flow © Synopsys
Page 103 and 104: VCS Overview VCS supports multiple
Page 105 and 106: Synopsys Design Flow Logic Synthesi
Page 107 and 108: DC and Design Flow © Synopsys 2012
Page 109 and 110: Design Compiler Input and Output Fi
Page 111 and 112: DFT Key Features One-pass test synt
Page 113 and 114: Formality Introduction Formality ch
Page 115 and 116: Equivalence Checking Verification P
Page 117 and 118: Formality Flow Overview Guidance (L
Page 119 and 120: Introduction TetraMAX is a high-spe
Page 121 and 122: Design Flow Using DFT Compiler and
Page 123 and 124: Steps of Running TetraMAX Reading t
Page 125 and 126: Synopsys Design Flow Static Timing
Page 127 and 128: PrimeTime Inputs and Outputs Parasi
Page 129 and 130: Synopsys Design Flow Physical Desig
Page 131 and 132: IC Compiler Design Flow © Synopsys
Page 133 and 134: Physical Design Steps (2) Core Cloc
Page 135: Introduction Hercules is a hierarch
Page 139 and 140: Schematic Netlist The schematic Net
Page 141 and 142: DRC Flow © Synopsys 2012 141 Physi
Page 143 and 144: Synopsys Design Flow Layout Parasit
Page 145 and 146: Inputs and Outputs of StarRC TCAD_G
Page 147 and 148: StarRC Extraction Flow StarRC Comma
Page 149 and 150: HSPICE Features HSPICE supports:
Page 151 and 152: Synopsys Design Flow © Synopsys 20
show all

Synopsys Design Flow

Create successful ePaper yourself

Delete template?

Save as template?