Synopsys Design Flow
Synopsys Design Flow
Synopsys Design Flow
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VCS Features<br />
The most used features<br />
are:<br />
• Tracing the Cause of Failed<br />
Assertion<br />
• Trace drivers and loads of a<br />
signal at any time to see the<br />
drivers and loads that caused a<br />
value change and see all the<br />
drivers/loads that possibly<br />
contributed to a signal value.<br />
RTL and Gate Signal<br />
Comparison<br />
Highlighting the net in gatelevel<br />
schematic and Verilog<br />
© <strong>Synopsys</strong> 2012 104