Synopsys Design Flow

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What’s a design flow? System Analysis System Studio Logic Modeling VERA Testbench VCS-MX Blah blah blah yada Blah yada blah blah Blah blah yada blah Blah yada yidie blah blah Blah yadie blah yada blah So on and yada yidie so Blah yadie forth blah blah So on on and and on yidie so yadie forth Jibber jabber So on on and jibber and on so forth Jibber just jawing jabber on and jibber Yackety on Jibber just yack jawing Ya'll com jabber jibber Yackety back just yack jawing Ya'll com Yackety back yack Ya'll com back VCS-MX Magellan Formality PrimeTime PrimePower Post-Route Verification PrimeTime NanoSim HSPICE © Synopsys 2012 98 Blah blah blah yada Blah yada blah blah Blah blah yada blah Blah yada yidie blah blah Blah yadie blah yada blah So on and yada yidie so Blah yadie forth blah blah So on on and and on yidie so yadie forth Jibber jabber So on on and jibber and on so forth Jibber just jawing jabber on and jibber Yackety on Jibber just yack jawing Ya'll com jabber jibber Yackety back just yack jawing Ya'll com Yackety back yack Ya'll com back Select Architecture RTL Verification ATPG TetraMAX Gate-level verification Specification Module Compiler RTL Gates Physical Compiler JupiterXT STAR-RCXT Hercules Synthesis Design Planning Gate-level netlist Place & Route Physical Design Checks …the steps you take to design a chip! Scripts Initial constraints Blah blah blah yada Blah yada blah blah Blah blah yada blah Blah yada yidie blah blah Blah yadie blah yada blah So on and yada yidie so Blah yadie forth blah blah So on on and and on yidie so yadie forth Jibber jabber So on on and jibber and on so forth Jibber just jawing jabber on and jibber Yackety on Jibber just yack jawing Ya'll com jabber jibber Yackety back just yack jawing Ya'll com Yackety back yack Ya'll com back Design Compiler Power Compiler DFT Compiler Design Constraints Physical Compiler Astro Technology Process Models / IP Proteus Physical Data Creation Library Compiler DesignWare Library Links-to- Layout Blah blah blah yada Blah yada blah blah Blah blah yada blah Blah yada yidie blah blah Blah yadie blah yada blah So on and yada yidie so Blah yadie forth blah blah So on on and and on yidie so yadie forth Jibber jabber So on on and jibber and on so forth Jibber just jawing jabber on and jibber Yackety on Jibber just yack jawing Ya'll com jabber jibber Yackety back just yack jawing Ya'll com Yackety back yack Ya'll com back Mask Writer GDSII CATS
Design Implementation System Analysis System Studio Logic Modeling VERA Testbench Blah blah blah yada Blah yada blah blah Blah blah yada blah Blah yada yidie blah blah Blah yadie blah yada blah So on and yada yidie so Blah yadie forth blah blah So on on and and on yidie so yadie forth Jibber jabber So on on and jibber and on so forth Jibber just jawing jabber on and jibber Yackety on Jibber just yack jawing Ya'll com jabber jibber Yackety back just yack jawing Ya'll com Yackety back yack Ya'll com back VCS-MX Verification VCS-MX Magellan Formality PrimeTime PrimePower Post-Route Verification PrimeTime NanoSim HSPICE © Synopsys 2012 99 Blah blah blah yada Blah yada blah blah Blah blah yada blah Blah yada yidie blah blah Blah yadie blah yada blah So on and yada yidie so Blah yadie forth blah blah So on on and and on yidie so yadie forth Jibber jabber So on on and jibber and on so forth Jibber just jawing jabber on and jibber Yackety on Jibber just yack jawing Ya'll com jabber jibber Yackety back just yack jawing Ya'll com Yackety back yack Ya'll com back Select Architecture RTL Verification ATPG TetraMAX Gate-level verification Specification Module Compiler RTL Gates Physical Compiler JupiterXT STAR-RCXT Hercules Synthesis Design Planning Gate-level netlist Place & Route Physical Design Checks Scripts Initial constraints Blah blah blah yada Blah yada blah blah Blah blah yada blah Blah yada yidie blah blah Blah yadie blah yada blah So on and yada yidie so Blah yadie forth blah blah So on on and and on yidie so yadie forth Jibber jabber So on on and jibber and on so forth Jibber just jawing jabber on and jibber Yackety on Jibber just yack jawing Ya'll com jabber jibber Yackety back just yack jawing Ya'll com Yackety back yack Ya'll com back Design Compiler Power Compiler DFT Compiler Design Constraints Physical Compiler Astro Technology Process Models / IP Proteus Physical Data Creation Library Compiler DesignWare Library Links-to- Layout Design for Manufacturing Blah blah blah yada Blah yada blah blah Blah blah yada blah Blah yada yidie blah blah Blah yadie blah yada blah So on and yada yidie so Blah yadie forth blah blah So on on and and on yidie so yadie forth Jibber jabber So on on and jibber and on so forth Jibber just jawing jabber on and jibber Yackety on Jibber just yack jawing Ya'll com jabber jibber Yackety back just yack jawing Ya'll com Yackety back yack Ya'll com back Mask Writer GDSII CATS
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© Synopsys 2012 1 Digital IC Desig
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Introduction © Synopsys 2012 3
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© Synopsys 2012 5 Mobile 100 15 12
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Smart Everything Grid Buildings Car
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Drivers of Innovation and Different
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Advanced Designs and Tapeouts Sourc
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Leading the Way at 22/20nm Design S
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Advanced Design Trends 100% 75% 50%
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Clock Frequency Trends 100% 80% 60%
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$M Hardware/Software Development Co
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Key Innovations in Electronics: Aud
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Key Innovations in Electronics: Com
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Page 45 and 46:
Key Innovations in Semiconductors
Page 47 and 48: Key Innovations in Semiconductors
Page 55 and 56: Time Flies Away … DEC Alpha 21064
Page 59 and 60: Another Time Stamp … Itanium, 180
Page 61 and 62: 1961-2011, A 100,000,000X Improveme
Page 63 and 64: Gordon E. Moore’s Law Twice the N
Page 65 and 66: Wafer 1” - 1959 © Synopsys 2012
Page 67 and 68: Proyecciones para el 2000 en 1975
Page 69 and 70: EDA Back Then… CALMAGRAPHIC, Calm
Page 71 and 72: 1970 - From Manual Layout to Manufa
Page 73 and 74: Basic Early CAD Applications Gridde
Page 75 and 76: Technology Or… Art? © Synopsys 2
Page 77 and 78: Design - Synthesis © Synopsys 2012
Page 79 and 80: Design - Fab © Synopsys 2012 79
Page 81 and 82: Design - Verification © Synopsys 2
Page 83 and 84: Design - Verification © Synopsys 2
Page 85 and 86: Some Key Contributors to EDA Commer
Page 87 and 88: Design Process Verify: verify the c
Page 89 and 90: Bottom - up / Top - down Bottom - u
Page 91 and 92: The Front End Architecture: • Key
Page 93 and 94: The Back End Floorplanning • Wher
Page 95 and 96: The Back End Routing • Complete a
Page 97: Fabrication Mask fabrication Wafer
Page 101 and 102: Classic IC Design Flow © Synopsys
Page 103 and 104: VCS Overview VCS supports multiple
Page 105 and 106: Synopsys Design Flow Logic Synthesi
Page 107 and 108: DC and Design Flow © Synopsys 2012
Page 109 and 110: Design Compiler Input and Output Fi
Page 111 and 112: DFT Key Features One-pass test synt
Page 113 and 114: Formality Introduction Formality ch
Page 115 and 116: Equivalence Checking Verification P
Page 117 and 118: Formality Flow Overview Guidance (L
Page 119 and 120: Introduction TetraMAX is a high-spe
Page 121 and 122: Design Flow Using DFT Compiler and
Page 123 and 124: Steps of Running TetraMAX Reading t
Page 125 and 126: Synopsys Design Flow Static Timing
Page 127 and 128: PrimeTime Inputs and Outputs Parasi
Page 129 and 130: Synopsys Design Flow Physical Desig
Page 131 and 132: IC Compiler Design Flow © Synopsys
Page 133 and 134: Physical Design Steps (2) Core Cloc
Page 135 and 136: Introduction Hercules is a hierarch
Page 137 and 138: Design Database In the beginning of
Page 139 and 140: Schematic Netlist The schematic Net
Page 141 and 142: DRC Flow © Synopsys 2012 141 Physi
Page 143 and 144: Synopsys Design Flow Layout Parasit
Page 145 and 146: Inputs and Outputs of StarRC TCAD_G
Page 147 and 148: StarRC Extraction Flow StarRC Comma
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HSPICE Features HSPICE supports:
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Synopsys Design Flow © Synopsys 20
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Synopsys Design Flow

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