Synopsys Design Flow
Synopsys Design Flow
Synopsys Design Flow
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<strong>Design</strong> Compiler Input and Output Files<br />
© <strong>Synopsys</strong> 2012 109<br />
<strong>Design</strong> source<br />
Code<br />
Verilog(.v )<br />
VHDL (.vhd)<br />
Synthesis<br />
scripts (.tcl)<br />
<strong>Design</strong><br />
constraints<br />
(.con, .sdc)<br />
<strong>Design</strong><br />
Compiler<br />
Reports and logs<br />
(text formats)<br />
<strong>Design</strong> database<br />
(.db - <strong>Synopsys</strong> internal<br />
database format)<br />
Gate level Verilog description
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