Synopsys Design Flow

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Synopsys Design Flow SPICE-level Simulation of Completed Design (HSPICE) © Synopsys 2012 148
HSPICE Features HSPICE supports: • Analog/RF/mixed-signal IC Design • Verilog-A Behavioral Modeling • Design For Yield- Process Variability and MosRa Device Reliability Analysis • Transient Noise Analysis • Cell and Memory Characterization © Synopsys 2012 149
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© Synopsys 2012 1 Digital IC Desig
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Introduction © Synopsys 2012 3
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© Synopsys 2012 5 Mobile 100 15 12
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Smart Everything Grid Buildings Car
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Drivers of Innovation and Different
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Advanced Designs and Tapeouts Sourc
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Leading the Way at 22/20nm Design S
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Advanced Design Trends 100% 75% 50%
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Clock Frequency Trends 100% 80% 60%
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$M Hardware/Software Development Co
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Key Innovations in Electronics: Aud
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Key Innovations in Electronics: Com
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Key Innovations in Semiconductors
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Time Flies Away … DEC Alpha 21064
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Another Time Stamp … Itanium, 180
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1961-2011, A 100,000,000X Improveme
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Gordon E. Moore’s Law Twice the N
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Wafer 1” - 1959 © Synopsys 2012
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Proyecciones para el 2000 en 1975
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EDA Back Then… CALMAGRAPHIC, Calm
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1970 - From Manual Layout to Manufa
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Basic Early CAD Applications Gridde
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Technology Or… Art? © Synopsys 2
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Design - Synthesis © Synopsys 2012
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Design - Fab © Synopsys 2012 79
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Design - Verification © Synopsys 2
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Design - Verification © Synopsys 2
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Some Key Contributors to EDA Commer
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Design Process Verify: verify the c
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Bottom - up / Top - down Bottom - u
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The Front End Architecture: • Key
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The Back End Floorplanning • Wher
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The Back End Routing • Complete a
Page 97 and 98: Fabrication Mask fabrication Wafer
Page 99 and 100: Design Implementation System Analys
Page 101 and 102: Classic IC Design Flow © Synopsys
Page 103 and 104: VCS Overview VCS supports multiple
Page 105 and 106: Synopsys Design Flow Logic Synthesi
Page 107 and 108: DC and Design Flow © Synopsys 2012
Page 109 and 110: Design Compiler Input and Output Fi
Page 111 and 112: DFT Key Features One-pass test synt
Page 113 and 114: Formality Introduction Formality ch
Page 115 and 116: Equivalence Checking Verification P
Page 117 and 118: Formality Flow Overview Guidance (L
Page 119 and 120: Introduction TetraMAX is a high-spe
Page 121 and 122: Design Flow Using DFT Compiler and
Page 123 and 124: Steps of Running TetraMAX Reading t
Page 125 and 126: Synopsys Design Flow Static Timing
Page 127 and 128: PrimeTime Inputs and Outputs Parasi
Page 129 and 130: Synopsys Design Flow Physical Desig
Page 131 and 132: IC Compiler Design Flow © Synopsys
Page 133 and 134: Physical Design Steps (2) Core Cloc
Page 135 and 136: Introduction Hercules is a hierarch
Page 137 and 138: Design Database In the beginning of
Page 139 and 140: Schematic Netlist The schematic Net
Page 141 and 142: DRC Flow © Synopsys 2012 141 Physi
Page 143 and 144: Synopsys Design Flow Layout Parasit
Page 145 and 146: Inputs and Outputs of StarRC TCAD_G
Page 147: StarRC Extraction Flow StarRC Comma
Page 151 and 152: Synopsys Design Flow © Synopsys 20
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Synopsys Design Flow

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