Semiconductor Characterization System Technical Data - Helmar

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Model 4200-SCS Technical Data SEmIcondUcTor 12 4200-ScS Semiconductor Characterization System Technical Data 4200-PIV-Q Typical Specifications (continued) mAxImUm drAIn SoUrcE (40V range), typical maximum V d * (V) maximum I d * (A) r dS (W) 6.65 1.33 5 12.3 1.23 10 25 1.0 25 38 0.76 50 50 0.54 92 51.6 0.51 100 65 0.26 250 75.8 0.075 1k *Approximate maximum, does not account for interconnect losses. mAxImUm gATE SoUrcE (20V range ), typical maximum V g * (V) maximum I g * (A) r gS (W) 3.6 0.769 5 6.67 0.667 10 13.3 0.533 25 20 0.400 50 *Approximate maximum, does not account for interconnect losses. Max. Drain Voltage (V) 90 80 I V 1.6 1.4 70 1.2 60 1.0 50 40 0.8 30 0.6 20 0.4 10 V I 0.2 0 0.0 1 10 100 1000 10000 DUT Drain-Source Resistance (Ω) maximum Pulse drain I and V vs. drain-Source resistance 1.888.KEITHLEY (U.S. only) www.keithley.com Max. Drain Current (A) STABILIzATIon KIT The stabilization kit for the 4200-PIV-Q, the 4200-Q-STBL-KIT, minimizes the oscillations caused be III-V RF transistors and LDMOS RF devices. The stabilization kit includes 10 resistors and 2 blanks for customization. Stabilization resistor 10 resistors (+ 2 blanks) in the kit A G R E A T E R M E A S U R E O F C O N F I D E N C E
4200-ScS Semiconductor Characterization System Technical Data 4200-fLASH non-volatile memory Test option The 4200-FLASH package tests single FLASH memory cells or small arrays. This package includes all the necessary code and the interconnect needed to perform a standard set of Flash memory tests for NAND or NOR technologies, with higher pulse voltages important for MLC technologies. The tests included generate program and/or erase cycles using the patentpending Segment ARB pulse mode as well as controlling the in-line High Endurance Output Relay. Endurance and Disturb tests are also included. Four channels of multi-level pulse: • ±40V pulsing into high impedance pin (±20V into 50W). • High Endurance Output Relay provides fast open/close for pin isolation during erase pulse. • Pulse Widths: 200ns to 1s. • Up to 25 pulse levels (100 pulse segments). Included tests: • Endurance. • Program-read. • Erase-read. • Disturb. Easy setup for program/erase cycles Typical nor fLASH gate program/erase cycle 1.888.KEITHLEY (U.S. only) www.keithley.com 4200-fLASH Typical Specifications 1 Channels: 4 channels (optional 8 channels max.). typiCal pulse performanCe: number of voltage levels/waveform: 25. minimum transition time: 150ns. pulse source voltage range: 0 to ±20V into 50W. 0 to ±40V into high impedance. pulse width: 250ns to 1s. trigger synchronization/Jitter: ±8ns. switching time for Dut pin isolation: 100µs. heor off Capacitance: 250pF. smu typiCal DC performanCe typical DC leakage:
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Semiconductor Characterization System Technical Data - Helmar

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