Xilinx Exemplar/ModelSim Tutorial for CPLDs

Exemplar Tutorial
• testbench.vhd
• rtl_sim.do
Verilog
For the Verilog tutorial, copy the following files into the
/cpld_tut/verilog/watch/func directory.
• divider.v
• smallcntr.v
• cnt60.v
• hex2led.v
• tenths.v
• watch.v
• stmchine.v
• testfixture.v
• rtl_sim.do
Starting ModelSim
If you are using the PC, invoke the simulator by selecting Programs
→ Model Tech → ModelSim from the Start menu. For UNIX workstations,
type the following at the prompt.
vsim -i &
Set the project directory using the File → Change Directory
menu command and select watch/func.
Creating the Work Directory
Before compiling the VHDL/Verilog source files, create a directory
for use as a library. Type the following at the ModelSim prompt.
vlib work
This action is echoed in the Transcript window as shown in the
following figure.
1-12 Xilinx Development System