OMAP5912 Applications Processor Silicon Errata ... - Curtin University

OMAP5912 

Applications Processor 

Silicon Errata 

SPRZ209C 

December 2003 − Revised September 2004 

Copyright © 2004, Texas Instruments Incorporated

OMAP5912 Silicon Errata 

REVISION HISTORY 

This revision history highlights the technical changes made to SPRZ209B to generate SPRZ209C. 

Scope: Added MMC_8 and DM_TIMER_1 advisories, etc. 

PAGE(S) 

NO. 

ADDITIONS/CHANGES/DELETIONS 

7 Section 1.1: 

− replaced “Quality and Reliability Conditions” section with “Device and Development-Support Tool Nomenclature” section 

32 Added MMC_8, SPI Mode on the MMC/SD Peripheral is Not Supported 

60 Added Section 6.19, Dual-Mode Timers Advisories 

60 Added DM_TIMER_1, Dual-Mode Timer Peripherals May Not Detect Incoming Events 

SPRZ209C 

2


SPRZ209C 

Contents 

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 

1.1 Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 

1.2 Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 

2 Important Notices and Information About OMAP5912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 

2.1 Useful Information Regarding TMS320C55x Assembler Diagnostic Messages . . . . . . . . . . . . . . . . . . . . . . . 9 

2.1.1 ERROR Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 

2.1.2 WARNING Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 

2.1.3 REMARK Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 

3 DSP Subsystem Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 

3.1 DSP ICACHE Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 

DSP_ICACHE_1 ICACHE Update of TAG-RAM on Wrong Location When a Miss Occurs Between 

RAMSET Preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 

3.2 DSP Emulation Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 

DSP_EMU_1 DSP IDLE Interrupt Not Serviced When an Emulator is Connected . . . . . . . . . . . . . . . . . . 13 

DSP_EMU_2 Emulation is Broken When the DSP is in Isolation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 

3.3 DSP EMIF Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 

DSP_EMIF_1 DSP EMIF/DMA Port Hangs During EMIF Bus Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 

3.4 DSP System Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 

DSP_SYS_1 Bus Error Issued on Byte Accesses to I/O Space, 0x0 Through 0x5f . . . . . . . . . . . . . . . . . 16 

DSP_SYS_2 Use Caution When Reading Following a Configuration Change . . . . . . . . . . . . . . . . . . . . . 16 

DSP_SYS_3 Page Table of DSPMMU Gets Corrupted in Synchronous Scalable Mode . . . . . . . . . . . . . 17 

DSP_SYS_4 Data Page Register and Stack Pointer Updates are not Pipeline-Protected Against 

Data Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 

4 MPU Subsystem Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 

4.1 System Direct Memory Access (DMA) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 

SYS_DMA_1 Incorrect Value in DMA_PCHx_SR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 

4.2 MPU Emulation Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 

MPU_EMU_1 Emulation Connection is Intrusive to ARM Idle Mode. 

OMAP5912 Cannot Go Into Idle With Code Composer Studio Connected. . . . . . . . . . . . . 21 

4.3 MPU System Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 

MPU_SYS_1 MPU IRQ122−127 Can Cause Spurious Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 

MPU_SYS_2 Special Software Procedure is Needed to Acknowledge ARM LV1 Interrupt . . . . . . . . . . . 22 

4.4 MPU Watchdog Timer Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 

MPU_WATCHDOG_1 MPU Watchdog Does Not Reset DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

24 

3


SPRZ209C 

5 Traffic Controller Subsystem Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 

5.1 EMIF Slow (EMIFS) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 

EMIFS_1 Wrong Behavior on CS0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 

EMIFS_2 Program Fetch Prevents Sleep Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 

5.2 EMIF Fast (EMIFF) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 

EMIFF_1 Dual Data Rate (DDR) SDRAM Interface Does Not Support Dual Data Rate Speeds . . . . . . . . . . 26 

EMIFF_2 SDRAM Interface MRS/EMRS Command Issued Twice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 

EMIFF_3 Glitch in DPLL Clock During Reset Assertion Affects EMIFF State Machine . . . . . . . . . . . . . . . . . 27 

5.3 Traffic Controller Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 

TC_1 OMAP5912 Global Software Reset Affects Traffic Controller Frequency . . . . . . . . . . . . . . . . . . . . . 28 

6 OMAP5912 Peripheral Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 

6.1 Multimedia Card/Secure Digital (MMC/SD) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 

MMC_1 MMC/SDIO2 Clock is Not Fed Back to the Peripheral for Some I/O Configuration . . . . . . . . . . . . 30 

MMC_2 Emulation Mode is Intrusive to the MMC/SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 

MMC_3 CMD12 Implementation in TI MMC/SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 

MMC_4 MMC/SDIO CRC Error in CSD_STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 

MMC_5 When Reset With MMC_CON Register Bit 11 (POW), MMC_STAT Does Not Reset . . . . . . . . . . 31 

MMC_6 MMC/SDIO CIRQ Interrupt Does Not Occur for SD-BT Response . . . . . . . . . . . . . . . . . . . . . . . . . . 32 

MMC_7 MMC/SDIO Partial Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 

MMC_8 SPI Mode on the MMC/SD Peripheral is Not Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 

6.2 MICROWIRE Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 

UWIRE_1 MICROWIRE Interface RX Data Failures Possible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 

6.3 Inter-Integrated Circuit (I2C) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 

I2C_1 I2C Interface Needs to Preload Data Before Transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 

6.4 Universal Serial Bus (USB) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 

USB_1 W2FC USB Device’s Pullup Enable Wrong Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 

USB_2 W2FC USB Does Not Work for Some OMAP5912 I/O Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 

6.5 32k Timer Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 

TIMER_1 Timer32K Reload TRB Bit Does Not Work Correctly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 

6.6 Microprocessor Unit I/O (MPUIO) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 

MPUIO_1 MPUIO INPUT_LATCH Register Latch is Disabled During TIPB Read Access to it . . . . . . . . . . . . 39 

MPUIO_2 MPUIO GPIO_INT is Not Generated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 

6.7 Pulse-Width Tone (PWT) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 

PWT_1 Write Followed by Immediate Read not Supported on the PWT Peripheral . . . . . . . . . . . . . . . . . . . 

41 

4


SPRZ209C 

6.8 Camera Interface Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 

CAM_1 Interrupt Observability on Camera Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 

CAM_2 Camera Interface PEAK_COUNTER May be Wrong . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 

CAM_3 Camera Interface RAZ FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 

CAM_4 Shutdown of Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 

CAM_5 Wrong Interrupt Behavior for Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 

6.9 Infrared Data Adapter (IrDA) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 

IRDA_1 NIRQ can Stay Low for a Few OCP Clock Cycles After an Interrupt is Serviced . . . . . . . . . . . . . . 44 

IRDA_3 UART IrDA (MIR Mode) Sends an Additional Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 

IRDA_4 When the UART is in Sleep Mode, a Write to THR Wakes Up the UART and 

Causes FIFO Synchronization Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 

IRDA_5 Rx Overrun and TX_FIFO_FULL Bit Not Operational When FIFO is Disabled . . . . . . . . . . . . . . . . 46 

6.10 Universal Asynchronous Receiver/Transmitter (UART) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 

UART_1 Falling Edge on UART2.RX May Cause a Wake-up Event on OMAP5912 . . . . . . . . . . . . . . . . . . . 47 

UART_2 Disabled UART’s FIFO Interrupts DMA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 

UART_4 Receive Overrun Not Reset on an Early Read of LSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 

6.11 Emulation Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 

EMU_1 32-bit Peripheral Register Access Through the Debugger Between Two 16-Bit Application 

Reads May Corrupt the On-going Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 

EMU_2 GDD Does Not Support Execution Suspension in Case of CPU 

SUSPEND and FREE Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 

EMU_3 Emulation Access to IT_STATUS_REG Clears Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 

EMU_4 Default TDO State During Reset is Unpredictable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 

6.12 Specially Optimized Screen Interface (SoSSI) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 

SOSSI_1 SoSSI Match Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 

SOSSI_2 SoSSI CPriority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 

6.13 Compact Camera Port (CCP) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 

CCP_1 Compact Camera Port Software Reset Does Not Reset Attn-Signal Registers . . . . . . . . . . . . . . . 52 

CCP_2 CCP DMA Does Not Operate as Expected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 

6.14 32-kHz Oscillator Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 

OSC_1 32-kHz Oscillator Does Not Power Down in Deep Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 

OSC_2 32-kHz Oscillator Does Not Work Properly in OMAP5912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 

6.15 Serial Peripheral Interface (SPI) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 

SPI_1 SPI Slave Not Supported on SPIF.DOUT on ZZG Ball R18 (ZDY Ball N17) . . . . . . . . . . . . . . . . . . 55 

SPI_2 SPI Not Able to Receive the First Data While Waking up From Sleep Mode . . . . . . . . . . . . . . . . . . 55 

SPI_3 SPI Outputs are not Controlled Correctly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 

SPI_4 SPI Module Does Not Support 8-Bit Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

56 

5


SPRZ209C 

6.16 Ultra Low-Power Device (ULPD) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 

ULPD_1 ULPD Analog Cell Configuration are Reset After a MPU Peripheral Reset . . . . . . . . . . . . . . . . . . . 57 

6.17 Multichannel Serial Interface (MCSI) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 

MCSI_1 Late Generation of TX DMA Request in the MCSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 

6.18 Multichannel Buffered Serial Port (McBSP) Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 

MCBSP_1 McBSP3 3-Pin Operation Versus 4-Pin Operation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 

6.19 Dual-Mode Timers Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 

DM_TIMER_1 Dual-Mode Timer Peripherals May Not Detect Incoming Events . . . . . . . . . . . . . . . . . . . . . 60 

7 OMAP5912 Device/System Level Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 

7.1 System Advisories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 

SYS_1 Pulldown on the UWIRE.SDI Pin Needs to be Disabled by Software to Save Power . . . . . . . . . . . 61 

SYS_2 When Disabled, the OMAP Peripheral Clock Prevents the OMAP5912 From Going Into 

Deep Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 

SYS_3 OMAP5912 Gated Outputs Forced to 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 

SYS_4 If BVLZ is Not Configured, the Corresponding Interrupt Must be Masked . . . . . . . . . . . . . . . . . . . . 62 

SYS_5 Configuration Registers FUNC_MUX_CTRL_10[8:3] and FUNC_MUX_CTRL_9[11:9] 

Reset Values Do Not Reflect M8, L3, AA20 Configuration in Reset Mode 1 . . . . . . . . . . . . . . . . . . 63 

8 Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 

64 

6


1 Introduction 

SPRZ209C 

This document describes the silicon updates to the functional specifications for the 

OMAP5912, silicon revision B. Issues related to CPU operation are documented in the 

TMS320C55x DSP CPU Programmer’s Reference Supplement (literature number SPRU652). 

1.1 Device and Development-Support Tool Nomenclature 

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320 

DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, 

TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX 

and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes 

(TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). 

Device development evolutionary flow: 

TMX Experimental device that is not necessarily representative of the final device’s electrical specifications 

TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality and 

reliability verification 

TMS Fully qualified production device 

Support tool development evolutionary flow: 

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing. 

TMDS Fully qualified development-support product 

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: 

“Developmental product is intended for internal evaluation purposes.” 

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the 

device have been demonstrated fully. TI’s standard warranty applies. 

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production 

devices. Texas Instruments recommends that these devices not be used in any production system because their 

expected end-use failure rate still is undefined. Only qualified production devices are to be used. 

All trademarks are the property of their respective owners. 

7


1.2 Revision Identification 

SPRZ209C 

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all OMAP 

processors and support tools. Each commercial OMAP platform member has one of three prefixes: X, P, or null (no 

prefix). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. 

These prefixes represent evolutionary stages of product development from engineering prototypes (TMDX) through 

fully qualified production devices/tools (TMDS). 

Device development evolutionary flow: 

X Experimental device that is not necessarily representative of the final device’s electrical specifications and 

may not use production assembly flow. (TMX definition) 

P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical 

specifications. (TMP definition) 

null Production version of the silicon die that is fully qualified. (TMS definition) 

Support tool development evolutionary flow: 

TMDX Development support product that has not yet completed Texas Instruments internal qualification testing. 

TMDS Fully qualified development support product 

TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their 

limitations and intended uses. Experimental devices (TMX) may not be representative of a final product and Texas 

Instruments reserves the right to change or discontinue these products without notice. 

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the 

device have been demonstrated fully. TI’s standard warranty applies. 

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. 

Texas Instruments recommends that these devices not be used in any production system because their expected 

end-use failure rate still is undefined. Only qualified production devices are to be used. 

The device revision can be determined by the symbols marked on the top of the ZDY package as shown in 

Figure 1. Some prototype devices may have markings different from those shown in Figure 1 with the device name 

in the following format: XOMAP5912ZDY where X = product level as defined above and ZDY = package. 


XOMAP5912ZDY 

4−39Z1158 

NOTE: Qualified devices are marked with no prefix at the beginning of the device name, while nonqualified devices are marked with the letter “X” 

at the beginning of the device name. 

OMAP is a trademark of Texas Instruments. 

Figure 1. Example Markings for OMAP5912 ZDY Package, Revision B 

8


2 Important Notices and Information About OMAP5912 

2.1 Useful Information Regarding TMS320C55x Assembler Diagnostic Messages 

SPRZ209C 

The TMS320C55x (C55x) DSP assembler generates three types of diagnostic messages when it detects a 

potential or probable Silicon Exception. 

2.1.1 ERROR Diagnostics 

The assembler generates ERROR diagnostics in cases where it can fully determine that the code will cause a 

silicon exception to occur on hardware. 

2.1.2 WARNING Diagnostics 

The assembler generates WARNING diagnostics in cases where it can fully determine that the code will cause a 

silicon exception to occur on hardware, but which, under certain circumstances, may not be an issue for the user. 

2.1.3 REMARK Diagnostics 

The assembler generates REMARK diagnostics in conditions where it can fully determine that the code may cause 

a silicon exception to occur on hardware, but the exception itself also depends on non-visible trigger conditions that 

the assembler has no knowledge of, such as whether interrupts are enabled. 

Since the assembler cannot determine the state of these trigger conditions, it cannot know that the exception will 

affect this code. Therefore, it generates a REMARK to instruct the user to examine the code and evaluate whether 

this is a potential silicon exception situation. (Please see the following sections for how to suppress remarks in 

situations where you have determined that the other trigger conditions do not exist.) 

Intended Treatment of REMARK Diagnostics 

The intent of generating REMARK diagnostics is to inform the user that the code could potentially cause a silicon 

exception and that it should be reviewed by the user side by side with the trigger conditions and a determination be 

made whether the code is a potential silicon exception situation. 

If the code is determined to be a potential silicon exception situation, users should modify their code to prevent that 

exception from occurring. 

If users determine that their code will not cause a silicon exception based on the trigger conditions, then the 

REMARK that the assembler generates can be suppressed. There are two methods of doing so; please see the 

“Suppressing REMARK Diagnostics” section. 

Suppressing REMARK Diagnostics 

Once the user determines that a silicon exception REMARK diagnostic is not appropriate for the code as written, 

the REMARK diagnostic can be suppressed in one of the following ways. 

• REMARK directives 

• REMARK command-line options 

TMS320C55x and C55x are trademarks of Texas Instruments. 

9


REMARK Directives: 

SPRZ209C 

The .noremark.remark directives can be used to suppress the generation of a REMARK diagnostic for particular 

regions of code. The .noremark directive turns off the generation of a particular REMARK diagnostic. The .remark 

directive re-enables the generation of a particular REMARK diagnostic. 

A ’.noremark ##’ (where ## is the remark id) directive is placed at the beginning of the region, and a ’.remark ##’ 

directive is placed at the end of the region. 

NOTE: The .noremark.remark directive combination should always be placed around the 

entire region of code that participates in the potential silicon exception. Otherwise, spurious 

diagnostics may still be generated. 

Additionally, the user has the option of disabling a silicon exception diagnostic for the entire file by placing just the 

.noremark directive at the top of the assembly file. However, this may be dangerous if, during inevitable code 

maintenance, the code is modified by someone not familiar with all the exception conditions. Please take great 

care when using the directives in this manner. 

REMARK Command-Line Options: 

The compiler shell (cl55) supports a command line option to suppress a particular REMARK diagnostic. The shell 

option −ar# (where # is the assembler’s silicon exception id as described above) suppresses the named REMARK 

for the entire scope of all assembly files compiled with that command. Using the option −ar without a number 

suppresses all REMARK diagnostics. 

Again, this may be dangerous if, during inevitable code maintenance, the code is modified by someone not familiar 

with all the silicon exception conditions. Please take great care when using the command-line REMARK options. 

Using the .noremark/.remark directives covering the shortest possible range of source lines is much safer. 

10


3 DSP Subsystem Advisories 

3.1 DSP ICACHE Advisories 

Advisory 

DSP_ICACHE_1 

Revision(s) Affected: B 

SPRZ209C 

ICACHE Update of TAG-RAM on Wrong Location When a Miss Occurs Between 

RAMSET Preload 

Details: The two ramset banks inside the ICACHE are preloaded when the corresponding ramset tag 

registers’ content are updated through I/O access. The ramset preload uses the same line-fill 

mechanism as the cache miss line-fill; therefore, there is a conflict of resource when the 

ramset refill happens while the I-cache miss line-fill is on. Although there is logic to arbitrate 

this conflict, a functional bug can corrupt the content of Tag ram under a corner condition as 

described below: 

1. I-cache must be turned on with ramset(s) enabled. 

2. The instruction(s) for updating the ramset tag register(s) are embedded with other 

program code in external memory. 

3. The external memory space where the instruction(s) for updating the ramset tag(s) are not 

present in the ICACHE will generate cache miss. 

Example: 

The following assembly code is likely to encounter this faulty corner case: 

Address Instruction 

Ext Mem DSP code 


... 

...... 



Ext Mem *port(#0x1400) = #0xc 2f ; Configure icache 

Ext Mem bit(ST3,#14) = #1 ; Turn on icache 

Ext Mem *port(#0x1406) = #0x0800 ; Update ramset tag for bank1 

Ext Mem *port(#0x1408) = #0x0801 ; Update ramset tag for bank2 


Ext Mem DSP coI...... 

...... 



While the ramset tag is being updated by the I/O bus, the CPU IBQ is prefetching instructions 

that are not present in ICACHE. 

11


Workaround: 

SPRZ209C 

ICACHE Update of TAG-RAM on Wrong Location When a Miss Occurs Between RAMSET Preload (Continued) 

1. Put the code for updating the ramset tag in internal memory, i.e., non-cacheable memory 

space. 

2. Branch from external memory program code to the ramset tag update code. 

3. Continue polling the ramset tag valid bit to make sure the ramset preload has finished. 

4. Branch back to external memory for normal program execution after the preload has 

finished. 

For example: 

Address Instruction 



... 

...... 



Ext Mem *port(#0x1400) #0xce2f ; Configure icache 

Ext Mem bit(ST3,#14) = #1 ; Turn on icache 

EXt Mem goto Preload_ramsets 

Preload_ramsets: 

Int Mem *port(#0x1406) = #0x0800 ; Update ramset tag for bank1 

Scan0: 

Int Mem TC1 = bit(*port(0x1405), #15) ; Read the Tag Valid 

; bit of ramset bank 0 

Int Mem nop_16 

Int Mem if (!TC1) goto Scan0 ; Continue polling if the 

; Tag Valid bit is not 1. 

Int Mem *port(#0x1408) = #0x0801 ; Update ramset tag for bank1 

Scan1: 

Int Mem TC1 = bit(*port(0x1407), #15) ; Read the Tag Valid 

; bit of ramset bank 1 

Int Mem nop_16 

Int Mem if (!TC1) goto Scan1 ; Continue polling if the 

; Tag Valid bit is not 1. 

Int Mem goto Back_from_ramset_preload 

Back_from_ramset_preload: 


Ext Mem I Ie 

...... 

...... 



TI does not intend to correct this functionality on future revisions of OMAP5912. 

12


3.2 DSP Emulation Advisories 

Advisory 

DSP_EMU_1 


SPRZ209C 

DSP IDLE Interrupt Not Serviced When an Emulator is Connected 

Details: A DSP IDLE Interrupt is not serviced when the emulator is connected as shown below: 

1. Emulator connected 

2. RT mode is set 

3. Run test code 

ASM code sets INTM 

ASM code clears all pending interrupts in IFR 

ASM code configures timers, but does not enable 

ASM code sets ICR to 0x3f 

4. Emulator halts CPU 

PC indicates halted at IDLE instruction 

DBGSTAT = 0x805f (IDLE, DSUSP and FXWOK) 

ISR = 0x3f 

No interrupts pending in IFR 

5. Provide single interrupt. 

6. Enable RT int by emulation write to DBIER0 

Halted background code immediately comes out of idle 

ISR = 0x3F (interrupt not taken) 

Workaround: There is no workaround. The emulator result is different from the functional mode (which will 

service the ISR). This only affects the debugger mode. 


13


Advisory 

DSP_EMU_2 


SPRZ209C 

Emulation is Broken When the DSP is in Isolation Mode 

Details: DSP isolation does not route TDI to TDO signals to allow the emulation to continue operating 

once the DSP is put in isolation mode. The DSP can be placed in isolation mode to save 

leakage current by setting bit 12 of POWER_CTRL_REG in ULPD. 

Workaround: There is no workaround. 


14


3.3 DSP EMIF Advisories 

Advisory 

DSP_EMIF_1 


SPRZ209C 

DSP EMIF/DMA Port Hangs During EMIF Bus Error 

Details: If the EMIF times out, the CPU will get a timeout bus error interrupt which may also cause a 

DMA interrupt. If this occurs, the DMA will not timeout but will hang instead. 

Workaround: Whenever an EMIF bus error interrupt occurs, the software needs to reset the DMA and 

reschedule the transfer. 


15


3.4 DSP System Advisories 

Advisory 

DSP_SYS_1 


SPRZ209C 

Bus Error Issued on Byte Accesses to I/O Space, 0x0 Through 0x5f 

Details: A bus error is wrongly issued when a byte access is made to I/O space, address 0x0 through 

0x5f. A bus error is captured by IFR1 bit 8 as “BERRINTF” and ST3 bit 7 as “CBERR”. The 

following is the entire list of byte-access instructions. 

dst = uns(high_byte(Smem)) 

dst = uns(low_byte(Smem)) 

ACx = low_byte(Smem)


Advisory 

DSP_SYS_3 


SPRZ209C 

Page Table of DSPMMU Gets Corrupted in Synchronous Scalable Mode 

Details: When the DSPMMU is configured in the following configuration: 

1. Walking Table Logic (WTL) is enabled 

2. Configured for large or small or tiny page (with two level descriptors) 

3. OMAP5912 is in Synchronous Scalable mode. 

The page table inside external memory gets corrupted when a miss occurs due to an extra 

write request generated by the SYNC DSP modules. 

When a SYNC DSP module request is registered to transfer the request from the DSPMMU to 

the TC, and the WTL is enabled and a miss occurs, the DSPMMU reads the descriptors from 

the page table through the sync DSP module and Traffic Controller. During the transition 

between the first level descriptor fetch and second level descriptor fetch, the SYNC DSP 

generates an extra write request to the first level descriptor location due to improper 

synchronization of request signal. This extra write corrupts the page table. As long as the TLB 

does not get flushed, there is no problem with this extra write to the page table. When the TLB 

is flushed and another miss occurs, the DSPMMU fetches the wrong descriptor. 

This problem does not occur with section (only first level descriptor fetch only). This is 

because there are no back-to-back requests from the DSPMMU to SYNC DSP. 

Workaround: There is no workaround; however, this exception only occurs when the clock mode is set to 

synchronous scalable mode, and walking table logic and two level descriptors are used. 

Except for operating systems, normal applications do not use two level descriptors and 

walking table logic functions. Use only sections in the DSPMMU to avoid any problem due to 

the corruption of the page table. 

17


Advisory 

DSP_SYS_4 


SPRZ209C 

Data Page Register and Stack Pointer Updates are not Pipeline-Protected Against 

Data Move Instructions 

Details: The following registers are used for address generation in direct-addressing mode: 

• XDP[22:0] (DPH[6:0] and DP[15:0]) when the CPL bit (ST1[14]) is 0. (Note that DP[15:7] is 

mapped to ST0[8:0].) 

• XSP[22:0] (SPH[6:0] and SP[15:0]) when the CPL bit (ST1[14]) is 1. 

Any update to these registers, followed by direct-addressing mode, is completed by the 

address generation. However, because of a missing pipeline-protection mechanism, under the 

following conditions, the update of the registers will not be reflected for the address 

generation. 

Condition 1 

• Instruction to update the Data Page register or Stack Pointer in the EXECUTE phase. 

(*See the instruction list below.) 

• less than 4 instruction cycles 

• Smem = coeff || readport() or coeff = Smem || writeport() 

(Smem is in direct-addressing mode. Only these two pairs are problem cases; other 

instructions work fine.) 

(*) 

When CPL = 0, 

Xdst = Xsrc (Xdst is XDP) 

Xdst = popboth() ( ” ) 

XAdst = dbl(Lmem) (XAdst is XDP) 

DP = Smem 

DPH = Smem 

bit(ST0,#k4) = #0/1 (k4 is 8,7, ... ,1,0) 

When CPL = 1, 

Xdst = Xsrc (Xdst is XSP or XSSP) 

Xdst = popboth() ( ” ) 

XAdst = dbl(Lmem) (XAdst is XSP or XSSP) 

SP = Smem 

SP = TAx 

SP = SP + K8 

18


SPRZ209C 

Data Page Register and Stack Pointer Updates are not Pipeline Protected Against Data Move Instructions (Continued) 

Condition 2 

Instruction with MMR write to 

• DPH(0x2B)/DP(0x2E)/ST0_55(0x02)/ST0(0x06) with CPL = 0 or 

SPH(0x4E)/SP(0x18,0x4D) with CPL = 1 in WRITE phase 

• less than 5 instruction cycles 

• “Smem = coeff || readport()” or “coeff = Smem || writeport()” 

(Smem is in direct-addressing mode. Only these two pairs are problem cases; other 

instructions work fine.) 

Workaround: Make sure enough instruction slots are inserted between the two events as follows: 

• More than 4 instruction slots for Condition 1. 

• More than 5 instructions slots for Condition 2. 

Example: 

XDP = AC0 

nop 

nop 

nop 

nop 

@#0xa = coef(*CDP) || readport() 


19


4 MPU Subsystem Advisories 

4.1 System Direct Memory Access (DMA) Advisories 

Advisory 

SYS_DMA_1 


SPRZ209C 

Incorrect Value in DMA_PCHx_SR Register 

Details: The SDMA global registers—PchSR_M0, PchSR_M1, and PchSR_P—are used to display the 

current logical channel which is running on the M0, M1, and P physical channels, respectively. 

However, in OMAP5912 these registers do not show the correct logical channel when the 

channels are individually enabled. These registers get updated only when all the physical 

channels (M0, M1, and P) are working simultaneously. Update of any particular PchSR 

register depends on the enabling of other physical channels. 

Workaround: Do not rely on these registers if you are running less than 3 logical channels. 


20


4.2 MPU Emulation Advisories 

Advisory 

MPU_EMU_1 


SPRZ209C 

Emulation Connection is Intrusive to ARM Idle Mode. 

OMAP5912 Cannot Go Into Idle With Code Composer Studio Connected. 

Details: The JTAG on ARM926EJ-S does not work if the functional clock is halted. 

The logic to the on-chip power management is gated by emulator connection so that the 

functional clock is not shut down and the sleep mode is not entered. 



ARM926EJ-S is a trademark of ARM Limited in the EU and other countries. 

21


4.3 MPU System Advisories 

Advisory 

MPU_SYS_1 


SPRZ209C 

MPU IRQ122−127 Can Cause Spurious Interrupts 

Details: On OMAP5912, MPU IRQ122 through IRQ127 are tied low and therefore, are capable of 

interrupting the system if their corresponding ILR registers (from address 0xFFFE:0384 for 

IRQ122 to 0xFFFE:0398 for IRQ127) are configured as level-sensitive. 

A level interrupt is configured if SENS_EDGE is set to 1 (bit 1 of ILR register). 

Workaround: Make sure SENS_EDGE is cleared to 0 for IRQ122−IRQ127’s IRL registers (from address 

0xFFFE:0384 for IRQ122 to 0xFFFE:0398 for IRQ127). 


Advisory 

MPU_SYS_2 


Special Software Procedure is Needed to Acknowledge ARM LV1 Interrupt 

Details: The correct procedure for acknowledging an interrupt in the LV1 interrupt handler is described 

below: 

• INTH asserts an interrupt 

• ARM enters an interrupt routine 

• ARM executes the interrupt routine 

At the end of the interrupt routine, ARM needs to do the following: 

• Save the LV1 MIR (Mask interrupt) register 

• Mask all interrupts 

• For level-sensitive interrupt, clear the source of the interrupt 

• For edge-sensitive interrupt, clear the current interrupt line in the INTH 

• Write to the NEW_IRQ_AGR register to clear the register 

• Restore MIR 

22


SPRZ209C 

Special Software Procedure is Needed to Acknowledge ARM LV1 Interrupt (Continued) 

If this is not done, no interrupt will be missed; however, there might be an interrupt priority 

problem: 

• If the interrupt that is acknowledged in the interrupt routine is asserted again before 

NEW_IRQ_AGR bit is written, then the LV1 INTH will register this interrupt as the currently 

pending interrupt, even if higher-priority interrupts are still pending. 

• The other interrupts will have to wait. 

One common case when this might happen is if two or more lv2 interrupts fire almost at the 

same time. 

At the end of ISR, LV2 INTH’s NEW_IRQ_AGR is set at first and LV1’s one is set next. IRQ to 

LV1 is asserted again before setting Lv1’s NEW_IRQ_AGR if there is other pending interrupt 

request on Lv2. Interrupt request on Lv2 will be serviced first regardless of priority on any 

possibly active Lv1 interrupts. 

Workaround: At the end of the interrupt routine, ARM needs to do the following: 

• Save the LV1 MIR (Mask interrupt) register 

• Mask all interrupts 

• For level-sensitive interrupts, clear the source of the interrupt 

• For edge-sensitive interrupts, clear the current interrupt line in the INTH 

• Write to the NEW_IRQ_AGR register to clear the register. 

• Restore MIR 


23


4.4 MPU Watchdog Timer Advisories 

Advisory 

MPU_WATCHDOG_1 


SPRZ209C 

MPU Watchdog Does Not Reset DPLL 

Details: If the MPU watchdog timer expires, a reset is provided to the ARMCK_CTL registers (resetting 

the clock divisors) but not to the DPLL. 

This means that when OMAP5912 is operating at 192 MHz with SDRAM at 96 MHz (/2) and a 

WD timer reset occurs, the ARM will begin executing code at the reset vector with the DPLL 

remaining at 192 MHz and all clock divisors set at /1. See below: 

• Before reset: 

− DPLL register (0xFFFE CF00) = 0x2813 (DPLL Lock mode, 16 x multiplier) 

− ARM_SYSST register (0xFFFE CE18) = 0x1000 (Synchronous scalable mode) 

− ARM_CKCTL register (0xFFFE CE00) = 0x5101 (ARMINTH, TC. PER clocks div/2; 

clkref = CLKGen1) 

• After reset: 

− DPLL register (0xFFFE CF00) = 0x2813 − No change 

− ARM_SYSST register (0xFFFE CE18) = 0x000C (Full synchronous mode, 

WD + MPU reset) 

− ARM_CKCTL register (0xFFFE CE00) = 0x3000 (No div; clkref = CLKGen1) 

Workaround: Use the 32k watchdog timer. It properly resets the DPLL when it expires; however, the 32k WD 

Timer has less precision on the timer value (it counts 30.5 µs ticks instead of ~0.1 µs ticks) 

and cannot cause a WD reset to occur in less than 30.5 µs. 


24


5 Traffic Controller Subsystem Advisories 

5.1 EMIF Slow (EMIFS) Advisories 

Advisory 

EMIFS_1 


SPRZ209C 

Wrong Behavior on CS0 

Details: Due to incorrect decoding logic on CS0 (between internal peripherals and External NOR 

FLASH), NOR flash cannot be accessed on CS0 (32Mb). 

Workaround: There is no workaround. Do not map external memory on EMIFS Chip Select 0. 

TI is investigating whether this feature will be fixed on future revisions of OMAP5912. 

Advisory 

EMIFS_2 


Program Fetch Prevents Sleep Entry 

Details: An address range centered on 0x0000_3C18 cannot be used while booting from EMIFS Chip 

Select 3. If the program enters this particular address range, a debug request is sent to the 

ARM processor which prevents OMAP5912 from entering the idle mode. 

This behavior is intentional and is related to OMAP5912 special features. This feature will not 

affect normal devices as the booting is done from the internal Boot ROM. 

Workaround: The software has to stay away from 0x0000_3C18 ± 10 x 32-bit addresses. This is needed to 

account for the ARM926 pipeline architecture. 


25


5.2 EMIF Fast (EMIFF) Advisories 

Advisory 

EMIFF_1 


SPRZ209C 

Dual Data Rate (DDR) SDRAM Interface Does Not Support Dual Data Rate Speeds 

Details: Because of the way the EMIFF DDR interface is implemented internally on the OMAP5912, 

there are on-chip delays in the EMIFF data path that limit the rate at which DDR SDRAM 

memories can be accessed. DDR SDRAM will give no improvement in performance than 

single data rate SDRAM. 


TI does intend to correct this functionality on a future revision of OMAP5912. 

Advisory 

EMIFF_2 


SDRAM Interface MRS/EMRS Command Issued Twice 

Details: When the ACCESS_FACTOR1 in the RHEA CNTL register is configured for values strictly 

greater than 1, unpredictable behavior occurs on the SDRAM bus and multiple MRS 

commands are issued by the Traffic Controller. 

Workaround: Make sure that the ACCESS_FACTOR1 (bit field 7:4) in the RHEA CNTL (0xFFFE:CA00) is 

set to 1 so that the strobe_1 period on the TIPB bus is equal to 1/2 the TIPB bridge clock 

period. 


26


Advisory 

EMIFF_3 


SPRZ209C 

Glitch in DPLL Clock During Reset Assertion Affects EMIFF State Machine 

Details: When a reset to the DPLL is asserted, there is a glitch at the output of the DPLL due to the 

transition from DPLL core clock (high frequency) to the DPLL reference clock. 

When a warm reset (MPU reset) occurs, it does not reach the EMIFF. This may cause the 

EMIFF to not enter self-refresh mode. Because of this, data in EMIFF may get corrupt. 

When a power-on-reset (POR) is asserted, there is no functional failure as the entire 

OMAP5912 device gets reset. 

Workaround: There is no software workaround if a warm reset (MPU reset) is asserted. A power-on-reset is 

the only way to recover the EMIFF state machine. 


27


5.3 Traffic Controller Advisories 

Advisory 

TC_1 


SPRZ209C 

OMAP5912 Global Software Reset Affects Traffic Controller Frequency 

Details: At power-up reset, the traffic controller (TC) clock is the system clock (base frequency is 

19.2 MHz, 12 MHz, or 13 MHz) and in fully synchronous mode (ARM clock = DSP clock = 

TC clock). During boot, if the user decides to do the following: 

MODULE 

• Switch to synchronous scalable mode (ARM clock = DSP clock, TC clock = ARM clock/2) 

and enable the DPLL (system clock x 10 = 192-MHz clock if the base frequency is 

19.2 MHz), 

• Perform a global software reset by: 

− setting the SW_RST bit (bit 3 in the ARM_RSTCT1 register), or 

− setting the ARM RST bit (bit 0 in the ARM_RSTC1 register) and then clearing the 

DSP_EN bit (bit 1 in the ARM_RSTC1 register). 

Then, the DPLL is still enabled and OMAP5912 is switched back automatically to fully 

synchronous mode (ARM_SYSST register is reset). This causes: ARM clock = DSP clock = 

TC Clock =192 MHz. 192 MHz is too high of a frequency for the TC to operate and can 

potentially cause incorrect data to be fetched. See Table 1. 

Table 1. Reset Sources for the Clock Module and the DPLL 

Cold Reset † Warm Reset ‡ 

Global 

System 

Reset § 

ARM 

WD Reset 

EVENT 

DSP 

WD Reset 

MPU 

Software 

Reset 

DSP 

Software 

Reset 

DSP 

Software 

Reset # 

CLKM_1 Yes Yes Yes Yes No No No No 



DPLL_1 Yes Yes No No No No No No 

DPLL_2 Yes Yes No No No No No No 

† Power-up reset or on_noff 

‡ MPU_nreset, secure WD reset, or 32-kHz WD reset 

§ SW_RST (Bit 3 in ARM_RSTCT1) is written to 1, or set ARMRST (Bit 0 in ARM_RSTC1) and clear DSP_EN (Bit 1 in 

ARM_RSTC1) 

DSP_EN (Bit 1 in ARM_RSTC1) is written to 0 

# DSP_RST (Bit 2 in ARM_RSTC1) is written to 1 

28


SPRZ209C 

OMAP5912 Global Software Reset Affects Traffic Controller Frequency (Continued) 

Workaround: Before performing a Global Software Reset, it is recommended that the DPLL be bypassed so 

that after the clock module has reset to fully synchronous mode, the TC frequency is equal to 

the OMAP5912 base frequency. 


29


6 OMAP5912 Peripheral Advisories 

6.1 Multimedia Card/Secure Digital (MMC/SD) Advisories 

Advisory 

MMC_1 


SPRZ209C 

MMC/SDIO2 Clock is Not Fed Back to the Peripheral for Some I/O Configuration 

Details: MMC/SDIO input timings are referenced to the feedback input clock. The feedback input clock 

is wrapped around from the output clock, through a bidirectional I/O, and back to the feedback 

clock input port of the MMC/SDIO subchip/ports. For MMC/SDIO2, there are two pins that can 

provide this clock function, MCSI2.CLK (ZZG ball Y10; ZDY ball P8) and CAM.RSTZ (ZZG 

ball M19; ZDY ball K12). CAM.RSTZ is not getting wrapped back around and routed to the 

feedback clock port ADPFDBKCLKI. 

Workaround: Do not use remapping of MMC2.CLK on CAM.RSTZ (ZZG ball M19; ZDY ball K12). Instead, 

use MCSI2.CLK (ZZG ball Y10; ZDY ball P8). 


Advisory 

MMC_2 


Emulation Mode is Intrusive to the MMC/SDIO 

Details: Using Code Composer Studio Integrated Development Environment (IDE), executed step by 

step, the following was observed: 

MMC_SDIO1_CON_16_0 = 0x803 

There is no effect in the Code Composer Studio memory window at the corresponding 

0xFFFB780C address. Moreover, if a direct Code Composer Studio read command tries to 

access this address, the same result occurs. 

Workaround: If you put back the PC pointer to the same instruction and run it to some latter point in the 

code (not step-by-step). The instruction is well executed and 0x803 is written to the register. 

TI does intend to correct this functionality on future revisions of OMAP5912. 

Code Composer Studio is a trademark of Texas Instruments. 

30


Advisory 

MMC_3 


SPRZ209C 

CMD12 Implementation in TI MMC/SDIO 

Details: The Multimedia Card System specification (Revision 3.2) states that while the CMD12 Stop 

Command is issued by the Host, valid data can still be received or sent (refer to Figures 28 

and 31 of the MMC card specification). 

The TI MMC/SDIO state machine will block any CMD12 stop command as soon as the receive 

FIFO is full to avoid the loss of a valid read data. Similarly, in case of a write sequence, the TI 

MMC/SDIO state machine will block any CMD12 stop command if the transmit FIFO is empty. 

Workaround: During a read sequence, make sure the receive FIFO is not full before issuing a CMD12 stop 

command. During a write sequence, make sure the transmit FIFO is not empty before issuing 

a CMD12 stop command. 

Advisory 

MMC_4 



MMC/SDIO CRC Error in CSD_STRUCTURE 

Details: In normal operations, the MMCSDIO controller reads the CSD_structure register of the 

external card. However, during CRC calculation, it does not account for the field related to the 

CSD_STRUCTURE register version 1.2 (bit 2 of the CSD_Structure). Consequently, a CRC 

error occurs. 

Workaround: If a CRC error occurs (MMC_STAT bit 8 is set and Data CRC Error is set), the software should 

do a CRC software computation on the 128 bits received during the read of the 

CSD_Structure to confirm if it was a valid CRC error. 

Advisory 

MMC_5 



When Reset With MMC_CON Register Bit 11 (POW), MMC_STAT Does Not Reset 

Details: During power-off, MMC_STAT is supposed to be reset by setting the POW bit in the 

MMC_CON register; however, this does not occur. 

Workaround: Software workaround: write 0xFFFF to MMC_STAT after a POW reset. 


31


Advisory 

MMC_6 


SPRZ209C 

MMC/SDIO CIRQ Interrupt Does Not Occur for SD-BT Response 

Details: An asynchronous interrupt on DAT [1] is not propagated to the MMC_STAT [CIRQ] when the 

MMCSDIO peripheral is in auto IDLE with its interface OCP clock turned off. Because the 

OCP clock is off, incoming events from the external MMC/SDIO card are not synchronized. 

Workaround: There are two ways to switch on the interface OCP clock when the module is in auto-idle 

state: 

Advisory 

MMC_7 


• OCP accesses by the host: polling loop on the MMC_STAT register. 

• Set bit INAB = 1 in the MMC_CMD register after the BRS (Block received/sent) in the 

MMC_STAT register is set after completion of a command + data transfer. This will trigger 

an EOC (end-of-command) interrupt. During this EOC interrupt, if a CIRQ interrupt does 

not occur, read the MMC_STAT register and set bit INAB = 1 again, which will trigger 

another EOC, and so on, until CIRQ = 1, which will happen if DAT [1] is low (the time 

when DAT [1] goes low is not always predictable). 

MMC/SDIO Partial Reset 

Details: When setting the SRST bit in the MMC_SYSC register to perform a software reset, the RSTD 

bit in the MMC_SYSS register never gets set. 

Workaround: To perform a partial reset, the following sequence must be used: 

1. Set up the module as needed (with a POW=1) 

2. Clear the POW and the CKDIV bits 

3. Set the POW along with the CKDIV bits 


Advisory 

MMC_8 

Revision(s) Affected: All revisions 

SPI Mode on the MMC/SD Peripheral is Not Supported 

Details: The SPI mode on the MMC/SD peripheral is not supported on this device. 

Workaround: This exception will not be fixed in future silicon revisions. 

32


6.2 MICROWIRE Advisories 

Advisory 

UWIRE_1 


Details: See the table below and Figure 2 and Figure 3. 

CSx_EDGE_RD = 0 

CSx_EDGE_WR = 0 

SCLK Not Inverted Data read on falling edge of 

SCLK. Data write on falling 

edge of SCLK. 

Delay of 2 SCLK cycles 

between last bit transmitted 

on falling edge and first bit 

captured on falling edge. 

No issue. 

SCLK Inverted Data read on rising edge of 

SCLK. Data write on rising 

edge of SCLK. 



on rising edge and first bit 

captured on rising edge. 

No issue. 



Data read on rising edge of 


edge of SCLK. 





No issue. 

Data read on falling edge of 


edge of SCLK. 





No issue. 

MICROWIRE is a registered trademark of National Semiconductor Corporation. 

SPRZ209C 

MICROWIRE Interface RX Data Failures Possible 





edge of SCLK. 

Delay of 1.5 SCLK cycles 




Issue found (see Figure 2): 

One extra bit is captured. 

Workaround: 

Ignore Bit 0 of the receive 

data register (shift right one 

bit). Note that this 

workaround does not work for 

a 16-bit data configuration 

(1 bit is lost). 



edge of SCLK. 





Issue found: 

One extra bit is captured. 

Workaround: 

Ignore Bit 0 of the receive 

data register (shift right one 

bit). Note that this 

workaround does not work for 

a 16-bit data configuration 

(1 bit is lost). 





edge of SCLK. 





Issue found (see Figure 3): 

First bit captured will start 

2.5 SCLK cycles after the last 

bit sent instead of 1.5 SCLK 

as defined in the specifications. 

Workaround: 

Do not use this configuration. 

Use one of the alternate 

configurations available for 

this module. 



edge of SCLK. 





Issue found: 

First bit captured will start 

2.5 SCLK cycles after the last 

bit sent instead of 1.5 SCLK 

as defined in the specifications. 

Workaround: 

Do not use this configuration. 

33


SCLK 

DI_PG 

DO 

NCS0 

SPRZ209C 

MICROWIRE Interface RX Data Failures Possible (Continued) 

One Extra 

Read Occurs 

Figure 2. Write (4 Bits) on Rising/Read (4 Bits) on Falling (TX = 0xA, RX and 0x1F = 0x14) 

SCLK 

DI_PG 

DO 

NCS0 

No Read 

Occurs Here 

Figure 3. Write (4 Bits) on Falling/Read (4 Bits) on Rising (TX = 0xA, RX and 0xF = 0xA) 


34


6.3 Inter-Integrated Circuit (I 2 C) Advisories 

Advisory 

I2C_1 


SPRZ209C 

I 2 C Interface Needs to Preload Data Before Transmitting 

Details: Software needs to enable the I 2 C peripheral in transmit mode before writing data to the FIFO. 

This does not apply for receive mode. 



35


6.4 Universal Serial Bus (USB) Advisories 

Advisory 

USB_1 


SPRZ209C 

W2FC USB Device’s Pullup Enable Wrong Polarity 

Details: The W2FC (USB device) pullup enable can be controlled by an output signal in the three 

different ways shown below. In each case, the polarity is the opposite of what is specified. 

1. ZZG ball W4 (ZDY ball P4), USB.PUEN (conf “000”), is active-low but should be high. 

2. ZZG ball W4 (ZDY ball P4), USB.PUDIS (conf “011”), is active-high but should be low. 

3. ZZG ball P9 (ZDY ball T2), USB.PUEN (conf “111”), is active-low but should be high. 

NOTE: The USB pullup can also be controlled elsewhere (e.g., in a UART/I 2 C/SPI-controlled 

USB OTG PHY). In these cases, this exception has no impact. 

Workaround: For each of the three cases above, possible software or hardware workaround are possible. 

Advisory 

USB_2 


1. Software: Use case 2) instead 

2. Software: Use case 1) instead 

3. Hardware: Use a GPIO pin instead as pullup enable. GPIO should be set to 1 after the 

pullup is enabled in the W2FC, and to 0 before it is disabled. 

Hardware: Add external inverter or change pullup implementation. 


W2FC USB Does Not Work for Some OMAP5912 I/O Settings 

Details: When mapped on OMAP Port2 (external PHY), USB Port0 works in the following PHY 

interface modes: 

• unidirectional 

• 6-pin or bidirectional 3-pin/4-pin 

USB Port 2 (external PHY) activity disrupts USB Port 0 inputs if that port is also used on the 

internal transceiver. This activity causes random reactions on USB Port 0, regardless of the 

PHY mode used on Port 2. Figure 4 shows USB implementation on OMAP5912. Note that 

other I/O multiplexing are implemented on OMAP5912 USB Port2 (for instance, I/O of 

UART2). 

36



USB 

OTG 

I 2 C 

UART 

0 

1 

2 

SPRZ209C 

W2FC USB Does Not Work for Some OMAP5912 I/O Settings (Continued) 

Signals 

Muxing 

and 

Isolation 

Logic 

Config 

USB 

Port 

0 

D+ 

D− 

USB USB 

D+ 

Port 

Transceiver 

1 

IC D− 

USB 

Port 

0,2 

Integrated 

USB Lines 

Transceiver 

USB 

Transceiver 

IC 

Figure 4. USB Implementation on OMAP5912 

Workaround: Do not use USB port 0 (with internal transceivers) and USB port 2 simultaneously. 

System-level configuration bit USB_TRANSCEIVER_CTRL.CONF_USB2_UNI_R must be set 

to 1 (default value is 0 after reset). 

This bit configures USB port 2 interface with external USB transceiver. 

• 0: bidirectional mode 

• 1: unidirectional mode 

This setting is required to avoid any corruption on USB Port #0 while using UART2 on ZZG 

balls V6 and W5 (ZDY balls R4 and T4). 


D+ 

D− 

37


6.5 32k Timer Advisories 

Advisory 

TIMER_1 


SPRZ209C 

Timer32K Reload TRB Bit Does Not Work Correctly 

Details: The Timer32K reload bit (TRB) is used to load the TCR register with the value contained in the 

TVR register. Once the TCR is loaded, the TRB bit should be automatically reset to ‘0’. The 

user should be able to use the TRB bit (by polling) to know when to load a new value in the 

TVR. 

However (see Figure 5), the TRB bit is reset to zero by the falling edge of 32-kHz clock only 

after a maximum of 1.5 x 32-kHz clock period (or minimum 0.5 x 32-kHz clock period) after the 

TRB bit is set. The TCR register is loaded after a maximum of 2 x 32-kHz clock periods (or 

minimum of 1 x 32-kHz clock period) on the rising edge of the 32-kHz clock. After the TRB is 

reset, there is a one 32-kHz clock period where a new TRB setting will not be taken into 

account by the module. If the user programs the TVR and updates the TRB bit within this 

32-kHz clock period, the new TVR will not be loaded correctly into the TCR. 

32-kHz Clock 

TVR Register 

TRB Bit 

(CR Register) 

TCR Register 

Value A Value B 

Period for Which the TRB Bit 

is Permanently Reset to “0” 

No TRB Bit Write is Taken 

into Account 

Set Bit TRB in the CR Register 

Write Value_A in the TVR Register 

Value A Value B 

Figure 5. Latching of TVR Register Onto the TCR Register 

Workaround: The safe way to load a new value in the TCR is to poll the TRB bit. When the TRB is equal to 

‘0’ (signaling that the previous value has been loaded), the user has to wait for an additional 

one 32-kHz clock period before loading a new value in the TVR and setting the TRB bit to ‘1’. 


38


6.6 Microprocessor Unit I/O (MPUIO) Advisories 

Advisory 

MPUIO_1 


SPRZ209C 

MPUIO INPUT_LATCH Register Latch is Disabled During TIPB Read Access to it 

Details: A continuous polling on the MPUIO INPUT_LATCH register does not work correctly. 

The MPUIO_INPUT_LATCH register is implemented with a latch that has the following 

functionality: 

• Enabled when there is no TIPB read access to the MPUIO INPUT_LATCH register. The 

register is directly updated by the MPUIO inputs. 

• Disabled when there is a TIPB read access to the MPUIO INPUT_LATCH register. The 

register holds its last value until the latch is enabled. 

Except in the MPUIO peripheral, the TIPB STROBE is not used to validate a TIPB read 

access. Consequently, as long as an MPUIO INPUT_LATCH register address is present on 

the TIPB bus, the corresponding MPUIO INPUT_LATCH register latch is selected and 

therefore disabled. 

Workaround: In order to avoid this behavior, during the MPUIO INPUT_LATCH register polling, a dummy 

TIPB access (the only condition is to do this access to another TIPB address) has to occur 

after the MPUIO INPUT_LATCH register read. 


39


Advisory 

MPUIO_2 


SPRZ209C 

MPUIO GPIO_INT is Not Generated 

Details: The reset of the MPUIO GPIO Interrupt is done asynchronously when a GPIO_INT register 

read occurs. The release of this reset is done synchronously with the 32 kHz clock to avoid 

any reset recovery time violation. A read of the GPIO_INT register while the 32k clock is low or 

transitioning can result in a deadlock of the interrupt state machine that causes all further 

interrupts on the subject MPUIO pin to be ignored. 

Workaround: After receiving the MPUIO GPIO_INT, the MPU should observe the 32-kHz system clock and 

then read the GPIO_INT register only after a ‘0’ to ‘1’ transition. 

There are different ways to detect a ‘0’ to ‘1’ transition on the 32-kHz system clock: 

• Polling the timer 32k counter until there is an increment (see the waveforms in Figure 6, 

which describe the procedure): 

32K 

INT 

Timer 32K 

Counter 

n n−1 n−2 

Polling of Timer 32K 

After Reception of the 

GPIO_INT and Wait for Increment 

Read GPIO_INT Register 

Figure 6. Read of GPIO Register While 32k Clock is Low 

• Loop-back the CLK32K_OUT output on one available MPUIO, GPIO or KB.R input, and 

polling the corresponding register. 

Note that the maximum delay inserted by this workaround, before the interrupt clears, is 

31 µSec (32K 1 clock period). 


40


6.7 Pulse-Width Tone (PWT) Advisories 

Advisory 

PWT_1 


SPRZ209C 

Write Followed by Immediate Read not Supported on 

the PWT Peripheral 

Details: A write followed by an immediate read does not work on the ARM address space defined 

below. If a read occurs immediately after the write to the same address, then the read will not 

be the data that was written. The affected address spaces are: 

• PWT peripheral: Address space FFFB:6000 to End Address FFFB:67FF 

Workaround: When an immediate read is required after a write to any register in the above address space, 

make two consecutive writes to the same address prior to the read. Using this procedure 

ensures that the first write completes and the read data will be correct. 


41


6.8 Camera Interface Advisories 

Advisory 

CAM_1 


SPRZ209C 

Interrupt Observability on Camera Port 

Details: The active-high arm_obs_int signal, which appears on the CAM.D[4] pin when the camera 

interface is in observability mode, is an inverted copy of the ITR register. The 

CONF_ARM_INT_SEL_R bits of the FUNC_MUX_CTRL_2 register are used to select the 

ARM level 2 interrupt to be observed. 

Workaround: There is no workaround. The interrupt observed is inactive-low and active-high. 

Advisory 

CAM_2 



Camera Interface PEAK_COUNTER May be Wrong 

Details: The PEAK_COUNTER may generate a wrong value. This occurs because the clock to the 

register is gated, preventing the register update. 

Workaround: Software workaround: Make sure that MCLK_EN, bit 5 of the Clock Control Register 

(CTRLCLOCK), is set to 1. 

Advisory 

CAM_3 



Camera Interface RAZ FIFO 

Details: The camera interface uses 4-byte-wide receive registers which latch the data from the data 

pins. When all four registers get valid data in them, the data is transferred into the FIFO. 

Unfortunately, if the user wants to begin a new frame of data, there is no way of manually 

resetting these registers to begin clean. 

Workaround: The only way to clear these registers is to allow the camera interface to be clocked with the 

LCLK signal while the VSYNC or HSYNC signals are inactive. Note: this solution will not 

work for designs which require the LCLK to be qualified (gated) to accommodate 

imagers that provide image decimation. 


42


Advisory 

CAM_4 


SPRZ209C 

Shutdown of Camera Interface 

Details: The camera interface logic generates CAM.EXCLK frequencies based on either the 12-MHz 

system clock or by a 48-MHz clock provided by the DPLL in the ULPD peripheral. The 12-MHz 

clock is enabled by setting bit 5 (MCLK_EN) of the camera interface CTRLCLOCK register. 

The 48-MHz clock is enabled either by setting bit 6 (DPLL_EN) or by selecting a clock mode 

where bit 2 is 1 (this is the MSB of the FOSCMODE field). 

To enter Deep Sleep mode, it is necessary to eliminate the camera module requests for both 

the 12-MHz and 48-MHz clocks. However, to eliminate the 48-MHz clock request, the 12-MHz 

clock must be running (i.e., these two clocks cannot be stopped simultaneously). 

Workaround: To completely shut down the camera module, two separate writes to the CTRLCLOCK register 

is required. 

1. The first write must clear DPLL_EN (bit 6 = 0) and select an FOSCMODE where bit 2 is 0. 

During this same write, other register bits may also be changed, but MCLK_EN must still 

be 1. This keeps the 12-MHz clock running. 

2. The second write must clear MCLK_EN (bit 5 = 0). 

This workaround is not necessary if neither bit 6 nor bit 2 was enabled. There are no other 

restrictions on these consecutive writes (i.e., they can be consecutive operations). 


Advisory 

CAM_5 


Wrong Interrupt Behavior for Camera Interface 

Details: When the word number in the FIFO reaches 128, the FIFO becomes full. The counter inside 

the FIFO considers this word number as a negative value, which causes the status bit (bit 5) 

to be cleared. The status bit (bit 5) indicates that the threshold value has been reached, and 

clearing it deactivates the interrupt line without any status read access. 

Workaround: Read the FIFO before it is full (128 words) or set the threshold field (in MODE register) at 126 

instead of 127. 


43


6.9 Infrared Data Adapter (IrDA) Advisories 

Advisory 

IRDA_1 


SPRZ209C 

NIRQ can Stay Low for a Few OCP Clock Cycles After an Interrupt is Serviced 

Details: This problem concerns the service of interrupts by reading from/writing to a register in the 

functional clock domain: 

After an access to the register is finished (falling edge of SCMDACCEPT), the NIRQ line can 

stay low for a few OCP clock cycles before it is deasserted. The actual delay depends on the 

clock ratio between the functional clock and the OCP clock. 

There may be potential problems with interrupts serviced twice when slower OCP Clocks are 

used, since some IRQ controllers are programmed to be level-sensitive. 

Workaround: Whenever an interrupt is processed: 

• In UART Mode, the user needs to read the Interrupt Identification Register (IIR). If the 

IT_Pending is cleared, no interrupt as defined by IT_type is actually pending and the 

software should immediately exit the interrupt handler. 

• In IrDA mode, the user needs to read the Interrupt Identification Register (IIR). If the 

returned value is 0x00, no interrupt is actually pending and the software should 

immediately exit the interrupt handler. 


44


Advisory 

IRDA_3 


SPRZ209C 

UART IrDA (MIR Mode) Sends an Additional Bit 

Details: In MIR mode, an additional pulse is added at the end of the transmit frame after the Stop Flag. 

The MIR protocol makes sure that this additional bit is not interpreted as a start bit of a 

subsequent transmit frame. 

Start Flags Frame Data CRC-16 Stop Flag 

Workaround: No workaround required. 


Advisory 

IRDA_4 


When the UART is in Sleep Mode, a Write to THR Wakes Up the UART and Causes FIFO 

Synchronization Errors 

Details: When the UART enters sleep mode, a write to the transmit Holding Register (THR) is meant to 

wake up the device and to trigger a transmission of the packet written into the THR. However, 

the FIFO still thinks it is empty so no data gets transmitted. If a second byte is written into 

THR, the FIFO begins transmitting the first data but does not send the second one. If a third 

data is written into the THR, the FIFO will send the second data. Ultimately, the sequence is 

preserved and there is no loss of data. 

Workaround: The software should not use Sleep mode and should not configure Sleep mode in the Interrupt 

Enable Register (IER) (bit 4 of IER Register) in UART Mode. 

The software should not use Sleep mode and should not configure the Sleep mode in the 

Mode Definition Register1 (MDR1) (bit 3 of MDR1 Register) in IrDA Mode. 


45


Advisory 

IRDA_5 


SPRZ209C 

Rx Overrun and TX_FIFO_FULL Bit Not Operational When FIFO is Disabled 

Details: If the user sets the FIFO depth to 1, bit 0 (FIFO_EN) of the FIFO Control Register (FCR) is 

cleared to 0, and the following occurs: 

• If an overrun condition occurs, it is not flagged. 

• TX_FIFO_FULL [bit 0 of Supplementary Status Register (SSR)] is always 0 whether or not 

the FIFO (1 byte in this case) is FULL. 

Workaround: Avoid overrun conditions by setting the FIFO depth to 64 (corresponding to 1 for FIFO_EN). 

For the case where an overrun condition is unlikely: 

• In UART mode, use TX_FIFO_E mapped as bit 5 of the Line Status Register (LSR) to 

detect whether or not a byte is present in the FIFO. 

• In IrDA mode, use THR_EMPTY mapped as bit 7 of the Line Status Register (LSR) to 

detect whether or not a byte is present in the FIFO. 


46


6.10 Universal Asynchronous Receiver/Transmitter (UART) Advisories 

Advisory 

UART_1 


SPRZ209C 

Falling Edge on UART2.RX May Cause a Wake-up Event on OMAP5912 

Details: A falling edge on UART2.RX may cause a wake-up event on OMAP5912. In order to prevent 

this wakeup, it is recommended that UART2.RX be set to high. 

Workaround: Use DIS_PERIPH_NREQ in ULPD SOFT_DISABLE_REQ_REG[3] to disable an unwanted 

request caused by a falling edge on UART2.RX (ZZG ball R9; ZDY ball U4). To enable or 

disable wake-up completely, set SYSC[2] to 1 or 0, respectively. This will enable or disable 

any method of wake-up. 

To enable or disable individual methods when SYSC[2] is 1, set the WER[0:6] register to 1 to 

enable the specific event and 0 to disable the specific event. 

The events are: 

• CTS activity bit 0 

• DSR activity 

• RI activity 

• DCD activity 

• RX/IRRX activity 

• RHR interrupt 

• Receive Line Status interrupt bit 6 


47


Advisory 

UART_2 


SPRZ209C 

Disabled UART’s FIFO Interrupts DMA Channel 

Details: When the UART is disabled (MDR1 = 0x7), its FIFO can interrupt the DMA channel upon 

setting register bits[2:0] in the Supplementary Control Register (SCR). This can cause 

problems if the SCR[2:0] bits are set prior to setting the trigger thresholds. 

Workaround: Set the DMA just before setting the Mode Select in the MDR1 register to avoid filling the FIFO 

in the UART. 


Advisory 

UART_4 


Receive Overrun Not Reset on an Early Read of LSR 

Details: During receive overrun (LSR[1] = RX_OE), if a read of the Line Status Register (LSR) is done 

within one baud clock period after the overrun happens, the LSR is not cleared and the 

Overrun Interrupt remains asserted while any read of the LSR done after one baud clock 

period following the overrun event will clear the LSR and deassert the Overrun Interrupt. 

Workaround: During the interrupt sequence, one should loop for at least one baud clock period before 

reading the Line Status Register (LSR). 


48


6.11 Emulation Advisories 

Advisory 

EMU_1 


SPRZ209C 

32-bit Peripheral Register Access Through the Debugger Between Two 16-Bit Application 

Reads May Corrupt the On-going Application 

Details: Getting visibility of 32-bit peripheral registers from the debugger may corrupt the on-going 

application read sequence if the debugger access takes place between two 16-bit application 

reads. 

Workaround: There is no workaround. Ensure no debugger access is performed to such 32-bit peripheral 

registers between the 16-bit application accesses. 


Advisory 

EMU_2 


GDD Does Not Support Execution Suspension in Case of CPU 

SUSPEND and FREE Bit = 0 

Details: The GDD continues running even if suspended by the processor for both FREE = 0 and 

FREE = 1. 



Advisory 

EMU_3 


Emulation Access to IT_STATUS_REG Clears Bits 

Details: Debugger read access to IT_STATUS_REG (offset 0x14) clears status bits 2,1, and 0. The 

ULPD peripheral does not detect the initiator of the read access. This results in a debugger 

read access which impacts the register content in the same manner as in a normal application 

context. 

Workaround: Emulation reads must preserve the application state. 


49


Advisory 

EMU_4 


SPRZ209C 

Default TDO State During Reset is Unpredictable 

Details: Some flip flops which control the enable of the TDO do not initialize properly if there is no 

rising edge on TRST. This can be an issue if several JTAG ports are daisy-chained in a design 

and TDO is left floating. 



50


6.12 Specially Optimized Screen Interface (SoSSI) Advisories 

Advisory 

SOSSI_1 


SPRZ209C 

SoSSI Match Interrupt 

Details: The SoSSI match output is not registered, which causes the MPU interrupt handler to capture 

glitches regardless of the interrupt sensitivity configuration. 

Workaround: There is no software workaround. 


Advisory 

SOSSI_2 


SoSSI CPriority 

Details: With the Double_FIFO feature, the SoSSI does allow two data transfers with independent 

parameters (display data type, byte count, and reordering) to be performed. 

If one FIFO pixel data transfer is on-going and the Double_FIFO feature is enabled, the 

command data transfer to another FIFO is allowed to override the pixel data transfer 

depending of the CPriority bit value in DIF003_INIT2 register. 

If the CPriority bit is set to 1 and command (A0 = 0) is sent during the pixel data transfer, the 

pixel data transfer should be aborted and the command should be sent to display. However, 

due to a problem with the SoSSI peripheral, the command will be sent but the pixel data 

transfer is not aborted. The rest of the pixel data is sent after the command. After the pixel 

data transfer is completed, the SoSSI will lock up. 

If the CPriority bit is set to 0 and command (A0 = 0) is sent during the pixel data transfer, the 

pixel data transfer should be completed and the command should be sent to display after that. 

However, due to a problem with SoSSI peripheral, the command will be sent immediately and 

after which, undefined amount 0x00 data will be sent. 

Workaround: Software has to ensure that the pixel data transfer in one FIFO is completed before initiating 

command transfer to another FIFO. 


51


6.13 Compact Camera Port (CCP) Advisories 

Advisory 

CCP_1 


SPRZ209C 

Compact Camera Port Software Reset Does Not Reset Attn-Signal Registers 

Details: The Compact Camera Port (CCP) includes an Attn status output signal,which is used as a 

DMA request. If the Attn signal is enabled, it gets asserted when the CCP FIFO receives a 4 x 

32-bit of data. The Attn signal stays active until the 4 x 32-bit data is read from the FIFO. If the 

FIFO after reads contain another 4 x 32-bit block of data, the Attn signal gets asserted again. 

When CCP software reset (partial reset, not intended to reset the whole CCP) is applied, the 

registers defining Attn-signal state should be reset, but they are not. 

If software reset is applied when Attn signal is active, it will stay active after software reset is 

completed. As a result, it is possible for the buffer to be configured as an input and ignore the 

gating event. 

Workaround: The software needs to read the CCP FIFO four times after every software reset. This will 

disable the Attn signal. Even if Attn signal is not active, this can be done without disturbing the 

functionality of the CCP. 


Advisory 

CCP_2 


CCP DMA Does Not Operate as Expected 

Details: The CCP peripheral has an internal status output signal, which in OMAP5912, is used as a 

DMA request. This signal should be asserted when the CCP internal FIFO has received 

4 x 32-bit data. The signal stays active until all 4 x 32-bit data has been read from the FIFO. 

However, in OMAP5912, a false status signal comes after the final (fourth word) read if 

3 words remain in the CCP FIFO. The false status does not occur when 0, 1, or 2 words 

remain in the CCP FIFO after the fourth word is read. 

This false behavior can be hidden, if new data from the camera arrives before the DMA reads 

the fourth word. If new data has not arrived, then the DMA will read 3 words and 1 word of 

zeros. 

Workaround(s): 1. If the data format does not contain zero-words, then corrupt data can be removed by 

software if the reduced bandwidth is acceptable. 

2. Implement a check of data size between received data from the camera and data written 

to memory. If the sizes do not match, then the false status has occurred and the picture 

has become corrupted. 


52


6.14 32-kHz Oscillator Advisories 

Advisory 

OSC_1 


SPRZ209C 

32-kHz Oscillator Does Not Power Down in Deep Sleep Mode 

Details: The 32-kHz oscillator is always powered up regardless of the Reset_Mode value. In particular, 

if an external 32-kHz clock is provided to OMAP5912, the power down of the oscillator is not 

configured so that active circuitry in the oscillator would be cut off. This behavior is noticeable 

in deep sleep mode as the oscillator current consumption is in the range of 5 µA. See 

Figure 7. 

PWRDN 

VOLTAGE 

ON XI 

VOLTAGE 

ON XO 

APPROXIMATE 

WORST-CASE 

CURRENT 

MAGNITUDE 

ON XI 

APPROXIMATE 

WORST-CASE 

CURRENT 

MAGNITUDE 

ON XO 

TOTAL 

CURRENT 

CONSUMPTION 

L VSS VSS 50 nA 5 µA 5 µA H 

L VDD VSS 50 nA 5 µA 5 µA H 

L VSS VDD 50 nA 100 µA 100 µA L 

L VDD VDD 50 nA 100 µA 100 µA L 

H VSS VSS 1 nA 1 nA 1 nA L 

H VDD VSS 1 nA 1 nA 2 nA H 

H VSS VDD 1 nA 100 µA 100 µA L 

H VDD VDD 1 nA 100 µA 100 µA H 

Figure 7. Oscillator Current Consumption 

Workaround: Make sure that if the 32-kHz oscillator is not required, the OSC32K_PWRDN bit is set to one 

in the RTC Oscillator Register (RTC_OSC_REG). 


Y 

53


Advisory 

OSC_2 


SPRZ209C 

32-kHz Oscillator Does Not Work Properly in OMAP5912 

Details: Coupling between the CLK32K_OUT (ZZG ball R13; ZDY ball U12) signal and oscillator XI 

creates a parasitic oscillation mode, preventing the oscillator from working properly. 

Workaround: Connect an external CMOS 32-kHz clock onto CLK32K_IN (ZZG ball P13; ZDY ball T11) 

instead of using the on-chip 32-kHz oscillator. 


54


6.15 Serial Peripheral Interface (SPI) Advisories 

Advisory 

SPI_1 


SPRZ209C 

SPI Slave Not Supported on SPIF.DOUT on ZZG Ball R18 (ZDY Ball N17) 

Details: The 3-state control for SPIF.DOUT on ZZG ball R18 (ZDY ball N17) (Mode 011) is tied 

active-low when the SPIF.DOUT is chosen in the pin-multiplexing. In addition, the input buffer 

on ZZG ball R18 (ZDY ball N17) is not routed to the SPI, which prevents slave operation. 

Workaround: Possible workaround for the SPI in Slave mode is to use SPIF.DOUT on ZZG ball W21 (ZDY 

ball R15). 


Advisory 

SPI_2 


SPI Not Able to Receive the First Data While Waking up From Sleep Mode 

Details: While waking up from sleep mode by a data sent to the SPI (GPIO wake-up), the functional 

clock of the SPI is available far after the end of the data transmission, resulting in the data not 

being latched by the SPI. 

Workaround: Resend the data after the functional clock is available at the SPI module. 


Advisory 

SPI_3 


SPI Outputs are not Controlled Correctly 

Details: The SPI output buffer’s direction (GZ) is connected to the SPI’s output MODE [or inv(MODE)] 

for the SPIF.DIN pin. This signal is static and it defines master/slave operations in the 

OMAP5912 SPI peripheral. Because this signal is static and is directly connected to GZ’s SPI 

outputs, the SPI peripheral will not release the bus correctly. Multi-point connections on the 

SPI peripheral are then limited. 

The correction is to use the dynamic signal (TSPDOEN) provided by the SPI module as 

direction control for the SPI output buffer. TSPDOEN places the output buffer in high 

impedance while no shifting operation is in progress. 

Workaround: If OMAP5912’s SPI peripheral is to act as a master, make sure there are no other master SPIs 

in the system in order to avoid bus contentions. 

TI does intend to correct this functionality on a future revision of OMAP5912. 

55


Advisory 

SPI_4 


Details: The SPI peripheral does not support 8-bit accesses. 

SPRZ209C 

SPI Module Does Not Support 8-Bit Accesses 

Workaround: If 8 bits of data must be transferred, the data must be packed in a16-bit structure. 


56


6.16 Ultra Low-Power Device (ULPD) Advisories 

Advisory 

ULPD_1 


Details: ULPD has the following reset scheme: 

SPRZ209C 

ULPD Analog Cell Configuration are Reset After a MPU Peripheral Reset 

• Internal Registers are reset by ULPD power-up reset. 

• ARM registers are reset by ULPD MPU Peripheral Reset. 

As the ULPD is responsible for OMAP3.2 reset generation (including the MPU peripheral 

reset), if the MPU warm reset or any of the watchdog resets (32 kHz or secure watchdog) is 

active, the MPU peripheral reset is activated and the analog set-up time registers are reset. 

Therefore, when the FSM goes out of Deep Sleep, the set-up counters are loaded with the 

reset value of the analog set-up time registers instead of the optimized value previously 

programmed by the user, this causes wake-up latency penalty. 

Note that PWR_CTRL_REG[12] (DSP isolation control) and RESET_STATUS[3:0] are not 

affected by this behavior. 

Workaround: Software should account for the analog set-up time cell latencies. 


57


6.17 Multichannel Serial Interface (MCSI) Advisories 

Advisory 

MCSI_1 


SPRZ209C 

Late Generation of TX DMA Request in the MCSI 

Details: Multiple DSP-based DMA mode transmits and receives on the MCSI peripherals do not work 

properly. The MCSI peripheral is re-transmitting the last word of data that it had transmitted in 

the previous DMA Frame. 

On the first DMA frame that the MCSI transmits, the MCSI peripheral generates a tx_dma_req 

just prior to asserting the frame sync signal. It then generates the proper binary stream. 

On the second and subsequent DMA frames transmitted, the MCSI does not generate a 

tx_dma_req prior to asserting the frame sync signal and the last data from the previous DMA 

frame is re-transmitted by the MCSI. Then, a tx_dma_req is asserted and the character that 

was supposed to be first transmitted is loaded and shifted through the MCSI. 

Subsequently, the first dma request results in the transmission of the second character by the 

MCSI. The proper number of tx DMA requests is generated. When the last DMA request is 

generated, the MCSI loads the transmit buffer but does not transmit this character until the 

next DMA frame when the same incorrect sequence of data retrieval and transmission by the 

MCSI TX DMA process is repeated. 

Workaround: Write the first data under DSP CPU control to the TX register before the DMA transfer. This is 

to ensure that the correct data is sent. Next, the DMA must be programmed to send the 

remaining elements 2 through N after that. 


58


6.18 Multichannel Buffered Serial Port (McBSP) Advisories 

Advisory 

MCBSP_1 


SPRZ209C 

McBSP3 3-Pin Operation Versus 4-Pin Operation Configuration 

Details: Two OMAP5912 configuration bits in Module Configuration Register 0 (MOD_CONF_CTRL_0) 

are used for setting up McBSP3, as shown below: 

• MOD_CONF_CTRL_0[28] should control the McBSP3 FSYNC output mode (McBSP3 in 

3-pin or 4-pin mode) 

− 3-pin mode: FXOUT is connected to FSRIN. FSXIN is tied low. 

− 4-pin mode: FSRIN = FSXIN is connected to FSXOUT high-impedance output buffer. 

• MOD_CONF_CTRL_0[19] should control the source for McBSP3 CLKS (either DSPXOR 

or DSPPER) 

In OMAP5912, MOD_CONF_CTRL_0[28] does not work and MOD_CONF_CTRL_0[19] 

controls both McBSP3 modes and OCP input clock (McBSP interface clock). 

• MOD_CONF_CTRL_0[19] = 0: 

− McBSP3 is in 3-pin mode 

− Interface clock: DSPXOR 

• MOD_CONF_CTRL_0[19] = 1: 

− McBSP3 is in 4-pin mode 

− Interface clock: DSPPER 

Note that the access time to the peripheral will change depending on 3-pin or 4-pin usage. 

If McBSP3 is configured with CLKSM = 1 and CLKME = 0, the input clock of the sample rate 

generator (SRG) will be either the DSPXOR_CK (system clock) or DSPPER_CK 

(programmable) depending on MOD_CONF_CTRL_0[19]. This means the dividers in the SRG 

must be configured differently to achieve the same frequency in 3-pin versus 4-pin mode. 

Workaround: When configuring the McBSP3 in 3-pin or 4-pin mode, make sure the correct access time to 

the peripheral is accounted for. 


59


6.19 Dual-Mode Timers Advisories 

Advisory 

DM_TIMER_1 

Revision(s) Affected: All revisions 

SPRZ209C 

Dual-Mode Timer Peripherals May Not Detect Incoming Events 

Details: Due to internal metastability issues, the dual-mode timer peripherals, when used in 

event-capture mode, may not detect incoming events. 



60


7 OMAP5912 Device/System Level Advisories 

7.1 System Advisories 

Advisory 

SYS_1 


SPRZ209C 

Pulldown on the UWIRE.SDI Pin Needs to be Disabled by Software to Save Power 

Details: On the UWIRE.SDI pin, there is a pulldown active by default. The inactive level of the signal is 

high. Therefore, the pulldown needs to be disabled in software in order to save power. 

Workaround: Write 0x0000EAEFh to the COMP_MODE_CTRL_0 register (base address: FFFE:1000 + 

offset 0x0C). 

Set bit 18 (CONF_PDEN_WIRE_SDI_R) of the PULL_DWN_CTRL_1 register (offset: 

FFFE:1000 + offset 0x44) to 1. 

TI does not plan to correct this functionality on all OMAP5912 revisions. 

Advisory 

SYS_2 


When Disabled, the OMAP Peripheral Clock Prevents the OMAP5912 From Going Into 

Deep Sleep 

Details: If the peripheral clock is disabled, OMAP5912 cannot go into deep sleep when executing the 

Arm Idle instruction because the TC1_IDLEACK do not rise since it is synchronous to the 

peripheral clock. The Idle request is not acknowledged. 

If the peripheral clock is enabled prior to the execution of the Arm Idle instruction, the chip 

goes correctly in deep sleep. 

Workaround: If the peripheral clock is enabled (via EN_PERCK of ARM_IDLECT2) prior to the execution of 

the Arm Idle instruction, the chip goes correctly in deep sleep. 

TI does not plan to correct this functionality on all OMAP5912 revisions. 

61


Advisory 

SYS_3 


SPRZ209C 

OMAP5912 Gated Outputs Forced to 0 

Details: Some outputs can be forced to 0 in the case of battery failure or external event (falling edge) 

on GPIO9 or MPUIO3. The outputs that exhibit this feature are listed in the OMAP5912 

Applications Processor Data Manual (literature number SPRS231) and are classified as either 

“gated1” or “gated2” outputs. As a gating is defined to tie pins to the fixed value 0 regardless 

of the mode for which they are configured, gating also controls the 3-state buffer output 

enable. As a result, the buffer can be configured as an input, which causes it to ignore the 

gating event. 

Workaround: When configuring OMAP5912 inputs/outputs, the user should make sure that the I/O which 

should be forced to 0 in case of battery failure or event on GPIO9/MPUIO3 has been 

configured before as output. 


Advisory 

SYS_4 


If BVLZ is Not Configured, the Corresponding Interrupt Must be Masked 

Details: On OMAP5912, the UART3.CTS, UART1.DSR, and the MMC/SDIO2’s MMC.DATDIR1 

signals have been multiplexed with BVLZ (battery low-level external interrupt). 

If BVLZ is not used, the user has to make sure that the corresponding interrupt mask is set 

(MPU Level 1 Interrupt Mapping, IRQ_3) and that bit 3 of the ULPD’s POWER_CTRL_REG, 

which controls RST_HOST_OUT of the ULPD, is cleared to 0. 

Workaround: Mask SCV3OMAP3/PIIRQINPUTN 3 and clear bit 3 of the ULPD’s POWER_CTRL_REG to 0 

(default value at reset is 1). 


62


Advisory 

SYS_5 


SPRZ209C 

Configuration Registers FUNC_MUX_CTRL_10[8:3] and FUNC_MUX_CTRL_9[11:9] 

Reset Values Do Not Reflect M8, L3, AA20 Configuration in Reset Mode 1 

Details: The following changes have been implemented in OMAP5912: 

• Reset values in reset_mode1 of ZZG balls M8, L3, AA20 (ZDY balls K2, J1, and N12, 

respectively) have been changed inside the configuration block. 

Default muxing mode is now 7 (0111 in binary) for the 3 balls below: 

• ZZG ball M8 (ZDY ball K2): configured as GPIO_60 instead of NFBE_1 

• ZZG ball L3 (ZDY ball J1): configured as GPIO_59 instead of NFBE_0 

• ZZG ball AA20 (ZDY ball N12): configured as GPIO_41 instead of NRESETOUT 

This is not reflected inside FUNC_MUX_CTRL_10[8:3] and FUNC_MUX_CTRL_9 [11:9] (with 

reset values of 000000 and 000, respectively, instead of 111111 and 111). 

Workaround: Special care must be taken while reprogramming the pads’ configuration when using reset 

mode 1. In reset mode 1, FUNC_MUX_CTRL_10[8:3] needs to be programmed to 111111 and 

FUNC_MUX_CTRL_9 [11:9] to 111 in order to keep their intended reset value before new pad 

configurations. 


63


8 Documentation Support 

For device-specific data sheets and related documentation, visit the TI web site at: http://www.ti.com 

For further information regarding the OMAP5912, please refer to: 

• OMAP5912 Applications Processor Data Manual (literature number SPRS231) 

For additional information, see the latest versions of: 

• TMS320C55x DSP Functional Overview (literature number SPRU312) 

• TMS320C55x DSP CPU Reference Guide (literature number SPRU371) 

• TMS320C55x DSP Mnemonic Instruction Set Reference Guide (literature number SPRU374) 

• TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature number SPRU375) 

• TMS320C55x DSP CPU Programmer’s Reference Supplement (literature number SPRU652) 

SPRZ209C 

64

IMPORTANT NOTICE 

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, 

enhancements, improvements, and other changes to its products and services at any time and to discontinue 

any product or service without notice. Customers should obtain the latest relevant information before placing 

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms 

and conditions of sale supplied at the time of order acknowledgment. 

TI warrants performance of its hardware products to the specifications applicable at the time of sale in 

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI 

deems necessary to support this warranty. Except where mandated by government requirements, testing of all 

parameters of each product is not necessarily performed. 

TI assumes no liability for applications assistance or customer product design. Customers are responsible for 

their products and applications using TI components. To minimize the risks associated with customer products 

and applications, customers should provide adequate design and operating safeguards. 

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, 

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process 

in which TI products or services are used. Information published by TI regarding third-party products or services 

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. 

Use of such information may require a license from a third party under the patents or other intellectual property 

of the third party, or a license from TI under the patents or other intellectual property of TI. 

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without 

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction 

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for 

such altered documentation. 

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that 

product or service voids all express and any implied warranties for the associated TI product or service and 

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. 

Following are URLs where you can obtain information on other Texas Instruments products and application 

solutions: 

Products Applications 

Amplifiers amplifier.ti.com Audio www.ti.com/audio 

Data Converters dataconverter.ti.com Automotive www.ti.com/automotive 

DSP dsp.ti.com Broadband www.ti.com/broadband 

Interface interface.ti.com Digital Control www.ti.com/digitalcontrol 

Logic logic.ti.com Military www.ti.com/military 

Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork 

Microcontrollers microcontroller.ti.com Security www.ti.com/security 

Telephony www.ti.com/telephony 

Video & Imaging www.ti.com/video 

Wireless www.ti.com/wireless 

Mailing Address: Texas Instruments 

Post Office Box 655303 Dallas, Texas 75265 

Copyright © 2004, Texas Instruments Incorporated

OMAP5912 Applications Processor Silicon Errata ... - Curtin University

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?