Intel 45nm Process Overview - UCSB CAD & Test

A 45nm Logic Technology with High-k + Metal
Gate Transistors, Strained Silicon, 9 Cu
Interconnect Layers, 193nm Dry Patterning, and
100% Pb-free Packaging
K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M.
Buehler, A. Cappellani, R. Chau * , C.-H. Choi, G. Ding, K. Fischer, T. Ghani,
R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He # , J. Hicks # , R. Heussner,
D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee,
H. Liu, J. Maiz # , B. McIntyre, P. Moon, J. Neirynck, S. Pae # , C. Parker,
D. Parsons, C. Prasad # , L. Pipes, M. Prince, P. Ranade, T. Reynolds,
J. Sandford, L. Shifren % , J. Sebastian, J. Seiple, D. Simon, S. Sivakumar,
P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki
Portland Technology Development, * CR, # QRE, % PTM
Intel Corporation

Outline
• Introduction
• Process Features
• Transistors
• Interconnects
• Manufacturing
• Conclusions
2

Introduction
• SiON scaling running out of atoms
• Poly depletion limits inversion T OX scaling
Electrical (Inv) Tox (nm)
10
1
Poly
SiON
Silicon
350nm 250nm 180nm 130nm 90nm 65nm
1000
100
10
1
0.1
0.01
Gate Leakage (Rel.)
3

High-k + Metal Gate Benefits
• High-k gate dielectric
– Reduced gate leakage
– T OX scaling
• Metal gates
– Eliminate polysilicon depletion
– Resolves V T pinning and poor mobility
for high-k dielectrics
4

High-k + Metal Gate Challenges
• High-k gate dielectric
– Poor mobility, V T pinning due to soft
optical phonons
– Poor reliability
• Metal gates
– Dual bandedge workfunctions
– Thermal stability
– Integration scheme
5

Outline
• Introduction
• Process Features
• Transistors
• Interconnects
• Manufacturing
• Conclusions
6

Process Features
• 45 nm Groundrules
• 193 nm Dry Lithography
• High-K + Metal Gate Transistors
• 3 RD Generation Strained Silicon
• Trench Contacts with Local Routing
• 9 Cu Interconnect Layers
• 100% Lead-free Packaging
7

Process Features
• 45 nm Groundrules
• 193 nm Dry Lithography
• High-K + Metal Gate Transistors
• 3 RD Generation Strained Silicon
• Trench Contacts with Local Routing
• 9 Cu Interconnect Layers
• 100% Lead-free Packaging
8

45nm Design Rules
Layer Pitch (nm) Thick (nm) Aspect Ratio
Isolation 200 200
Contacted Gate 160 60
--
Metal 1 160 144
1.8
Metal 2 160 144
1.8
Metal 3 160 144
1.8
Metal 4 240 216
1.8
Metal 5 280 252
1.8
Metal 6 360 324
1.8
Metal 7 560 504 1.8
Metal 8 810 720 1.8
Metal 9 30.5μm 7μm
0.4
~0.7x linear scaling from 65nm
--
9

Contacted Gate Pitch
• Transistor gate pitch of 160 nm continues
0.7x per generation scaling
Contacted Gate Pitch (nm)
1000
100
Pitch
250nm 180nm 130nm 90nm 65nm 45nm
Technology Node
0.7x every
2 years
Tightest contacted gate pitch reported for 45 nm generation

SRAM Cells
• 0.346 μm 2 and 0.382 μm 2 SRAM cells
– Optimize density and power/performance
SRAM Cell Size ( μm 2 )
10
1
0.1
250nm 180nm 130nm 90nm 65nm 45nm
Technology Node
0.5x every
2 years
Transistor density doubles every two years
11

SRAM Array Density
• SRAM array density achieves 1.9 Mb/mm 2
SRAM Array Density (Mb/mm 2 )
– Includes row/column drivers and other circuitry
10.0
1.0
0.1
1.9 Mb/mm 2
90nm 65nm 45nm
Array density scales at ~2X per generation
12

Outline
• Introduction
• Process Features
• Transistors
• Interconnects
• Manufacturing
• Conclusions
13

Transistor Process Flow
• Key considerations
– Integrate hafnium-based high-k dielectric,
dual metal gate electrodes, strained silicon
– Thermal stability of metal gate electrodes
• High-k First, Metal Gate Last
– Metal gate deposition after high temperature
anneals
– Integrated with strained silicon process
– Transistor mask count same as 65nm
14

Transistor Process Flow
Dummy
Polysilicon
n-ext n-ext p-ext p-ext
STI
High-k High-k
p-well N-well
Standard process except for ALD high-k
15a

Transistor Process Flow
N+ N+
ILD0
STI
SiGe
p-well N-well
e-SiGe & S/D, Thermal anneal, ILD0 deposition
SiGe
15b

Transistor Process Flow
N+ N+
STI
SiGe
p-well N-well
Poly Opening Polish
SiGe
15c

Transistor Process Flow
N+ N+
STI
SiGe
p-well N-well
Dummy Poly removal
SiGe
15d

Transistor Process Flow
N+ N+
STI
SiGe
p-well N-well
PMOS WF Metal deposition
SiGe
15e

Transistor Process Flow
N+ N+
STI
SiGe
p-well N-well
PMOS WF Metal patterning
SiGe
15f

Transistor Process Flow
N+ N+
STI
SiGe
p-well N-well
NMOS WF Metal deposition
SiGe
15g

Transistor Process Flow
N+ N+
Al fill
STI
SiGe
p-well N-well
Metal Gate trenches filled with low resistance Al
SiGe
15h

Transistor Process Flow
N+ N+
STI
SiGe
p-well N-well
Metal Gate Polish
SiGe
15i

Transistor Process Flow
N+ N+
Low Resistance Al Fill
NMOS WF PMOS WF
STI
SiGe
High-k High-k
p-well N-well
SiGe
High-k + Metal gate transistor formation complete
15j

Transistor Features
• 35 nm min. gate length
• 160 nm contacted gate
pitch
• 1.0 nm EOT Hi-K
• Dual workfunction
metal gate electrodes
• 3 RD generation of
strained silicon
16

Gate Leakage
• Gate leakage is reduced >25X for NMOS
and 1000X for PMOS
Normalized Gate Leakage
100
10
1
0.1
0.01
0.001
HiK+MG 45nm
HiK+MG 45nm
0.0001
0.00001
PMOS
NMOS
-1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2
65nm: Bai, 2004 IEDM
SiON/Poly 65nm
VGS (V)
SiON/Poly 65nm
17

Threshold Voltage (V)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Optimal Workfunction Metals
• Excellent V T rolloff and DIBL
|VDS|= 0.05V
|VDS|= 1.0V
30 35 40 45 50 55 60
LGATE (nm)
NMOS -0.05
PMOS
Threshold Voltage (V)
0.00
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
-0.45
-0.50
|VDS|= 0.05V
|VDS|= 1.0V
30 35 40 45 50 55 60
LGATE (nm)
18

3 RD Generation Strained Silicon
• Increased Ge
fraction
– 90 nm: 17% Ge
– 65 nm: 23% Ge
– 45 nm: 30% Ge
• SiGe closer to
channel
19

IOFF (nA/μm)
NMOS I DSAT vs. I OFF
1000
100
10
1
VDD = 1.0V
90 nm
90nm: Mistry 2004 VLSI
65nm: Tyagi, 2005 IEDM
65 nm
0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
IDSAT (mA/μm)
1.36 mA/μm at I OFF = 100 nA/μm
12% better than 65 nm
160 nm
20

IOFF (nA/μm)
PMOS I DSAT vs. I OFF
1000
100
10
1
VDD = 1.0V
90 nm
65 nm
90nm: Mistry 2004 VLSI
65nm: Tyagi, 2005 IEDM
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
IDSAT (mA/μm)
1.07 mA/μm at I OFF = 100 nA/μm
51% better than 65 nm
160 nm
21

Transistor Performance vs. Gate Pitch
IDSAT (mA/μm)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1000
1.0V, 100 nA/μm
90nm: Mistry, 2004 VLSI
65nm: Tyagi, 2005 IEDM
Gate Pitch
(Generation)
NMOS
PMOS
320nm
(90nm)
220nm
(65nm)
Contacted Gate Pitch (nm)
160nm
(45nm)
Simultaneous performance and density improvement
100
22

Ring Oscillator Performance
DELAY PER STAGE (pS)
9
8
7
6
5
4
3
Fanout = 2
65nm @ 1.2V
45nm @1.1V
10 100 1000 10000
IOFFN + IOFFP (nA/um)
FO=2 delay of 5.1 ps at I OFFN = I OFFP = 100 nA/μm
23% better than 65 nm at the same leakage
23

Transistor Reliability Challenges
• Defect types in SiO 2 have been studied
for decades
• New defect types for high-k need to be
suppressed
• T INV scaled ~0.7X relative to 65 nm
– Need to support 30% higher E-field
24

Transistor Reliability - TDDB
TDDB (sec)
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
1.E+02
SiON/Poly
65nm
65nm: Bai, 2004 IEDM
45nm
HK+MG
4 6 8 10 12 14 16
Field (MV/cm)
45nm High-k + Metal Gate supports 30% higher E-field
25

Transistor Reliability: Bias Temperature
PMOS NBTI
Vt increase (mV)
45 nm Hi-k + MG supports
50% higher E-field
50
40
30
20
10
0
SiON/Poly
65nm
Vt increase (mV)
5 7 9 11 13
SiO2 equivalent EField (MV/cm)
50
40
30
20
10
0
SiON/Poly
65nm
PMOS NBTI
45nm HK+MG
5 7 9 11 13
SiO2 equivalent EField (MV/cm)
NMOS PBTI
45nm HK+MG
NMOS PBTI
45 nm Hi-k + MG supports
15% higher E-field
65nm: Bai, 2004 IEDM
26

Outline
• Introduction
• Process Features
• Transistors
• Interconnects
• Manufacturing
• Conclusions
27

Interconnects
• Metal 1-3 pitches
match transistor
pitch
• Graduated upper
level pitches
optimize density &
performance
• Lower layer SiCN
etch stop layer
thinned 50% relative
to 65 nm
• Extensive use of
low-k ILD
CDO
CDO
CDO
CDO
CDO
CDO
CDO
SiO 2
MT8
MT7
MT6
MT5
MT4
MT3
MT2
MT1
28

Metal 9: ReDistribution Layer (RDL)
• Metal 9 RDL: 7um thick with polymer ILD
MT8
MT7
– Improved on-die power distribution
Metal 9
Cu Bump
7 μm
Polymer ILD
29

100% Lead Free Packaging
• Environmental benefit, lower SER
Cu Pad
Pb/Sn Solder
Pb Bump
90 nm
Cu Pad
Pb/Sn Solder
Cu Bump
65 nm
Cu Pad
Sn/Ag/Cu Solder
Cu Bump
45 nm
30

Outline
• Introduction
• Process Features
• Transistors
• Interconnects
• Manufacturing
• Conclusions
31

153Mb SRAM Test Vehicle
• Process learning vehicle demonstrates
– High yield
– High performance
– Stable low voltage operation
0.346 μm2 SRAM Cell
>1 billion transistors
Fully functional Jan’06
1.3V |***************************** .
1.2V |************************** .
1.1V |************************* .
1.0V |********************** .
0.9V |**************** . .
2GHz
3.8GHz
4.7GHz
0.8V |****** . . .
+---------+---------+---------+
1.8GHz 2.3GHz 3.2GHz 5.3GHz
32

Multiple Microprocessors
Single Core
Dual Core
Quad Core
33

Defect Reduction Trend
• Mature yield demonstrated 2 years after 65 nm
Defect
Density
(log scale)
130 nm 90 nm 65 nm 45 nm
2000 2001 2002 2003 2004 2005 2006 2007 2008

Defect Reduction Trend
• Mature yield demonstrated 2 years after 65 nm
• Matched yield in 2 ND Fab – Copy Exactly!
Defect
Density
(log scale)
130 nm 90 nm 65 nm 45 nm
F32
2000 2001 2002 2003 2004 2005 2006 2007 2008

Conclusions
• A 45 nm technology is described with
– Design rules supporting ~2X improvement in transistor density
– 193nm dry lithography at critical layers for low cost
– Trench contacts supporting local routing
– 8 standard Cu interconnect layers with extensive use of low-k
– Thick Metal 9 Cu RDL with polymer ILD
• High-k + Metal gate transistors implemented for the first
time in a high volume manufacturing process
– Integrated with 3 RD generation strained silicon
– Achieve record drive currents at low I OFF and tight gate pitch
• The technology is already in high volume manufacturing
– High yields demonstrated on SRAM and 3 microprocessors
– High yields demonstrated in two 300mm fabs
35

Acknowledgements
• The authors gratefully acknowledge the
many people in the following
organizations at Intel who contributed
to this work:
– Portland Technology Development
– Quality and Reliability Engineering
– Process & Technology Modeling
– Assembly & Test Technology Development
36

For further information on Intel's silicon technology,
please visit our Technology & Research page at
www.intel.com/technology
37