Intel 45nm Process Overview - UCSB CAD & Test

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3 RD Generation Strained Silicon • Increased Ge fraction – 90 nm: 17% Ge – 65 nm: 23% Ge – 45 nm: 30% Ge • SiGe closer to channel 19
IOFF (nA/μm) NMOS I DSAT vs. I OFF 1000 100 10 1 VDD = 1.0V 90 nm 90nm: Mistry 2004 VLSI 65nm: Tyagi, 2005 IEDM 65 nm 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 IDSAT (mA/μm) 1.36 mA/μm at I OFF = 100 nA/μm 12% better than 65 nm 160 nm 20
Page 1 and 2: A 45nm Logic Technology with High-k
Page 3 and 4: Introduction • SiON scaling runni
Page 5 and 6: High-k + Metal Gate Challenges •
Page 7 and 8: Process Features • 45 nm Groundru
Page 9 and 10: 45nm Design Rules Layer Pitch (nm)
Page 11 and 12: SRAM Cells • 0.346 μm 2 and 0.38
Page 13 and 14: Outline • Introduction • Proces
Page 15 and 16: Transistor Process Flow Dummy Polys
Page 17 and 18: Transistor Process Flow N+ N+ STI S
Page 25 and 26: Transistor Features • 35 nm min.
Page 27: Threshold Voltage (V) 0.50 0.45 0.4
Page 31 and 32: Transistor Performance vs. Gate Pit
Page 33 and 34: Transistor Reliability Challenges
Page 35 and 36: Transistor Reliability: Bias Temper
Page 37 and 38: Interconnects • Metal 1-3 pitches
Page 39 and 40: 100% Lead Free Packaging • Enviro
Page 41 and 42: 153Mb SRAM Test Vehicle • Process
Page 43 and 44: Defect Reduction Trend • Mature y
Page 45 and 46: Conclusions • A 45 nm technology
Page 47: For further information on Intel's

Intel 45nm Process Overview - UCSB CAD & Test

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