Intel 45nm Process Overview - UCSB CAD & Test
Intel 45nm Process Overview - UCSB CAD & Test
Intel 45nm Process Overview - UCSB CAD & Test
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Transistor Features<br />
• 35 nm min. gate length<br />
• 160 nm contacted gate<br />
pitch<br />
• 1.0 nm EOT Hi-K<br />
• Dual workfunction<br />
metal gate electrodes<br />
• 3 RD generation of<br />
strained silicon<br />
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