Intel 45nm Process Overview - UCSB CAD & Test

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Gate Leakage • Gate leakage is reduced >25X for NMOS and 1000X for PMOS Normalized Gate Leakage 100 10 1 0.1 0.01 0.001 HiK+MG <strong>45nm</strong> HiK+MG <strong>45nm</strong> 0.0001 0.00001 PMOS NMOS -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 65nm: Bai, 2004 IEDM SiON/Poly 65nm VGS (V) SiON/Poly 65nm 17
Threshold Voltage (V) 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 Optimal Workfunction Metals • Excellent V T rolloff and DIBL |VDS|= 0.05V |VDS|= 1.0V 30 35 40 45 50 55 60 LGATE (nm) NMOS -0.05 PMOS Threshold Voltage (V) 0.00 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 |VDS|= 0.05V |VDS|= 1.0V 30 35 40 45 50 55 60 LGATE (nm) 18
Page 1 and 2: A 45nm Logic Technology with High-k
Page 3 and 4: Introduction • SiON scaling runni
Page 5 and 6: High-k + Metal Gate Challenges •
Page 7 and 8: Process Features • 45 nm Groundru
Page 9 and 10: 45nm Design Rules Layer Pitch (nm)
Page 11 and 12: SRAM Cells • 0.346 μm 2 and 0.38
Page 13 and 14: Outline • Introduction • Proces
Page 15 and 16: Transistor Process Flow Dummy Polys
Page 17 and 18: Transistor Process Flow N+ N+ STI S
Page 25: Transistor Features • 35 nm min.
Page 29 and 30: IOFF (nA/μm) NMOS I DSAT vs. I OFF
Page 31 and 32: Transistor Performance vs. Gate Pit
Page 33 and 34: Transistor Reliability Challenges
Page 35 and 36: Transistor Reliability: Bias Temper
Page 37 and 38: Interconnects • Metal 1-3 pitches
Page 39 and 40: 100% Lead Free Packaging • Enviro
Page 41 and 42: 153Mb SRAM Test Vehicle • Process
Page 43 and 44: Defect Reduction Trend • Mature y
Page 45 and 46: Conclusions • A 45 nm technology
Page 47: For further information on Intel's

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