Intel 45nm Process Overview - UCSB CAD & Test

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Transistor Reliability - TDDB TDDB (sec) 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 SiON/Poly 65nm 65nm: Bai, 2004 IEDM 45nm HK+MG 4 6 8 10 12 14 16 Field (MV/cm) 45nm High-k + Metal Gate supports 30% higher E-field 25
Transistor Reliability: Bias Temperature PMOS NBTI Vt increase (mV) 45 nm Hi-k + MG supports 50% higher E-field 50 40 30 20 10 0 SiON/Poly 65nm Vt increase (mV) 5 7 9 11 13 SiO2 equivalent EField (MV/cm) 50 40 30 20 10 0 SiON/Poly 65nm PMOS NBTI 45nm HK+MG 5 7 9 11 13 SiO2 equivalent EField (MV/cm) NMOS PBTI 45nm HK+MG NMOS PBTI 45 nm Hi-k + MG supports 15% higher E-field 65nm: Bai, 2004 IEDM 26
Page 1 and 2: A 45nm Logic Technology with High-k
Page 3 and 4: Introduction • SiON scaling runni
Page 5 and 6: High-k + Metal Gate Challenges •
Page 7 and 8: Process Features • 45 nm Groundru
Page 9 and 10: 45nm Design Rules Layer Pitch (nm)
Page 11 and 12: SRAM Cells • 0.346 μm 2 and 0.38
Page 13 and 14: Outline • Introduction • Proces
Page 15 and 16: Transistor Process Flow Dummy Polys
Page 17 and 18: Transistor Process Flow N+ N+ STI S
Page 25 and 26: Transistor Features • 35 nm min.
Page 27 and 28: Threshold Voltage (V) 0.50 0.45 0.4
Page 29 and 30: IOFF (nA/μm) NMOS I DSAT vs. I OFF
Page 31 and 32: Transistor Performance vs. Gate Pit
Page 33: Transistor Reliability Challenges
Page 37 and 38: Interconnects • Metal 1-3 pitches
Page 39 and 40: 100% Lead Free Packaging • Enviro
Page 41 and 42: 153Mb SRAM Test Vehicle • Process
Page 43 and 44: Defect Reduction Trend • Mature y
Page 45 and 46: Conclusions • A 45 nm technology
Page 47: For further information on Intel's

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