Intel 45nm Process Overview - UCSB CAD & Test

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<strong>Process</strong> Features • 45 nm Groundrules • 193 nm Dry Lithography • High-K + Metal Gate Transistors • 3 RD Generation Strained Silicon • Trench Contacts with Local Routing • 9 Cu Interconnect Layers • 100% Lead-free Packaging 8
<strong>45nm</strong> Design Rules Layer Pitch (nm) Thick (nm) Aspect Ratio Isolation 200 200 Contacted Gate 160 60 -- Metal 1 160 144 1.8 Metal 2 160 144 1.8 Metal 3 160 144 1.8 Metal 4 240 216 1.8 Metal 5 280 252 1.8 Metal 6 360 324 1.8 Metal 7 560 504 1.8 Metal 8 810 720 1.8 Metal 9 30.5μm 7μm 0.4 ~0.7x linear scaling from 65nm -- 9
Page 1 and 2: A 45nm Logic Technology with High-k
Page 3 and 4: Introduction • SiON scaling runni
Page 5 and 6: High-k + Metal Gate Challenges •
Page 7: Process Features • 45 nm Groundru
Page 11 and 12: SRAM Cells • 0.346 μm 2 and 0.38
Page 13 and 14: Outline • Introduction • Proces
Page 15 and 16: Transistor Process Flow Dummy Polys
Page 17 and 18: Transistor Process Flow N+ N+ STI S
Page 25 and 26: Transistor Features • 35 nm min.
Page 27 and 28: Threshold Voltage (V) 0.50 0.45 0.4
Page 29 and 30: IOFF (nA/μm) NMOS I DSAT vs. I OFF
Page 31 and 32: Transistor Performance vs. Gate Pit
Page 33 and 34: Transistor Reliability Challenges
Page 35 and 36: Transistor Reliability: Bias Temper
Page 37 and 38: Interconnects • Metal 1-3 pitches
Page 39 and 40: 100% Lead Free Packaging • Enviro
Page 41 and 42: 153Mb SRAM Test Vehicle • Process
Page 43 and 44: Defect Reduction Trend • Mature y
Page 45 and 46: Conclusions • A 45 nm technology
Page 47: For further information on Intel's

Intel 45nm Process Overview - UCSB CAD & Test

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