Intel 45nm Process Overview - UCSB CAD & Test

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Ring Oscillator Performance DELAY PER STAGE (pS) 9 8 7 6 5 4 3 Fanout = 2 65nm @ 1.2V <strong>45nm</strong> @1.1V 10 100 1000 10000 IOFFN + IOFFP (nA/um) FO=2 delay of 5.1 ps at I OFFN = I OFFP = 100 nA/μm 23% better than 65 nm at the same leakage 23
Transistor Reliability Challenges • Defect types in SiO 2 have been studied for decades • New defect types for high-k need to be suppressed • T INV scaled ~0.7X relative to 65 nm – Need to support 30% higher E-field 24
Page 1 and 2: A 45nm Logic Technology with High-k
Page 3 and 4: Introduction • SiON scaling runni
Page 5 and 6: High-k + Metal Gate Challenges •
Page 7 and 8: Process Features • 45 nm Groundru
Page 9 and 10: 45nm Design Rules Layer Pitch (nm)
Page 11 and 12: SRAM Cells • 0.346 μm 2 and 0.38
Page 13 and 14: Outline • Introduction • Proces
Page 15 and 16: Transistor Process Flow Dummy Polys
Page 17 and 18: Transistor Process Flow N+ N+ STI S
Page 25 and 26: Transistor Features • 35 nm min.
Page 27 and 28: Threshold Voltage (V) 0.50 0.45 0.4
Page 29 and 30: IOFF (nA/μm) NMOS I DSAT vs. I OFF
Page 31: Transistor Performance vs. Gate Pit
Page 35 and 36: Transistor Reliability: Bias Temper
Page 37 and 38: Interconnects • Metal 1-3 pitches
Page 39 and 40: 100% Lead Free Packaging • Enviro
Page 41 and 42: 153Mb SRAM Test Vehicle • Process
Page 43 and 44: Defect Reduction Trend • Mature y
Page 45 and 46: Conclusions • A 45 nm technology
Page 47: For further information on Intel's

Intel 45nm Process Overview - UCSB CAD & Test

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