Interrupts

More documents

Recommendations

Info

Pins • INT3:0 External <strong>Interrupts</strong> 3 – 0 are alternate functions of Port D They are enabled if the I-flag in the Status Register is set (1) and the corresponding interrupt mask bit in the EIMSK is set (1). 1/4/2010 12
Pins • INT3:0 When the appropriate signal transition occurs on one of the external interrupt pins (INT7:0) an interrupt request (IRQ) is triggered and the corresponding bit in the EIFR register (Interrupt Flag Register) gets set. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. 1/4/2010 13
Page 1 and 2: Microprocessor Fundamentals Topic 1
Page 3 and 4: Interrupts • Interrupts are async
Page 5 and 6: Maskable/Non-maskable • Interrupt
Page 7 and 8: EICRA INT3 - 0 • External Interru
Page 9 and 10: EICRA INT3 - 0 1/4/2010 Exercise: W
Page 11: Pins • INT3:0 External Interrupts
Page 15 and 16: Pins • INT3:0 Exercise: I want to
Page 17 and 18: Pins • Bits 7 - 4 External Interr
Page 19 and 20: Vectors The complete vector table i
Page 21 and 22: An Example: • So, let’s work th
Page 23 and 24: An Example: We must start our progr
Page 25 and 26: An Example: We need to write the in
Page 27 and 28: An Example: We must start our progr
Page 29 and 30: An Example: Then we must write the
Page 31 and 32: What happens? • So what happens w
Page 33: Summary • In this topic we: - Bec

Interrupts

Create successful ePaper yourself

Delete template?

Save as template?