Interrupts

Microprocessor Fundamentals
Topic 16
Interrupts

Objectives
• To become familiar with interrupts on the AVR
– Maskable and non-maskable
– Initialization
– Triggers
• To develop interrupt service routines (ISRs) to
handle interrupts
• To understand the sequence of events that occur
when an IRQ occurs
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Interrupts
• Interrupts are asynchronous changes in program
flow that occur as a result of events outside the
running program
– They are usually hardware related:
• Examples: button press, timer expiration, peripheral device
needs data, etc
– Interrupt conditions are independent of the program:
• Interrupts can happen at any time (asynchronous)
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Why use interrupts?
• As programs (or systems) grow it becomes very
difficult to predict/ensure that time-critical events
are handled properly
– Example:
• An external device sends data to the processor
• The processor must read the data before that data is
overwritten
– This is typical in serial data transmission
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Maskable/Non-maskable
• Interrupts in general can be divided into two
kinds- maskable and non-maskable.
– A maskable interrupt is an interrupt whose trigger
event is not always important:
• The program can decide if the event should be recognized or
ignored and can be disabled/enabled
– A non-maskable interrupt is so important that it should
never be ignored
• The processor will always jump to this interrupt when it
happens
• The reset button is an example
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Interrupts on the ATmega128
• External interrupt inputs are pins INT7 - INT0
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– They are triggered by:
• A high-to-low transition (a falling edge) on one of these
pins
• A low-to-high transition (a rising edge) on one of these
pins
• A low level on one of these pins
– They are initialized by:
• External Interrupt Control Registers
– EICRA for INT3:0
– EICRB for INT7:4
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EICRA INT3 - 0
• External Interrupt Control Register A
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INT3 Control
INT2 Control
INT1 Control
INT0 Control
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EICRA INT3 - 0
• External Interrupt Control Register A
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INT3 Control
INT2 Control
INT1 Control
INT0 Control
If initialized for low-level triggering, the pin must be held low for a minimum of 50 ns
AND until the most recent instruction is completed.
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EICRA INT3 - 0
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Exercise: What value must be stored in EICRA to initialize INT3 and INT0 for
low-to-high transitions, INT2 for low level, and INT1 for high-to—low
transitions?
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EICRA INT3 - 0
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1 1 0 0 1 0 1 1
Exercise: What value must be stored in EICRA to initialize INT3 and INT0 for
low-to-high transitions, INT2 for low level, and INT1 for high-to-low transitions?
Ans: 1100 1011 or $CB
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Pins
• INT3:0
External Interrupts 3 – 0 are
alternate functions of Port D
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Pins
• INT3:0
External Interrupts 3 – 0 are
alternate functions of Port D
They are enabled if the I-flag
in the Status Register is set
(1) and the corresponding
interrupt mask bit in the
EIMSK is set (1).
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Pins
• INT3:0
When the appropriate signal transition occurs on one of the external interrupt pins
(INT7:0) an interrupt request (IRQ) is triggered and the corresponding bit in the
EIFR register (Interrupt Flag Register) gets set.
The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
These flags are always cleared when INT7:0 are configured as level interrupt.
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Pins
• INT3:0
Exercise: I want to clear the flag for INT1 (the others I don’t want to change). What
value must I write to this register?
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Pins
• INT3:0
Exercise: I want to clear the flag for INT1 (the others I don’t want to change). What
value must I write to this register?
Ans: 0000 0010 or $02
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EICRB INT7 - 4
• External Interrupt Control Register B
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INT3 Control
INT2 Control
INT1 Control
INT0 Control
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Pins
• Bits 7 - 4
External Interrupts 7 – 4 are
alternate functions of Port E
They are enabled if the I-flag
in the Status Register is set
(1) and the corresponding
interrupt mask bit in the
EIMSK is set (1).
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Vectors
The complete vector table is
shown on page 60 of the
“Complete ATmega128
Manual”
When an interrupt occurs
the hardware clears the
corresponding interrupt
flag and the Program
Counter is “vectored” to the
actual interrupt vector in
order to execute the
interrupt handling routine.
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Vectors
The complete vector table is
shown on page 60 of the
“Complete ATmega128
Manual”
When an interrupt occurs
the hardware clears the
corresponding interrupt
flag and the Program
Counter is “vectored” to the
actual interrupt vector in
order to execute the
interrupt handling routine.
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This is very different from other processors. In most
microcontrollers, the interrupt vector HOLDS THE
ADDRESS OF THE 1 ST INSTRUCTION OF THE ISR
(OR INTERRUPT HANDLER) not an instruction to
jump to it
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Vectors
The complete vector table is
shown on page 60 of the
“Complete ATmega128
Manual”
When an interrupt occurs
the hardware clears the
corresponding interrupt
flag and the Program
Counter is “vectored” to the
actual interrupt vector in
order to execute the
interrupt handling routine.
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Address Instruction Operand Comment
$0000 jmp RESET ; Reset Handler
$0002 jmp EXT_INT0 ; IRQ0 Handler
$0004 jmp EXT_INT1 ; IRQ1 Handler
$0006 jmp EXT_INT2 ; IRQ2 Handler
$0008 jmp EXT_INT3 ; IRQ3 Handler
$000A jmp EXT_INT4 ; IRQ4 Handler
$000C jmp EXT_INT5 ; IRQ5 Handler
$000E jmp EXT_INT6 ; IRQ6 Handler
$0010 jmp EXT_INT7 ; IRQ7 Handler
The manual states that this is “the most typical and
general program setup for the Reset and Interrupt
Vector Addresses in the ATmega128.” This indicates
that when an interrupt occurs, the program counter is
loaded with these addresses (i.e.; $0002 for an IRQ on
INT0, or $000E for an IRQ on INT6)
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An Example:
• So, let’s work through an example:
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– Assume we have a switch attached to PD0 that will
cause a high-to-low transition
– We want the signal to interrupt the processor and
execute our ISR
• So, we must write a initialization routine that will
allow this interrupt to occur
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An Example:
• So, let’s work through an example:
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– Assume we have a switch attached to PD0 that will
cause a high-to-low transition
– We want the signal to interrupt the processor and
execute our ISR
• So, we must write a initialization routine that will
allow this interrupt to occur
Exercise: What must the first two instructions be for our program?
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An Example:
We must start our program
with at least the first two
instructions (I included all of
the external interrupt
vectors so this can be used as
a template).
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$0000 jmp RESET ; Reset Handler
$0002 jmp EXT_INT0 ; IRQ0 Handler
$0004 jmp EXT_INT1 ; IRQ1 Handler
$0006 jmp EXT_INT2 ; IRQ2 Handler
$0008 jmp EXT_INT3 ; IRQ3 Handler
$000A jmp EXT_INT4 ; IRQ4 Handler
$000C jmp EXT_INT5 ; IRQ5 Handler
$000E jmp EXT_INT6 ; IRQ6 Handler
$0010 jmp EXT_INT7 ; IRQ7 Handler
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An Example:
We need to write the
initialization part of the
program and setup the stack
(use of the stack is required
when using interrupts)
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$0000 jmp RESET ; Reset Handler
$0002 jmp EXT_INT0 ; IRQ0 Handler
$0004 jmp EXT_INT1 ; IRQ1 Handler
$0006 jmp EXT_INT2 ; IRQ2 Handler
$0008 jmp EXT_INT3 ; IRQ3 Handler
$000A jmp EXT_INT4 ; IRQ4 Handler
$000C jmp EXT_INT5 ; IRQ5 Handler
$000E jmp EXT_INT6 ; IRQ6 Handler
$0010 jmp EXT_INT7 ; IRQ7 Handler
RESET: initialization instructions
ldi r21,low(RAMEND) ;setup the stack
out SPL,r21
ldi r21,high(RAMEND)
out SPH,r21
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An Example:
We need to write the
initialization part of the
program and setup the stack
(use of the stack is required
when using interrupts)
Start to initialize the
interrupt: set it up for the
high-to-low transition
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$0000 jmp RESET ; Reset Handler
$0002 jmp EXT_INT0 ; IRQ0 Handler
$0004 jmp EXT_INT1 ; IRQ1 Handler
$0006 jmp EXT_INT2 ; IRQ2 Handler
$0008 jmp EXT_INT3 ; IRQ3 Handler
$000A jmp EXT_INT4 ; IRQ4 Handler
$000C jmp EXT_INT5 ; IRQ5 Handler
$000E jmp EXT_INT6 ; IRQ6 Handler
$0010 jmp EXT_INT7 ; IRQ7 Handler
RESET: initialization instructions
ldi r21,low(RAMEND) ;setup the stack
out SPL,r21
ldi r21,high(RAMEND)
out SPH,r21
ldi r21,obxxxxxx10
out EICRA,r21 ;H-to-L on INT0
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EICRA INT3 - 0
• External Interrupt Control Register A
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INT3 Control
INT2 Control
For a high-to-low transition (falling edge) we need a “10”
INT1 Control
INT0 Control
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An Example:
We must start our program
with these instructions.
We need to write the
initialization part of the
program and setup the stack
(use of the stack is required
when using interrupts)
Start the initialize the
interrupt: set it up for the
high-to-low transition
Enable the interrupt
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$0000 jmp RESET ; Reset Handler
$0002 jmp EXT_INT0 ; IRQ0 Handler
$0004 jmp EXT_INT1 ; IRQ1 Handler
$0006 jmp EXT_INT2 ; IRQ2 Handler
$0008 jmp EXT_INT3 ; IRQ3 Handler
$000A jmp EXT_INT4 ; IRQ4 Handler
$000C jmp EXT_INT5 ; IRQ5 Handler
$000E jmp EXT_INT6 ; IRQ6 Handler
$0010 jmp EXT_INT7 ; IRQ7 Handler
RESET: initialization instructions
ldi r21,low(RAMEND) ;setup the stack
out SPL,r21
ldi r21,high(RAMEND)
out SPH,r21
ldi r21,obxxxxxx10
out EICRA,r21 ;H-to-L on INT0
ldi r21,0bxxxxxxx1
out EIMSK,r21 ;set INT0 Mask
sei ;set Global Int Mask
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An Example:
We must start our program
with these instructions.
We need to write the
initialization part of the
program and setup the stack
(use of the stack is required
when using interrupts)
Start the initialize the
interrupt: set it up for the
high-to-low transition
Enable the interrupt
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$0000 jmp RESET ; Reset Handler
$0002 jmp EXT_INT0 ; IRQ0 Handler
$0004 jmp EXT_INT1 ; IRQ1 Handler
$0006 jmp EXT_INT2 ; IRQ2 Handler
$0008 jmp EXT_INT3 ; IRQ3 Handler
$000A jmp EXT_INT4 ; IRQ4 Handler
$000C jmp EXT_INT5 ; IRQ5 Handler
$000E jmp EXT_INT6 ; IRQ6 Handler
$0010 jmp EXT_INT7 ; IRQ7 Handler
RESET: initialization instructions
ldi r21,low(RAMEND) ;setup the stack
out SPL,r21
ldi r21,high(RAMEND)
out SPH,r21
ldi r21,obxxxxxx10
out EICRA,r21 ;H-to-L on INT0
ldi r21,0bxxxxxxx1
out EIMSK,r21 ;set INT0 Mask
sei ;set Global Int Mask
the rest of the main program
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An Example:
Then we must write the code
for the ISR (Interrupt
Handler). It looks very much
like a subroutine, but ends
with the rti (Return from
Interrupt) instruction to get
back to the main program
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EXT_INT0:
push onto stack anything that needs saved
1 st instruction in the Interrupt Handler
:
:
:
pop off the stack (in reverse order)
sei ;set global interrupt flag to re-enable interrupts
rti
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What happens?
• So what happens when an interrupt (IRQ) occurs?
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What happens?
• So what happens when an interrupt (IRQ) occurs?
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1. The high-to-low transition occurs on PD0 (INT0)
2. The current instruction in the program continues to execute, until it
completes
3. Bit 0 in the EIFR (External Interrupt Flag Register) is set
4. The global interrupt bit in the status register is cleared (to disable any more
interrupts)
5. The PC is pushed onto the stack
6. The PC is loaded with $0002
7. The AVR executes the instruction at $0002: the jump to the label
EXT_INT0 so that execution of the interrupt handler can begin
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What happens?
• So what happens when an interrupt (IRQ) occurs?
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8. Then the ISR is executed
1. The INT0 flag in EIFR is cleared
2. If there are any “pushes”, they get executed
9. The remainder of the ISR is executed until (almost) the end
10. Anything pushed onto the stack is popped off in the reverse order
11. The global interrupt flag in the status register is set again to re-enable
interrupts
12. The RTI instruction is executed
1. The INT0 flag in EIFR is set again
13. The “old” address is popped off the stack and loaded into the PC
14. Main program continues execution where it left off
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Summary
• In this topic we:
– Became familiar with interrupts on the AVR
• Maskable and non-maskable
• Initialization
• Triggers
– Developed an interrupt service routine
– Discussed the sequence of events that occur when an
IRQ occurs
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