Current "control" VHDL Code

--- Current "control" VHDL Code
--- Current file name: control.vhd
--- Last Revised: 12/3/2008; 7:15 p.m.
--- Author: WDR
--- Copyright: William D. Richard, Ph.D., 2008
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
use IEEE.STD_LOGIC_UNSIGNED.ALL ;
use IEEE.STD_LOGIC_ARITH.ALL ;
ENTITY control IS
PORT (clk : IN STD_LOGIC ;
opcode : IN STD_LOGIC_VECTOR(4 DOWNTO 0) ;
n_eq_zero : IN STD_LOGIC ;
con : IN STD_LOGIC ;
done : IN STD_LOGIC ;
reset_l : IN STD_LOGIC ;
a_in : OUT STD_LOGIC ;
c_in : OUT STD_LOGIC ;
c_out : OUT STD_LOGIC ;
pc_in : OUT STD_LOGIC ;
pc_out : OUT STD_LOGIC ;
con_in : OUT STD_LOGIC ;
decr : OUT STD_LOGIC ;
ld : OUT STD_LOGIC ;
c1_out : OUT STD_LOGIC ;
c2_out : OUT STD_LOGIC ;
ir_in : OUT STD_LOGIC ;
gra : OUT STD_LOGIC ;
grb : OUT STD_LOGIC ;
grc : OUT STD_LOGIC ;
r_in : OUT STD_LOGIC ;
r_out : OUT STD_LOGIC ;
ba_out : OUT STD_LOGIC ;
md_bus : OUT STD_LOGIC ;
md_rd : OUT STD_LOGIC ;
md_wr : OUT STD_LOGIC ;
md_out : OUT STD_LOGIC ;
ma_in : OUT STD_LOGIC ;
read : OUT STD_LOGIC ;
write : OUT STD_LOGIC ;
add : OUT STD_LOGIC ;
sub : OUT STD_LOGIC ;
andx : OUT STD_LOGIC ;
orx : OUT STD_LOGIC ;
notx : OUT STD_LOGIC ;
neg : OUT STD_LOGIC ;
c_eq_b : OUT STD_LOGIC ;
inc4 : OUT STD_LOGIC ;
shr : OUT STD_LOGIC ;
shra : OUT STD_LOGIC ;
shl : OUT STD_LOGIC ;
shc : OUT STD_LOGIC) ;
END control ;
ARCHITECTURE behavioral of control IS
COMPONENT controlstore

BEGIN
PORT (d : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) ;
address : IN STD_LOGIC_VECTOR(8 DOWNTO 0)) ;
END COMPONENT ;
SIGNAL upc : STD_LOGIC_VECTOR(8 DOWNTO 0) ;
SIGNAL d : STD_LOGIC_VECTOR(47 DOWNTO 0) ;
SIGNAL brcondition : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
SIGNAL braddress : STD_LOGIC_VECTOR(8 DOWNTO 0) ;
clkd:PROCESS(clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (reset_l = '0') THEN
upc

a_out