A CCSDS-Based Communication System for a Single Chip On ...

A CCSDS-Based Communication System for a Single Chip On-Board
Computer
Daixun Zheng
Dr. Tanya Vladimirova
Prof. Martin Sweeting
Surrey Space Centre
University of Surrey
Guildford, Surrey GU2 7XH, UK
This paper will describe the results of a research experiment aiming to implement a simplified
communication system for a small satellite on-board computer (OBC) on a single
reconfigurable programmable logic chip (RSC-OBC) [1] using the Consultative Committee of
Space Data Systems (CCSDS) protocol. The development of the reconfigurable single chip
OBC is part of a long-term research programme at the Surrey Space Centre (SSC) named
“ChipSat”. Other related hardware implementation will also be presented.
Small Satellites aim to achieve low-cost, fast access to space and this is normally supported by
the use of off-the shelf components and development tools. System-on-a-Programmable-chip is
a major enabling technology. Such a single-chip solution to the core data handling,
communications and control systems will not only dramatically reduce size, complexity and
cost of small satellites electronics, but will also allow on-board hardware modification.
A simplified version of a Surrey Satellite Technology Limited (SSTL) on-board computer
(OBC) is in a process of implementation as a system-on-a-chip (SoC) device. A XILINX Virtex
FPGA is used for prototyping of the SoC. This single-chip OBC is composed of
Microprocessor IP Core, Memory Error Detection and Correction Unit, Bootstrap Loader,
HDLC Controller, CAN Interface, Network Interface, True IDE Interface, Cordic Co-Processor
and Peripheral Bus Interface. Synthesis results of the microprocessor and peripheral cores have
been reported in [2].
Being standard space industry communication protocol the Consultative Committee of Space
Data Systems (CCSDS) protocol has been employed on numerous missions ranging from
relatively simple low earth missions to deep space probes. Using the CCSDS standard has
proven important and advantageous since it could lead to spacecraft interoperability, re-usable
systems and mission cross support – not just for in-house missions but across the CCSDS space
agencies members – thereby reducing costs for on-board, group and test equipment, as well as
for spacecraft testing and in-orbit operations.
At present, the complete CCSDS TLM and TC implementation is still very complex for lowcost
small satellites and hardware implementations are expensive. A CCSDS software package
has been developed in SSC which represents a simplified yet reliable standalone alternative
software implementation of the CCSDS TLM and TC Command Operation Protocol (COP-1)
[3]. The COP-1 service is based on a streamlined version of the CCSDS Frame Acceptance and
Report Mechanism (FARM) and Frame Operation Protocol (FOP). Both the FARM and FOP
systems satisfy the essential requirements for a reliable CCSDS communication system. The
software imposes minimal memory footprint and performance requirements on the On-Board
Computer. The CCSDS communication system will implement the Packetisation Layer, the
Transfer Layer and the Coding Layer of both the TC and TLM Systems. The CCSDS Reed-
Solomon (R-S)/Turbo encoder and decoder are used for the TLM Channel Coding. The Bose,
Chaudhuri and Hocquenghem (BCH) cyclic detecting error code is used for the TC coding.
The functions of the ground segment are to format CCSDS TC packets and CCSDS TC frames;
calculate the BCH check; insert TC packets into the Data Field of TC frames; insert TC frames
into Codeblocks; format Control Link Transfer Units (CLTU) to ensure synchronisation;
implement the R-S or Turbo decoding; receive CCSDS TLM frames; subtract CCSDS TLM
1

packets from the Data Field of the TLM frames; decode the CRC and if no error is detected, the
raw TLM data is passed to be analysed and displayed. The functions of the spacecraft segment
are to format CCSDS TLM packets; format CCSDS TLM frames; insert TLM packets into the
Data Field of the TLM frames; calculate the CCSDS recommended Cyclic Redundancy Check
(CRC) cyclic code of the frame inserted at the end of TLM frames; format the Attached
Synchronized Marker (ASM); implement R-S or Turbo encoding; receive and decode CCSDS
TC frames; detect whether a transmission bit error has been identified by the BCH code. If
there is no error, the telecommand will be passed to the on-board Controller Area Network
(CAN) bus and accepted by the corresponding CAN node. The TC retransmission system
utilises the COP-1 "go-back-n" automatic retransmission protocol, which consists of the pair of
synchronized procedures, FOP (in the ground segment) and FARM (in the spacecraft segment).
The FOP transmits TC transfer frames to the FARM. The FARM returns Command Link
Control Words (CLCW) within the TLM transfer frames.
The experimental set-up for the simulation of the CCSDS communication system consists of a
XILINX Virtex 800 FPGA prototyping board supporting the on-board operation and a personal
computer (PC), supporting the ground operation. The on-board segment will be run by the
RSC-OBC. An on-board CAN bus system will be used to verify the validity of the whole
system. The CAN interface is implemented as a VHDL IP core and is integrated with the
LEON processor IP core. An external CAN card will take responsibilities of an on-board
payload which will generate TLM data and receive TC data. The CCSDS TLM encoder and
decoder are provided by the European Space Agency (ESA). The encoder is implemented in
software which will run on the RSC-OBC. The decoder will be implemented as a VHDL core
in a XILINX FPGA. The RSC-OBC will communicate with the PC via an asynchronous RS-
232 serial port.
The paper will be structured in the following way. The CCSDS end-to-end link model will be
overviewed and its TLM and TC simulation models will be presented. The CCSDS software
structure and interfaces will be illustrated. An approach to the simulation of the CCSDS
communication will be outlined. Finally, simulation results will be presented and illustrated.
Refrences:
1. D.Zheng, T.Vladimirova, H.Tiggeler, Prof. Martin Sweeting. “Reconfigurable Single-Chip
On-Board Computer for a Small Satellite”, 52nd International Astronautical Congress,
Toulouse, France, October 1-5, 2001, IAF-01-U3.09.
2. H.Tiggeler, T.Vladimirova, D.Zheng. “A System-on-a-Chip for Small Satellite Data
Processing and Control”, Proceedings of Military and Aerospace Applications of
Programmable Devices and Technologies International Conference (MAPLD’2000), P20,
September 2000, Laurel, Maryland US, NASA.
3. I. Rutter, T.Vladimirova, H.Tiggeler.“A CCSDS Software System for a Single-Chip On-
Board Computer of a Small Satellite”, AIAA Small Satellites Conference, 2001, SSC01-
VI-4.
2