Evaluation of Radiation Effects in Flash Memories Tetsuo Miyahira ...

I. INTRODUCTION
Evaluation of Radiation Effects in Flash Memories
Tetsuo Miyahira and Gary Swift
Jet Propulsion Laboratory, California Institute of Technology
Pasadena, California 91109
Features of flash memories
Flash memories are non-volatile; they do not require
power to retain memory content. They can be
programmed (erased and written to) and can be accessed
(read) at high speed. Longer time periods are required
for erasing and writing. Note that erasing is a blocklevel
function for these devices.
An alternative high-density storage
By using a single transistor memory cell, the flash
memories are currently nearly as dense as DRAMs and
potentially more dense. The development of flash
memories is lagging behind the development of DRAMs
because of the need for high internal voltages for writing
and erasing, but new approaches (such as multi-level
flash memories) are being used which may provide flash
memory densities close to those available with DRAMS.
Flash memories are beginning to be widely used in the
commercial market where they are showing up in
applications such as solid state disks. Flash memories do
have a limited life of about 10 4 to 10 6 erase and write
operations but this is sufficient for many applications.
Power savings
Because flash memories are non-volatile, power to the
device can be turned off when not in use. This saving in
power makes flash memories very attractive to spacecraft
designers. As a side benefit, flash memories are immune
to single event upset when powered off.
Downside of using flash memories
Writing to flash memories is a two step process. The
memory must first be erased as a block, and then written.
A write operation only writes a zero into a memory cell.
A block erase is required to first put all ones into the cells
prior to writing. Flash memories require a long time to
erase and write relative to DRAMs. As an example the
_____________________________
The research in this paper was carried out by the Jet Propulsion
Laboratory, California Institute of Technology, under contract
with the National Aeronautics and Space Administration, Code
AE, under the NASA microelectronics Space Radiation Effects
Program (MSREP)
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Intel 28F016 flash memories requires 20 to 30 seconds to
erase all 16 Mb (32 blocks), and 5 to 8 μs to write to each
cell. However, the time required to read (70 nsec.) is
close to DRAMs.
For space applications the time to erase/write is probably
not the main concern. The main concern would probably
be radiation effects: total dose and single event effects
sensitivity. This paper presents results of irradiation
experiment conducted recently by JPL’s radiation group
on representative flash devices to assess the seriousness
of this concern.
II. SUMMARY
NAND and NOR architecture
Flash memories are based on two architectures (NAND
and NOR). We wanted to examine both architectures so
we chose Samsung flash memories to represent the
NAND architecture and Intel flash memories to represent
the NOR architecture.
Total Integrated Dose (TID) test
Both manufacturers use a charge pump to get the higher
voltage required for programming. The charge pump is
provided for the convenience of the user to allow single
power supply operation. Degradation of the charge pump
from radiation affected these devices, which in turn
affects the programming and erase operations. As
discussed later, the NAND design is inherently more
sensitive to total dose damage than the NOR design.
Single Event Effects (SEE) tests
The memory cells themselves were immune to Single
Event Upsets (SEUs) but the memory erase, write, and
read electronics were sensitive to Single Event
Functional Interrupts (SEFIs). No individual stuck bits
were observed but there were three incidents, only with
the Intel 28F016, where functionality problems resulted
in a permanent damage to the devices. Both the
Samsung NAND and the Intel NOR devices had similar
SEU results with the exception of a permanent damage
effect that occurred only on the Intel device.

III. NAND and NOR architecture
The diagram entitled “NAND and NOR Architecture”
contrasts the basic cell structure of both the Samsung
NAND and the Intel NOR flash memories. The cell
structure is very similar to a MOS transistor except for
the floating gate. By adding or removing charge on this
floating gate one can turn on or off the transistor. A
positive charge on the floating gate relative to the source
turns on the device and a negative charge turns it off.
Because the floating gate is electrically isolated, it retains
its charge indefinitely and hence the cell’s non-volatility.
For both the Intel and Samsung devices, erasing is done
by the mechanism of Fowler-Nordheim tunneling. For
both device types, the control gate is grounded. In the
case of the Samsung device, programming voltage is
applied to the substrate, but for the Intel device,
programming voltage is applied to the source. The
electric field generated causes electrons to tunnel away
from the floating gate making it more positive and
turning the transistor on.
Samsung devices also use a form of tunneling for writing
of individual floating gates. For writing, the P-well and
the N-Substrate are grounded and programming voltage
is applied to the control gate. The voltage on the control
gate is capacitively coupled to the floating gate, which
creates an electric field that causes electrons to tunnel
from the P-well to the floating gate making it more
negative turning off the transistor.
For Intel devices, Channel Hot Electron (CHE) injection
is used to program individual transistors. For this
approach the source is grounded; the control gate has
programming voltage (Vpp) applied to it while the drain
gets approximately half of the programming voltage
applied to it. The voltage on the control gate is
capacitively coupled to the floating gate. This turns the
transistor on and causes the current (electrons) to flow
from the source to drain. Some of these electrons will
have sufficient energy (~3.1eV) to pass through the oxide
charging the floating gate. Electrons deposited on the
floating gate charge the gate negatively and turns off the
transistor.
Both manufacturers use charge pumps to get the higher
voltages required to program (erase and write) the
memory cells. As mentioned earlier, the charge pump is
sensitive to radiation damage. The Intel 28F016 devices
allow programming to be done with or without the
charge pump. In the latter case, programming voltage is
applied using an external supply. This flexibility allowed
us to evaluate the radiation tolerance of the charge pump
by contrasting both options: using the charge pump and
bypassing the charge pump. Unfortunately, Intel has
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eliminated the option of externally supplying
programming power in its higher density (32 Mb or
greater) parts.
As in any MOS device, trapped charge in the oxide will
cause a shift in the threshold voltage. The trapped
charge from erase and write operations limits the number
of erase/write operations allowable by these devices. The
additional effect of trapped charges from ionizing
radiation will also cause the device to fail. To date there
is little data on the combined effect of the two failure
mechanisms.
The NAND architecture typically uses eight or sixteen
cells that are stacked in series with a common bit line.
While this arrangement allows for a more compact
design, it does cause the device to be more sensitive to
radiation damage since radiation-induced leakage will
add together.
IV. TID RESULTS
TID failure of Intel and Samsung flash memories
The data displayed in chart entitled “Total Dose Failure
Levels” is the result of testing on six test devices from the
two manufacturers. The devices were irradiated with
Co 60 at room temperature at a rate of 25 rads/sec. The
devices were statically biased with both Vpp and Vdd at
5V.
As this graph indicates, the Intel NOR flash memory did
not fail until 100 krad(Si) when tested bypassing the
internal charge pump. An external supply was used to
supply programming voltage for this mode. However
when the Intel device was tested using the internal
charge pump, they failed at ~24 krads. The Samsung
NAND flash memory which had no provision for
bypassing the charge pump failed at ~10 krads. Based on
the results from the Intel tests, with and without the
charge pump, it is clear that the charge pump has a
significant effect on radiation hardness. The data also
suggest that the NAND architecture is more susceptible
to TID damage than the NOR architecture.
Time to erase using internal charge pump vs. using
external supply
The plot entitled “Time Required to Erase only” includes
data from Intel devices because Samsung devices had no
provisions for bypassing the charge pump. When the
Intel flash memories were tested with the charge pump
bypassed, the data showed no degradation in erase time
up to 30 krad(Si). When the internal charge pump was
used, the time to erase increased from 30 seconds at pre-

irradiation to 143 seconds at 12 krads for the worst of the
six test devices.
Supply current (Idd) degradation
In the plot entitled “Supply Current (Idd)” shows that Idd
for the Samsung device began to rise rapidly at about 8
krads and the device failed functionally at about ~10
krads. Idd for the Intel device began to rise rapidly at
about 20 krads and the device failed functionally at
~24 krads.
V. SEU RESULTS
SEU Tests
Unpowered mode. The purpose of this test was to
determine if the floating gate would upset with heavy
ions. Flash memories use an embedded microcontroller
to improve erase/write times. The device was left
unpowered, during irradiation, to prevent upsets in the
microcontroller, which in turn could cause an upsets in
the memory cells. The memory was loaded with a known
pattern prior to the test and left unpowered while being
irradiated with heavy ions. After the irradiation, the
device was powered and tested to see if there were any
changes to the pattern. No cell upset occurred when
tested in this mode even up to an effective LET of 120
MeV-cm 2 /mg.
Static mode. For this mode, the flash memory was
powered but there was no active addressing taking place
during irradiation. Most of the testing was done using
this mode. Before the irradiation, the device was loaded
with a known pattern and at the completion of the
irradiation, the device was tested to see if the memory
content had changed. When testing in this mode,
functional interrupts (SEFIs) would occur that in most
cases required power cycling (turning Vdd off and then on
again) to clear the error condition. We were able to
identify seven error modes (lockup conditions). Besides
the seven error modes, three Intel devices had
catastrophic high current condition that occurred during
functionality test after the irradiation was completed. We
did not experience this catastrophic high current
condition with the Samsung memories.
We had no visibility of functionality during irradiation,
because we were not addressing the test device when
tested in the static mode. Each irradiation run therefore
became a pass or fail test. In order to determine a cross
section, we selected fluence so that some of the runs
resulted in a SEFI and some did not. Cross section was
determined by adding the number of SEFIs then dividing
by the total fluence (passes as well as fails). The plot of
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the cross section as a function of LET for the Intel
28F016SV is shown on the graph entitled “Cross Section
for Complex Functional Upset Modes.” The error bars
are large because we did not know at what point during
the irradiation the SEFI occurred or if more than one
SEFI occurred during that run.
Read mode and erase/write mode. Most of the time
was spent testing in the static mode. The results from
tests in read and erase/write modes were too limited to
include in this paper. We will address these modes
further in future tests.
Isolating the memory array
We used a copper shield to mask off the microcontroller.
The diagram entitled “Chip Micrograph” shows the area
that was masked from the heavy ions. This was done to
see if memory upsets would still occur. We got mixed
results from this test, possibly because the sensing and
high voltage circuitry was interspersed with the memory
array, and could not be masked. With the Intel
28F016SA memories, we observed no errors. The
28F016SV (smart voltage) devices, however, did appear
to exhibit memory errors at very high LET. However,
the cross section was very low, and it is likely that the
apparent memory errors are caused by the response of the
more complex SV microcontroller. According to the
manufacturer, the SV and SA memory cell technologies
are identical and should have behaved similarly.
VI. PLAN FOR FOLLOW ON TESTS
X2000 Project
X2000 Project is driving the flash memory survey. There
are currently five missions proposed for X2000 project
(Europa, Pluto, Solar Probe, Champollion, and a Mars
mission). The Radiation Effects Group at JPL is
primarily concerned with the Europa spacecraft because
of its severe radiation environment. The Europa
spacecraft is expected to be exposed to mostly electron
dose of about four megarad(Si), behind 100 mils of
aluminum. Design trade studies indicate that it is
possible to shield to about 40 krad(Si) in order to gain the
advantages of using commercial flash and /or DRAMS as
opposed to using an all radiation hardened SRAM. If we
are able to find a suitable flash memory, the X2000
modular architecture needs at least one giga-bit and
would like eight giga-bits of flash memory for each
spacecraft. The follow-on flash memory evaluation will
be done in three steps, as described below.
Single Event Latchup (SEL) test and cursory Single
Event Upset (SEU) tests

The first test is planned for first quarter of FY99.
(October/November time frame). We are in the process
of purchasing flash memories from several
manufacturers, including denser Samsung and Intel
devices (32 Mb or larger). The Intel devices to be tested
are a new multi-level technology where each transistor
stores two bits.
TID test on most of the devices
We plan to test all of the devices that were tested for
latchup, unless the SEL data shows a significant reason
to omit the device from the test matrix
Detailed SEU evaluation
We plan to select two devices based on the SEL and TID
test results and perform a detailed SEU evaluation using
a new test system currently in development. A new test
system currently being developed will be capable of
capturing detailed information on each upset and/or SEFI
under software control.
New PCI-based test system
The new test system is much faster than the current
system and will allow one to scan through the memory
more quickly and therefore provide a more complete SEU
evaluation. The new system is based on the 33 MHz, 32bit
PCI bus instead of the 8 MHz, 16-bit ISA bus, which
the current system uses. It is expected that an order of
magnitude increase in performance will be gained.
VII. Conclusions
TID conclusions
• NOR architecture is inherently more robust.
• Internal charge pump is particularly susceptible.
• Parameters most sensitive to damage are erase/write
time.
• When the charge pump is bypassed the operating
current is the most sensitive parameter.
SEL conclusions
• There are enough commercial manufacturers that
some will have SEL immunity.
SEU conclusions
• The memory cells are robust.
• “Smarter” control logic increases SEU error modes
and susceptibility.
• With the exception of the catastrophic high current
condition that occurred only with the Intel devices,
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devices from both manufacturers had similar SEU
results.
Unfortunately COTS is driving the market towards more
radiation sensitivity.
• External program supply option is being eliminated.
• Inherently more sensitive NAND architecture is
being used by more manufacturers.
• Control logic is becoming “smarter” adding more
registers and, thus, SEU susceptibility.
VIII. Acknowledgements
Significant efforts and contributions to this paper by
other (past and present) members of JPL’s Radiation
Effects Group are gratefully acknowledged: Larry
Edmonds, Steve Guertin, Allan Johnston, Choon Lee,
Don Nichols, Duc Nguyen, Michael O’Connor, Bernie
Rax, Luis Selva, Harvey Schwartz, and Mike Wiedeman.
IX. References
[1] D. N. Nguyen, C. I. Lee, and A. H. Johnston, “Total
Ionizing Dose Effects on Flash Memories,” 1998 IEEE
Radiation Effects Data Workshop, p. 100.
[2] H. R. Schwartz and D. K. Nichols, “Single-Event
Upset in Flash Memories,” IEEE Transactions on
Nuclear Science, Vol. 44, p. 2315.

NAND and NOR Architectures
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